timing.cc revision 12386:2bf5fb25a5f1
1/* 2 * Copyright 2014 Google, Inc. 3 * Copyright (c) 2010-2013,2015,2017 ARM Limited 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2002-2005 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 */ 43 44#include "cpu/simple/timing.hh" 45 46#include "arch/locked_mem.hh" 47#include "arch/mmapped_ipr.hh" 48#include "arch/utility.hh" 49#include "config/the_isa.hh" 50#include "cpu/exetrace.hh" 51#include "debug/Config.hh" 52#include "debug/Drain.hh" 53#include "debug/ExecFaulting.hh" 54#include "debug/Mwait.hh" 55#include "debug/SimpleCPU.hh" 56#include "mem/packet.hh" 57#include "mem/packet_access.hh" 58#include "params/TimingSimpleCPU.hh" 59#include "sim/faults.hh" 60#include "sim/full_system.hh" 61#include "sim/system.hh" 62 63using namespace std; 64using namespace TheISA; 65 66void 67TimingSimpleCPU::init() 68{ 69 BaseSimpleCPU::init(); 70} 71 72void 73TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 74{ 75 pkt = _pkt; 76 cpu->schedule(this, t); 77} 78 79TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 80 : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 81 dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 82 fetchEvent([this]{ fetch(); }, name()) 83{ 84 _status = Idle; 85} 86 87 88 89TimingSimpleCPU::~TimingSimpleCPU() 90{ 91} 92 93DrainState 94TimingSimpleCPU::drain() 95{ 96 // Deschedule any power gating event (if any) 97 deschedulePowerGatingEvent(); 98 99 if (switchedOut()) 100 return DrainState::Drained; 101 102 if (_status == Idle || 103 (_status == BaseSimpleCPU::Running && isDrained())) { 104 DPRINTF(Drain, "No need to drain.\n"); 105 activeThreads.clear(); 106 return DrainState::Drained; 107 } else { 108 DPRINTF(Drain, "Requesting drain.\n"); 109 110 // The fetch event can become descheduled if a drain didn't 111 // succeed on the first attempt. We need to reschedule it if 112 // the CPU is waiting for a microcode routine to complete. 113 if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 114 schedule(fetchEvent, clockEdge()); 115 116 return DrainState::Draining; 117 } 118} 119 120void 121TimingSimpleCPU::drainResume() 122{ 123 assert(!fetchEvent.scheduled()); 124 if (switchedOut()) 125 return; 126 127 DPRINTF(SimpleCPU, "Resume\n"); 128 verifyMemoryMode(); 129 130 assert(!threadContexts.empty()); 131 132 _status = BaseSimpleCPU::Idle; 133 134 for (ThreadID tid = 0; tid < numThreads; tid++) { 135 if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 136 threadInfo[tid]->notIdleFraction = 1; 137 138 activeThreads.push_back(tid); 139 140 _status = BaseSimpleCPU::Running; 141 142 // Fetch if any threads active 143 if (!fetchEvent.scheduled()) { 144 schedule(fetchEvent, nextCycle()); 145 } 146 } else { 147 threadInfo[tid]->notIdleFraction = 0; 148 } 149 } 150 151 // Reschedule any power gating event (if any) 152 schedulePowerGatingEvent(); 153 154 system->totalNumInsts = 0; 155} 156 157bool 158TimingSimpleCPU::tryCompleteDrain() 159{ 160 if (drainState() != DrainState::Draining) 161 return false; 162 163 DPRINTF(Drain, "tryCompleteDrain.\n"); 164 if (!isDrained()) 165 return false; 166 167 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 168 signalDrainDone(); 169 170 return true; 171} 172 173void 174TimingSimpleCPU::switchOut() 175{ 176 SimpleExecContext& t_info = *threadInfo[curThread]; 177 M5_VAR_USED SimpleThread* thread = t_info.thread; 178 179 BaseSimpleCPU::switchOut(); 180 181 assert(!fetchEvent.scheduled()); 182 assert(_status == BaseSimpleCPU::Running || _status == Idle); 183 assert(!t_info.stayAtPC); 184 assert(thread->microPC() == 0); 185 186 updateCycleCounts(); 187 updateCycleCounters(BaseCPU::CPU_STATE_ON); 188} 189 190 191void 192TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 193{ 194 BaseSimpleCPU::takeOverFrom(oldCPU); 195 196 previousCycle = curCycle(); 197} 198 199void 200TimingSimpleCPU::verifyMemoryMode() const 201{ 202 if (!system->isTimingMode()) { 203 fatal("The timing CPU requires the memory system to be in " 204 "'timing' mode.\n"); 205 } 206} 207 208void 209TimingSimpleCPU::activateContext(ThreadID thread_num) 210{ 211 DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 212 213 assert(thread_num < numThreads); 214 215 threadInfo[thread_num]->notIdleFraction = 1; 216 if (_status == BaseSimpleCPU::Idle) 217 _status = BaseSimpleCPU::Running; 218 219 // kick things off by initiating the fetch of the next instruction 220 if (!fetchEvent.scheduled()) 221 schedule(fetchEvent, clockEdge(Cycles(0))); 222 223 if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 224 == activeThreads.end()) { 225 activeThreads.push_back(thread_num); 226 } 227 228 BaseCPU::activateContext(thread_num); 229} 230 231 232void 233TimingSimpleCPU::suspendContext(ThreadID thread_num) 234{ 235 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 236 237 assert(thread_num < numThreads); 238 activeThreads.remove(thread_num); 239 240 if (_status == Idle) 241 return; 242 243 assert(_status == BaseSimpleCPU::Running); 244 245 threadInfo[thread_num]->notIdleFraction = 0; 246 247 if (activeThreads.empty()) { 248 _status = Idle; 249 250 if (fetchEvent.scheduled()) { 251 deschedule(fetchEvent); 252 } 253 } 254 255 BaseCPU::suspendContext(thread_num); 256} 257 258bool 259TimingSimpleCPU::handleReadPacket(PacketPtr pkt) 260{ 261 SimpleExecContext &t_info = *threadInfo[curThread]; 262 SimpleThread* thread = t_info.thread; 263 264 RequestPtr req = pkt->req; 265 266 // We're about the issues a locked load, so tell the monitor 267 // to start caring about this address 268 if (pkt->isRead() && pkt->req->isLLSC()) { 269 TheISA::handleLockedRead(thread, pkt->req); 270 } 271 if (req->isMmappedIpr()) { 272 Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 273 new IprEvent(pkt, this, clockEdge(delay)); 274 _status = DcacheWaitResponse; 275 dcache_pkt = NULL; 276 } else if (!dcachePort.sendTimingReq(pkt)) { 277 _status = DcacheRetry; 278 dcache_pkt = pkt; 279 } else { 280 _status = DcacheWaitResponse; 281 // memory system takes ownership of packet 282 dcache_pkt = NULL; 283 } 284 return dcache_pkt == NULL; 285} 286 287void 288TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 289 bool read) 290{ 291 SimpleExecContext &t_info = *threadInfo[curThread]; 292 SimpleThread* thread = t_info.thread; 293 294 PacketPtr pkt = buildPacket(req, read); 295 pkt->dataDynamic<uint8_t>(data); 296 if (req->getFlags().isSet(Request::NO_ACCESS)) { 297 assert(!dcache_pkt); 298 pkt->makeResponse(); 299 completeDataAccess(pkt); 300 } else if (read) { 301 handleReadPacket(pkt); 302 } else { 303 bool do_access = true; // flag to suppress cache access 304 305 if (req->isLLSC()) { 306 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 307 } else if (req->isCondSwap()) { 308 assert(res); 309 req->setExtraData(*res); 310 } 311 312 if (do_access) { 313 dcache_pkt = pkt; 314 handleWritePacket(); 315 threadSnoop(pkt, curThread); 316 } else { 317 _status = DcacheWaitResponse; 318 completeDataAccess(pkt); 319 } 320 } 321} 322 323void 324TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 325 RequestPtr req, uint8_t *data, bool read) 326{ 327 PacketPtr pkt1, pkt2; 328 buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 329 if (req->getFlags().isSet(Request::NO_ACCESS)) { 330 assert(!dcache_pkt); 331 pkt1->makeResponse(); 332 completeDataAccess(pkt1); 333 } else if (read) { 334 SplitFragmentSenderState * send_state = 335 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 336 if (handleReadPacket(pkt1)) { 337 send_state->clearFromParent(); 338 send_state = dynamic_cast<SplitFragmentSenderState *>( 339 pkt2->senderState); 340 if (handleReadPacket(pkt2)) { 341 send_state->clearFromParent(); 342 } 343 } 344 } else { 345 dcache_pkt = pkt1; 346 SplitFragmentSenderState * send_state = 347 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 348 if (handleWritePacket()) { 349 send_state->clearFromParent(); 350 dcache_pkt = pkt2; 351 send_state = dynamic_cast<SplitFragmentSenderState *>( 352 pkt2->senderState); 353 if (handleWritePacket()) { 354 send_state->clearFromParent(); 355 } 356 } 357 } 358} 359 360void 361TimingSimpleCPU::translationFault(const Fault &fault) 362{ 363 // fault may be NoFault in cases where a fault is suppressed, 364 // for instance prefetches. 365 updateCycleCounts(); 366 updateCycleCounters(BaseCPU::CPU_STATE_ON); 367 368 if (traceData) { 369 // Since there was a fault, we shouldn't trace this instruction. 370 delete traceData; 371 traceData = NULL; 372 } 373 374 postExecute(); 375 376 advanceInst(fault); 377} 378 379PacketPtr 380TimingSimpleCPU::buildPacket(RequestPtr req, bool read) 381{ 382 return read ? Packet::createRead(req) : Packet::createWrite(req); 383} 384 385void 386TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 387 RequestPtr req1, RequestPtr req2, RequestPtr req, 388 uint8_t *data, bool read) 389{ 390 pkt1 = pkt2 = NULL; 391 392 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 393 394 if (req->getFlags().isSet(Request::NO_ACCESS)) { 395 pkt1 = buildPacket(req, read); 396 return; 397 } 398 399 pkt1 = buildPacket(req1, read); 400 pkt2 = buildPacket(req2, read); 401 402 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 403 404 pkt->dataDynamic<uint8_t>(data); 405 pkt1->dataStatic<uint8_t>(data); 406 pkt2->dataStatic<uint8_t>(data + req1->getSize()); 407 408 SplitMainSenderState * main_send_state = new SplitMainSenderState; 409 pkt->senderState = main_send_state; 410 main_send_state->fragments[0] = pkt1; 411 main_send_state->fragments[1] = pkt2; 412 main_send_state->outstanding = 2; 413 pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 414 pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 415} 416 417Fault 418TimingSimpleCPU::readMem(Addr addr, uint8_t *data, 419 unsigned size, Request::Flags flags) 420{ 421 panic("readMem() is for atomic accesses, and should " 422 "never be called on TimingSimpleCPU.\n"); 423} 424 425Fault 426TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, 427 Request::Flags flags) 428{ 429 SimpleExecContext &t_info = *threadInfo[curThread]; 430 SimpleThread* thread = t_info.thread; 431 432 Fault fault; 433 const int asid = 0; 434 const Addr pc = thread->instAddr(); 435 unsigned block_size = cacheLineSize(); 436 BaseTLB::Mode mode = BaseTLB::Read; 437 438 if (traceData) 439 traceData->setMem(addr, size, flags); 440 441 RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, 442 thread->contextId()); 443 444 req->taskId(taskId()); 445 446 Addr split_addr = roundDown(addr + size - 1, block_size); 447 assert(split_addr <= addr || split_addr - addr < block_size); 448 449 _status = DTBWaitResponse; 450 if (split_addr > addr) { 451 RequestPtr req1, req2; 452 assert(!req->isLLSC() && !req->isSwap()); 453 req->splitOnVaddr(split_addr, req1, req2); 454 455 WholeTranslationState *state = 456 new WholeTranslationState(req, req1, req2, new uint8_t[size], 457 NULL, mode); 458 DataTranslation<TimingSimpleCPU *> *trans1 = 459 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 460 DataTranslation<TimingSimpleCPU *> *trans2 = 461 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 462 463 thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 464 thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 465 } else { 466 WholeTranslationState *state = 467 new WholeTranslationState(req, new uint8_t[size], NULL, mode); 468 DataTranslation<TimingSimpleCPU *> *translation 469 = new DataTranslation<TimingSimpleCPU *>(this, state); 470 thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 471 } 472 473 return NoFault; 474} 475 476bool 477TimingSimpleCPU::handleWritePacket() 478{ 479 SimpleExecContext &t_info = *threadInfo[curThread]; 480 SimpleThread* thread = t_info.thread; 481 482 RequestPtr req = dcache_pkt->req; 483 if (req->isMmappedIpr()) { 484 Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 485 new IprEvent(dcache_pkt, this, clockEdge(delay)); 486 _status = DcacheWaitResponse; 487 dcache_pkt = NULL; 488 } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 489 _status = DcacheRetry; 490 } else { 491 _status = DcacheWaitResponse; 492 // memory system takes ownership of packet 493 dcache_pkt = NULL; 494 } 495 return dcache_pkt == NULL; 496} 497 498Fault 499TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 500 Addr addr, Request::Flags flags, uint64_t *res) 501{ 502 SimpleExecContext &t_info = *threadInfo[curThread]; 503 SimpleThread* thread = t_info.thread; 504 505 uint8_t *newData = new uint8_t[size]; 506 const int asid = 0; 507 const Addr pc = thread->instAddr(); 508 unsigned block_size = cacheLineSize(); 509 BaseTLB::Mode mode = BaseTLB::Write; 510 511 if (data == NULL) { 512 assert(flags & Request::STORE_NO_DATA); 513 // This must be a cache block cleaning request 514 memset(newData, 0, size); 515 } else { 516 memcpy(newData, data, size); 517 } 518 519 if (traceData) 520 traceData->setMem(addr, size, flags); 521 522 RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, 523 thread->contextId()); 524 525 req->taskId(taskId()); 526 527 Addr split_addr = roundDown(addr + size - 1, block_size); 528 assert(split_addr <= addr || split_addr - addr < block_size); 529 530 _status = DTBWaitResponse; 531 if (split_addr > addr) { 532 RequestPtr req1, req2; 533 assert(!req->isLLSC() && !req->isSwap()); 534 req->splitOnVaddr(split_addr, req1, req2); 535 536 WholeTranslationState *state = 537 new WholeTranslationState(req, req1, req2, newData, res, mode); 538 DataTranslation<TimingSimpleCPU *> *trans1 = 539 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 540 DataTranslation<TimingSimpleCPU *> *trans2 = 541 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 542 543 thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 544 thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 545 } else { 546 WholeTranslationState *state = 547 new WholeTranslationState(req, newData, res, mode); 548 DataTranslation<TimingSimpleCPU *> *translation = 549 new DataTranslation<TimingSimpleCPU *>(this, state); 550 thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 551 } 552 553 // Translation faults will be returned via finishTranslation() 554 return NoFault; 555} 556 557void 558TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 559{ 560 for (ThreadID tid = 0; tid < numThreads; tid++) { 561 if (tid != sender) { 562 if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 563 wakeup(tid); 564 } 565 TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt, 566 dcachePort.cacheBlockMask); 567 } 568 } 569} 570 571void 572TimingSimpleCPU::finishTranslation(WholeTranslationState *state) 573{ 574 _status = BaseSimpleCPU::Running; 575 576 if (state->getFault() != NoFault) { 577 if (state->isPrefetch()) { 578 state->setNoFault(); 579 } 580 delete [] state->data; 581 state->deleteReqs(); 582 translationFault(state->getFault()); 583 } else { 584 if (!state->isSplit) { 585 sendData(state->mainReq, state->data, state->res, 586 state->mode == BaseTLB::Read); 587 } else { 588 sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 589 state->data, state->mode == BaseTLB::Read); 590 } 591 } 592 593 delete state; 594} 595 596 597void 598TimingSimpleCPU::fetch() 599{ 600 // Change thread if multi-threaded 601 swapActiveThread(); 602 603 SimpleExecContext &t_info = *threadInfo[curThread]; 604 SimpleThread* thread = t_info.thread; 605 606 DPRINTF(SimpleCPU, "Fetch\n"); 607 608 if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 609 checkForInterrupts(); 610 checkPcEventQueue(); 611 } 612 613 // We must have just got suspended by a PC event 614 if (_status == Idle) 615 return; 616 617 TheISA::PCState pcState = thread->pcState(); 618 bool needToFetch = !isRomMicroPC(pcState.microPC()) && 619 !curMacroStaticInst; 620 621 if (needToFetch) { 622 _status = BaseSimpleCPU::Running; 623 Request *ifetch_req = new Request(); 624 ifetch_req->taskId(taskId()); 625 ifetch_req->setContext(thread->contextId()); 626 setupFetchRequest(ifetch_req); 627 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 628 thread->itb->translateTiming(ifetch_req, thread->getTC(), 629 &fetchTranslation, BaseTLB::Execute); 630 } else { 631 _status = IcacheWaitResponse; 632 completeIfetch(NULL); 633 634 updateCycleCounts(); 635 updateCycleCounters(BaseCPU::CPU_STATE_ON); 636 } 637} 638 639 640void 641TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, 642 ThreadContext *tc) 643{ 644 if (fault == NoFault) { 645 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 646 req->getVaddr(), req->getPaddr()); 647 ifetch_pkt = new Packet(req, MemCmd::ReadReq); 648 ifetch_pkt->dataStatic(&inst); 649 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 650 651 if (!icachePort.sendTimingReq(ifetch_pkt)) { 652 // Need to wait for retry 653 _status = IcacheRetry; 654 } else { 655 // Need to wait for cache to respond 656 _status = IcacheWaitResponse; 657 // ownership of packet transferred to memory system 658 ifetch_pkt = NULL; 659 } 660 } else { 661 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 662 delete req; 663 // fetch fault: advance directly to next instruction (fault handler) 664 _status = BaseSimpleCPU::Running; 665 advanceInst(fault); 666 } 667 668 updateCycleCounts(); 669 updateCycleCounters(BaseCPU::CPU_STATE_ON); 670} 671 672 673void 674TimingSimpleCPU::advanceInst(const Fault &fault) 675{ 676 SimpleExecContext &t_info = *threadInfo[curThread]; 677 678 if (_status == Faulting) 679 return; 680 681 if (fault != NoFault) { 682 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 683 684 advancePC(fault); 685 686 Tick stall = dynamic_pointer_cast<SyscallRetryFault>(fault) ? 687 clockEdge(syscallRetryLatency) : clockEdge(); 688 689 reschedule(fetchEvent, stall, true); 690 691 _status = Faulting; 692 return; 693 } 694 695 696 if (!t_info.stayAtPC) 697 advancePC(fault); 698 699 if (tryCompleteDrain()) 700 return; 701 702 if (_status == BaseSimpleCPU::Running) { 703 // kick off fetch of next instruction... callback from icache 704 // response will cause that instruction to be executed, 705 // keeping the CPU running. 706 fetch(); 707 } 708} 709 710 711void 712TimingSimpleCPU::completeIfetch(PacketPtr pkt) 713{ 714 SimpleExecContext& t_info = *threadInfo[curThread]; 715 716 DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 717 pkt->getAddr() : 0); 718 719 // received a response from the icache: execute the received 720 // instruction 721 assert(!pkt || !pkt->isError()); 722 assert(_status == IcacheWaitResponse); 723 724 _status = BaseSimpleCPU::Running; 725 726 updateCycleCounts(); 727 updateCycleCounters(BaseCPU::CPU_STATE_ON); 728 729 if (pkt) 730 pkt->req->setAccessLatency(); 731 732 733 preExecute(); 734 if (curStaticInst && curStaticInst->isMemRef()) { 735 // load or store: just send to dcache 736 Fault fault = curStaticInst->initiateAcc(&t_info, traceData); 737 738 // If we're not running now the instruction will complete in a dcache 739 // response callback or the instruction faulted and has started an 740 // ifetch 741 if (_status == BaseSimpleCPU::Running) { 742 if (fault != NoFault && traceData) { 743 // If there was a fault, we shouldn't trace this instruction. 744 delete traceData; 745 traceData = NULL; 746 } 747 748 postExecute(); 749 // @todo remove me after debugging with legion done 750 if (curStaticInst && (!curStaticInst->isMicroop() || 751 curStaticInst->isFirstMicroop())) 752 instCnt++; 753 advanceInst(fault); 754 } 755 } else if (curStaticInst) { 756 // non-memory instruction: execute completely now 757 Fault fault = curStaticInst->execute(&t_info, traceData); 758 759 // keep an instruction count 760 if (fault == NoFault) 761 countInst(); 762 else if (traceData && !DTRACE(ExecFaulting)) { 763 delete traceData; 764 traceData = NULL; 765 } 766 767 postExecute(); 768 // @todo remove me after debugging with legion done 769 if (curStaticInst && (!curStaticInst->isMicroop() || 770 curStaticInst->isFirstMicroop())) 771 instCnt++; 772 advanceInst(fault); 773 } else { 774 advanceInst(NoFault); 775 } 776 777 if (pkt) { 778 delete pkt->req; 779 delete pkt; 780 } 781} 782 783void 784TimingSimpleCPU::IcachePort::ITickEvent::process() 785{ 786 cpu->completeIfetch(pkt); 787} 788 789bool 790TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 791{ 792 DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr()); 793 // we should only ever see one response per cycle since we only 794 // issue a new request once this response is sunk 795 assert(!tickEvent.scheduled()); 796 // delay processing of returned data until next CPU clock edge 797 tickEvent.schedule(pkt, cpu->clockEdge()); 798 799 return true; 800} 801 802void 803TimingSimpleCPU::IcachePort::recvReqRetry() 804{ 805 // we shouldn't get a retry unless we have a packet that we're 806 // waiting to transmit 807 assert(cpu->ifetch_pkt != NULL); 808 assert(cpu->_status == IcacheRetry); 809 PacketPtr tmp = cpu->ifetch_pkt; 810 if (sendTimingReq(tmp)) { 811 cpu->_status = IcacheWaitResponse; 812 cpu->ifetch_pkt = NULL; 813 } 814} 815 816void 817TimingSimpleCPU::completeDataAccess(PacketPtr pkt) 818{ 819 // received a response from the dcache: complete the load or store 820 // instruction 821 assert(!pkt->isError()); 822 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 823 pkt->req->getFlags().isSet(Request::NO_ACCESS)); 824 825 pkt->req->setAccessLatency(); 826 827 updateCycleCounts(); 828 updateCycleCounters(BaseCPU::CPU_STATE_ON); 829 830 if (pkt->senderState) { 831 SplitFragmentSenderState * send_state = 832 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 833 assert(send_state); 834 delete pkt->req; 835 delete pkt; 836 PacketPtr big_pkt = send_state->bigPkt; 837 delete send_state; 838 839 SplitMainSenderState * main_send_state = 840 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 841 assert(main_send_state); 842 // Record the fact that this packet is no longer outstanding. 843 assert(main_send_state->outstanding != 0); 844 main_send_state->outstanding--; 845 846 if (main_send_state->outstanding) { 847 return; 848 } else { 849 delete main_send_state; 850 big_pkt->senderState = NULL; 851 pkt = big_pkt; 852 } 853 } 854 855 _status = BaseSimpleCPU::Running; 856 857 Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread], 858 traceData); 859 860 // keep an instruction count 861 if (fault == NoFault) 862 countInst(); 863 else if (traceData) { 864 // If there was a fault, we shouldn't trace this instruction. 865 delete traceData; 866 traceData = NULL; 867 } 868 869 delete pkt->req; 870 delete pkt; 871 872 postExecute(); 873 874 advanceInst(fault); 875} 876 877void 878TimingSimpleCPU::updateCycleCounts() 879{ 880 const Cycles delta(curCycle() - previousCycle); 881 882 numCycles += delta; 883 884 previousCycle = curCycle(); 885} 886 887void 888TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 889{ 890 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 891 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 892 cpu->wakeup(tid); 893 } 894 } 895 896 // Making it uniform across all CPUs: 897 // The CPUs need to be woken up only on an invalidation packet (when using caches) 898 // or on an incoming write packet (when not using caches) 899 // It is not necessary to wake up the processor on all incoming packets 900 if (pkt->isInvalidate() || pkt->isWrite()) { 901 for (auto &t_info : cpu->threadInfo) { 902 TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 903 } 904 } 905} 906 907void 908TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) 909{ 910 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 911 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 912 cpu->wakeup(tid); 913 } 914 } 915} 916 917bool 918TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 919{ 920 DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr()); 921 922 // The timing CPU is not really ticked, instead it relies on the 923 // memory system (fetch and load/store) to set the pace. 924 if (!tickEvent.scheduled()) { 925 // Delay processing of returned data until next CPU clock edge 926 tickEvent.schedule(pkt, cpu->clockEdge()); 927 return true; 928 } else { 929 // In the case of a split transaction and a cache that is 930 // faster than a CPU we could get two responses in the 931 // same tick, delay the second one 932 if (!retryRespEvent.scheduled()) 933 cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1))); 934 return false; 935 } 936} 937 938void 939TimingSimpleCPU::DcachePort::DTickEvent::process() 940{ 941 cpu->completeDataAccess(pkt); 942} 943 944void 945TimingSimpleCPU::DcachePort::recvReqRetry() 946{ 947 // we shouldn't get a retry unless we have a packet that we're 948 // waiting to transmit 949 assert(cpu->dcache_pkt != NULL); 950 assert(cpu->_status == DcacheRetry); 951 PacketPtr tmp = cpu->dcache_pkt; 952 if (tmp->senderState) { 953 // This is a packet from a split access. 954 SplitFragmentSenderState * send_state = 955 dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 956 assert(send_state); 957 PacketPtr big_pkt = send_state->bigPkt; 958 959 SplitMainSenderState * main_send_state = 960 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 961 assert(main_send_state); 962 963 if (sendTimingReq(tmp)) { 964 // If we were able to send without retrying, record that fact 965 // and try sending the other fragment. 966 send_state->clearFromParent(); 967 int other_index = main_send_state->getPendingFragment(); 968 if (other_index > 0) { 969 tmp = main_send_state->fragments[other_index]; 970 cpu->dcache_pkt = tmp; 971 if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 972 (big_pkt->isWrite() && cpu->handleWritePacket())) { 973 main_send_state->fragments[other_index] = NULL; 974 } 975 } else { 976 cpu->_status = DcacheWaitResponse; 977 // memory system takes ownership of packet 978 cpu->dcache_pkt = NULL; 979 } 980 } 981 } else if (sendTimingReq(tmp)) { 982 cpu->_status = DcacheWaitResponse; 983 // memory system takes ownership of packet 984 cpu->dcache_pkt = NULL; 985 } 986} 987 988TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 989 Tick t) 990 : pkt(_pkt), cpu(_cpu) 991{ 992 cpu->schedule(this, t); 993} 994 995void 996TimingSimpleCPU::IprEvent::process() 997{ 998 cpu->completeDataAccess(pkt); 999} 1000 1001const char * 1002TimingSimpleCPU::IprEvent::description() const 1003{ 1004 return "Timing Simple CPU Delay IPR event"; 1005} 1006 1007 1008void 1009TimingSimpleCPU::printAddr(Addr a) 1010{ 1011 dcachePort.printAddr(a); 1012} 1013 1014 1015//////////////////////////////////////////////////////////////////////// 1016// 1017// TimingSimpleCPU Simulation Object 1018// 1019TimingSimpleCPU * 1020TimingSimpleCPUParams::create() 1021{ 1022 return new TimingSimpleCPU(this); 1023} 1024