timing.cc revision 11303:f694764d656d
1/*
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2010-2013,2015 ARM Limited
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 */
43
44#include "arch/locked_mem.hh"
45#include "arch/mmapped_ipr.hh"
46#include "arch/utility.hh"
47#include "base/bigint.hh"
48#include "config/the_isa.hh"
49#include "cpu/simple/timing.hh"
50#include "cpu/exetrace.hh"
51#include "debug/Config.hh"
52#include "debug/Drain.hh"
53#include "debug/ExecFaulting.hh"
54#include "debug/SimpleCPU.hh"
55#include "mem/packet.hh"
56#include "mem/packet_access.hh"
57#include "params/TimingSimpleCPU.hh"
58#include "sim/faults.hh"
59#include "sim/full_system.hh"
60#include "sim/system.hh"
61
62#include "debug/Mwait.hh"
63
64using namespace std;
65using namespace TheISA;
66
67void
68TimingSimpleCPU::init()
69{
70    BaseSimpleCPU::init();
71}
72
73void
74TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
75{
76    pkt = _pkt;
77    cpu->schedule(this, t);
78}
79
80TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
81    : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this),
82      dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0),
83      fetchEvent(this)
84{
85    _status = Idle;
86}
87
88
89
90TimingSimpleCPU::~TimingSimpleCPU()
91{
92}
93
94DrainState
95TimingSimpleCPU::drain()
96{
97    if (switchedOut())
98        return DrainState::Drained;
99
100    if (_status == Idle ||
101        (_status == BaseSimpleCPU::Running && isDrained())) {
102        DPRINTF(Drain, "No need to drain.\n");
103        activeThreads.clear();
104        return DrainState::Drained;
105    } else {
106        DPRINTF(Drain, "Requesting drain.\n");
107
108        // The fetch event can become descheduled if a drain didn't
109        // succeed on the first attempt. We need to reschedule it if
110        // the CPU is waiting for a microcode routine to complete.
111        if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled())
112            schedule(fetchEvent, clockEdge());
113
114        return DrainState::Draining;
115    }
116}
117
118void
119TimingSimpleCPU::drainResume()
120{
121    assert(!fetchEvent.scheduled());
122    if (switchedOut())
123        return;
124
125    DPRINTF(SimpleCPU, "Resume\n");
126    verifyMemoryMode();
127
128    assert(!threadContexts.empty());
129
130    _status = BaseSimpleCPU::Idle;
131
132    for (ThreadID tid = 0; tid < numThreads; tid++) {
133        if (threadInfo[tid]->thread->status() == ThreadContext::Active) {
134            threadInfo[tid]->notIdleFraction = 1;
135
136            activeThreads.push_back(tid);
137
138            _status = BaseSimpleCPU::Running;
139
140            // Fetch if any threads active
141            if (!fetchEvent.scheduled()) {
142                schedule(fetchEvent, nextCycle());
143            }
144        } else {
145            threadInfo[tid]->notIdleFraction = 0;
146        }
147    }
148
149    system->totalNumInsts = 0;
150}
151
152bool
153TimingSimpleCPU::tryCompleteDrain()
154{
155    if (drainState() != DrainState::Draining)
156        return false;
157
158    DPRINTF(Drain, "tryCompleteDrain.\n");
159    if (!isDrained())
160        return false;
161
162    DPRINTF(Drain, "CPU done draining, processing drain event\n");
163    signalDrainDone();
164
165    return true;
166}
167
168void
169TimingSimpleCPU::switchOut()
170{
171    SimpleExecContext& t_info = *threadInfo[curThread];
172    M5_VAR_USED SimpleThread* thread = t_info.thread;
173
174    BaseSimpleCPU::switchOut();
175
176    assert(!fetchEvent.scheduled());
177    assert(_status == BaseSimpleCPU::Running || _status == Idle);
178    assert(!t_info.stayAtPC);
179    assert(thread->microPC() == 0);
180
181    updateCycleCounts();
182}
183
184
185void
186TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
187{
188    BaseSimpleCPU::takeOverFrom(oldCPU);
189
190    previousCycle = curCycle();
191}
192
193void
194TimingSimpleCPU::verifyMemoryMode() const
195{
196    if (!system->isTimingMode()) {
197        fatal("The timing CPU requires the memory system to be in "
198              "'timing' mode.\n");
199    }
200}
201
202void
203TimingSimpleCPU::activateContext(ThreadID thread_num)
204{
205    DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num);
206
207    assert(thread_num < numThreads);
208
209    threadInfo[thread_num]->notIdleFraction = 1;
210    if (_status == BaseSimpleCPU::Idle)
211        _status = BaseSimpleCPU::Running;
212
213    // kick things off by initiating the fetch of the next instruction
214    if (!fetchEvent.scheduled())
215        schedule(fetchEvent, clockEdge(Cycles(0)));
216
217    if (std::find(activeThreads.begin(), activeThreads.end(), thread_num)
218         == activeThreads.end()) {
219        activeThreads.push_back(thread_num);
220    }
221}
222
223
224void
225TimingSimpleCPU::suspendContext(ThreadID thread_num)
226{
227    DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
228
229    assert(thread_num < numThreads);
230    activeThreads.remove(thread_num);
231
232    if (_status == Idle)
233        return;
234
235    assert(_status == BaseSimpleCPU::Running);
236
237    threadInfo[thread_num]->notIdleFraction = 0;
238
239    if (activeThreads.empty()) {
240        _status = Idle;
241
242        if (fetchEvent.scheduled()) {
243            deschedule(fetchEvent);
244        }
245    }
246}
247
248bool
249TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
250{
251    SimpleExecContext &t_info = *threadInfo[curThread];
252    SimpleThread* thread = t_info.thread;
253
254    RequestPtr req = pkt->req;
255
256    // We're about the issues a locked load, so tell the monitor
257    // to start caring about this address
258    if (pkt->isRead() && pkt->req->isLLSC()) {
259        TheISA::handleLockedRead(thread, pkt->req);
260    }
261    if (req->isMmappedIpr()) {
262        Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt);
263        new IprEvent(pkt, this, clockEdge(delay));
264        _status = DcacheWaitResponse;
265        dcache_pkt = NULL;
266    } else if (!dcachePort.sendTimingReq(pkt)) {
267        _status = DcacheRetry;
268        dcache_pkt = pkt;
269    } else {
270        _status = DcacheWaitResponse;
271        // memory system takes ownership of packet
272        dcache_pkt = NULL;
273    }
274    return dcache_pkt == NULL;
275}
276
277void
278TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res,
279                          bool read)
280{
281    SimpleExecContext &t_info = *threadInfo[curThread];
282    SimpleThread* thread = t_info.thread;
283
284    PacketPtr pkt = buildPacket(req, read);
285    pkt->dataDynamic<uint8_t>(data);
286    if (req->getFlags().isSet(Request::NO_ACCESS)) {
287        assert(!dcache_pkt);
288        pkt->makeResponse();
289        completeDataAccess(pkt);
290    } else if (read) {
291        handleReadPacket(pkt);
292    } else {
293        bool do_access = true;  // flag to suppress cache access
294
295        if (req->isLLSC()) {
296            do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
297        } else if (req->isCondSwap()) {
298            assert(res);
299            req->setExtraData(*res);
300        }
301
302        if (do_access) {
303            dcache_pkt = pkt;
304            handleWritePacket();
305            threadSnoop(pkt, curThread);
306        } else {
307            _status = DcacheWaitResponse;
308            completeDataAccess(pkt);
309        }
310    }
311}
312
313void
314TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2,
315                               RequestPtr req, uint8_t *data, bool read)
316{
317    PacketPtr pkt1, pkt2;
318    buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read);
319    if (req->getFlags().isSet(Request::NO_ACCESS)) {
320        assert(!dcache_pkt);
321        pkt1->makeResponse();
322        completeDataAccess(pkt1);
323    } else if (read) {
324        SplitFragmentSenderState * send_state =
325            dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
326        if (handleReadPacket(pkt1)) {
327            send_state->clearFromParent();
328            send_state = dynamic_cast<SplitFragmentSenderState *>(
329                    pkt2->senderState);
330            if (handleReadPacket(pkt2)) {
331                send_state->clearFromParent();
332            }
333        }
334    } else {
335        dcache_pkt = pkt1;
336        SplitFragmentSenderState * send_state =
337            dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
338        if (handleWritePacket()) {
339            send_state->clearFromParent();
340            dcache_pkt = pkt2;
341            send_state = dynamic_cast<SplitFragmentSenderState *>(
342                    pkt2->senderState);
343            if (handleWritePacket()) {
344                send_state->clearFromParent();
345            }
346        }
347    }
348}
349
350void
351TimingSimpleCPU::translationFault(const Fault &fault)
352{
353    // fault may be NoFault in cases where a fault is suppressed,
354    // for instance prefetches.
355    updateCycleCounts();
356
357    if (traceData) {
358        // Since there was a fault, we shouldn't trace this instruction.
359        delete traceData;
360        traceData = NULL;
361    }
362
363    postExecute();
364
365    advanceInst(fault);
366}
367
368PacketPtr
369TimingSimpleCPU::buildPacket(RequestPtr req, bool read)
370{
371    return read ? Packet::createRead(req) : Packet::createWrite(req);
372}
373
374void
375TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
376        RequestPtr req1, RequestPtr req2, RequestPtr req,
377        uint8_t *data, bool read)
378{
379    pkt1 = pkt2 = NULL;
380
381    assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
382
383    if (req->getFlags().isSet(Request::NO_ACCESS)) {
384        pkt1 = buildPacket(req, read);
385        return;
386    }
387
388    pkt1 = buildPacket(req1, read);
389    pkt2 = buildPacket(req2, read);
390
391    PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand());
392
393    pkt->dataDynamic<uint8_t>(data);
394    pkt1->dataStatic<uint8_t>(data);
395    pkt2->dataStatic<uint8_t>(data + req1->getSize());
396
397    SplitMainSenderState * main_send_state = new SplitMainSenderState;
398    pkt->senderState = main_send_state;
399    main_send_state->fragments[0] = pkt1;
400    main_send_state->fragments[1] = pkt2;
401    main_send_state->outstanding = 2;
402    pkt1->senderState = new SplitFragmentSenderState(pkt, 0);
403    pkt2->senderState = new SplitFragmentSenderState(pkt, 1);
404}
405
406Fault
407TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
408                         unsigned size, unsigned flags)
409{
410    panic("readMem() is for atomic accesses, and should "
411          "never be called on TimingSimpleCPU.\n");
412}
413
414Fault
415TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags)
416{
417    SimpleExecContext &t_info = *threadInfo[curThread];
418    SimpleThread* thread = t_info.thread;
419
420    Fault fault;
421    const int asid = 0;
422    const ThreadID tid = curThread;
423    const Addr pc = thread->instAddr();
424    unsigned block_size = cacheLineSize();
425    BaseTLB::Mode mode = BaseTLB::Read;
426
427    if (traceData)
428        traceData->setMem(addr, size, flags);
429
430    RequestPtr req  = new Request(asid, addr, size,
431                                  flags, dataMasterId(), pc,
432                                  thread->contextId(), tid);
433
434    req->taskId(taskId());
435
436    Addr split_addr = roundDown(addr + size - 1, block_size);
437    assert(split_addr <= addr || split_addr - addr < block_size);
438
439    _status = DTBWaitResponse;
440    if (split_addr > addr) {
441        RequestPtr req1, req2;
442        assert(!req->isLLSC() && !req->isSwap());
443        req->splitOnVaddr(split_addr, req1, req2);
444
445        WholeTranslationState *state =
446            new WholeTranslationState(req, req1, req2, new uint8_t[size],
447                                      NULL, mode);
448        DataTranslation<TimingSimpleCPU *> *trans1 =
449            new DataTranslation<TimingSimpleCPU *>(this, state, 0);
450        DataTranslation<TimingSimpleCPU *> *trans2 =
451            new DataTranslation<TimingSimpleCPU *>(this, state, 1);
452
453        thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode);
454        thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode);
455    } else {
456        WholeTranslationState *state =
457            new WholeTranslationState(req, new uint8_t[size], NULL, mode);
458        DataTranslation<TimingSimpleCPU *> *translation
459            = new DataTranslation<TimingSimpleCPU *>(this, state);
460        thread->dtb->translateTiming(req, thread->getTC(), translation, mode);
461    }
462
463    return NoFault;
464}
465
466bool
467TimingSimpleCPU::handleWritePacket()
468{
469    SimpleExecContext &t_info = *threadInfo[curThread];
470    SimpleThread* thread = t_info.thread;
471
472    RequestPtr req = dcache_pkt->req;
473    if (req->isMmappedIpr()) {
474        Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
475        new IprEvent(dcache_pkt, this, clockEdge(delay));
476        _status = DcacheWaitResponse;
477        dcache_pkt = NULL;
478    } else if (!dcachePort.sendTimingReq(dcache_pkt)) {
479        _status = DcacheRetry;
480    } else {
481        _status = DcacheWaitResponse;
482        // memory system takes ownership of packet
483        dcache_pkt = NULL;
484    }
485    return dcache_pkt == NULL;
486}
487
488Fault
489TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
490                          Addr addr, unsigned flags, uint64_t *res)
491{
492    SimpleExecContext &t_info = *threadInfo[curThread];
493    SimpleThread* thread = t_info.thread;
494
495    uint8_t *newData = new uint8_t[size];
496    const int asid = 0;
497    const ThreadID tid = curThread;
498    const Addr pc = thread->instAddr();
499    unsigned block_size = cacheLineSize();
500    BaseTLB::Mode mode = BaseTLB::Write;
501
502    if (data == NULL) {
503        assert(flags & Request::CACHE_BLOCK_ZERO);
504        // This must be a cache block cleaning request
505        memset(newData, 0, size);
506    } else {
507        memcpy(newData, data, size);
508    }
509
510    if (traceData)
511        traceData->setMem(addr, size, flags);
512
513    RequestPtr req = new Request(asid, addr, size,
514                                 flags, dataMasterId(), pc,
515                                 thread->contextId(), tid);
516
517    req->taskId(taskId());
518
519    Addr split_addr = roundDown(addr + size - 1, block_size);
520    assert(split_addr <= addr || split_addr - addr < block_size);
521
522    _status = DTBWaitResponse;
523    if (split_addr > addr) {
524        RequestPtr req1, req2;
525        assert(!req->isLLSC() && !req->isSwap());
526        req->splitOnVaddr(split_addr, req1, req2);
527
528        WholeTranslationState *state =
529            new WholeTranslationState(req, req1, req2, newData, res, mode);
530        DataTranslation<TimingSimpleCPU *> *trans1 =
531            new DataTranslation<TimingSimpleCPU *>(this, state, 0);
532        DataTranslation<TimingSimpleCPU *> *trans2 =
533            new DataTranslation<TimingSimpleCPU *>(this, state, 1);
534
535        thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode);
536        thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode);
537    } else {
538        WholeTranslationState *state =
539            new WholeTranslationState(req, newData, res, mode);
540        DataTranslation<TimingSimpleCPU *> *translation =
541            new DataTranslation<TimingSimpleCPU *>(this, state);
542        thread->dtb->translateTiming(req, thread->getTC(), translation, mode);
543    }
544
545    // Translation faults will be returned via finishTranslation()
546    return NoFault;
547}
548
549void
550TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
551{
552    for (ThreadID tid = 0; tid < numThreads; tid++) {
553        if (tid != sender) {
554            if(getCpuAddrMonitor(tid)->doMonitor(pkt)) {
555                wakeup(tid);
556            }
557            TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt,
558                    dcachePort.cacheBlockMask);
559        }
560    }
561}
562
563void
564TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
565{
566    _status = BaseSimpleCPU::Running;
567
568    if (state->getFault() != NoFault) {
569        if (state->isPrefetch()) {
570            state->setNoFault();
571        }
572        delete [] state->data;
573        state->deleteReqs();
574        translationFault(state->getFault());
575    } else {
576        if (!state->isSplit) {
577            sendData(state->mainReq, state->data, state->res,
578                     state->mode == BaseTLB::Read);
579        } else {
580            sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq,
581                          state->data, state->mode == BaseTLB::Read);
582        }
583    }
584
585    delete state;
586}
587
588
589void
590TimingSimpleCPU::fetch()
591{
592    // Change thread if multi-threaded
593    swapActiveThread();
594
595    SimpleExecContext &t_info = *threadInfo[curThread];
596    SimpleThread* thread = t_info.thread;
597
598    DPRINTF(SimpleCPU, "Fetch\n");
599
600    if (!curStaticInst || !curStaticInst->isDelayedCommit()) {
601        checkForInterrupts();
602        checkPcEventQueue();
603    }
604
605    // We must have just got suspended by a PC event
606    if (_status == Idle)
607        return;
608
609    TheISA::PCState pcState = thread->pcState();
610    bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
611                       !curMacroStaticInst;
612
613    if (needToFetch) {
614        _status = BaseSimpleCPU::Running;
615        Request *ifetch_req = new Request();
616        ifetch_req->taskId(taskId());
617        ifetch_req->setThreadContext(thread->contextId(), curThread);
618        setupFetchRequest(ifetch_req);
619        DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
620        thread->itb->translateTiming(ifetch_req, thread->getTC(),
621                &fetchTranslation, BaseTLB::Execute);
622    } else {
623        _status = IcacheWaitResponse;
624        completeIfetch(NULL);
625
626        updateCycleCounts();
627    }
628}
629
630
631void
632TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req,
633                           ThreadContext *tc)
634{
635    if (fault == NoFault) {
636        DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
637                req->getVaddr(), req->getPaddr());
638        ifetch_pkt = new Packet(req, MemCmd::ReadReq);
639        ifetch_pkt->dataStatic(&inst);
640        DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
641
642        if (!icachePort.sendTimingReq(ifetch_pkt)) {
643            // Need to wait for retry
644            _status = IcacheRetry;
645        } else {
646            // Need to wait for cache to respond
647            _status = IcacheWaitResponse;
648            // ownership of packet transferred to memory system
649            ifetch_pkt = NULL;
650        }
651    } else {
652        DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr());
653        delete req;
654        // fetch fault: advance directly to next instruction (fault handler)
655        _status = BaseSimpleCPU::Running;
656        advanceInst(fault);
657    }
658
659    updateCycleCounts();
660}
661
662
663void
664TimingSimpleCPU::advanceInst(const Fault &fault)
665{
666    SimpleExecContext &t_info = *threadInfo[curThread];
667
668    if (_status == Faulting)
669        return;
670
671    if (fault != NoFault) {
672        advancePC(fault);
673        DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
674        reschedule(fetchEvent, clockEdge(), true);
675        _status = Faulting;
676        return;
677    }
678
679
680    if (!t_info.stayAtPC)
681        advancePC(fault);
682
683    if (tryCompleteDrain())
684            return;
685
686    if (_status == BaseSimpleCPU::Running) {
687        // kick off fetch of next instruction... callback from icache
688        // response will cause that instruction to be executed,
689        // keeping the CPU running.
690        fetch();
691    }
692}
693
694
695void
696TimingSimpleCPU::completeIfetch(PacketPtr pkt)
697{
698    SimpleExecContext& t_info = *threadInfo[curThread];
699
700    DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ?
701            pkt->getAddr() : 0);
702
703    // received a response from the icache: execute the received
704    // instruction
705    assert(!pkt || !pkt->isError());
706    assert(_status == IcacheWaitResponse);
707
708    _status = BaseSimpleCPU::Running;
709
710    updateCycleCounts();
711
712    if (pkt)
713        pkt->req->setAccessLatency();
714
715
716    preExecute();
717    if (curStaticInst && curStaticInst->isMemRef()) {
718        // load or store: just send to dcache
719        Fault fault = curStaticInst->initiateAcc(&t_info, traceData);
720
721        // If we're not running now the instruction will complete in a dcache
722        // response callback or the instruction faulted and has started an
723        // ifetch
724        if (_status == BaseSimpleCPU::Running) {
725            if (fault != NoFault && traceData) {
726                // If there was a fault, we shouldn't trace this instruction.
727                delete traceData;
728                traceData = NULL;
729            }
730
731            postExecute();
732            // @todo remove me after debugging with legion done
733            if (curStaticInst && (!curStaticInst->isMicroop() ||
734                        curStaticInst->isFirstMicroop()))
735                instCnt++;
736            advanceInst(fault);
737        }
738    } else if (curStaticInst) {
739        // non-memory instruction: execute completely now
740        Fault fault = curStaticInst->execute(&t_info, traceData);
741
742        // keep an instruction count
743        if (fault == NoFault)
744            countInst();
745        else if (traceData && !DTRACE(ExecFaulting)) {
746            delete traceData;
747            traceData = NULL;
748        }
749
750        postExecute();
751        // @todo remove me after debugging with legion done
752        if (curStaticInst && (!curStaticInst->isMicroop() ||
753                curStaticInst->isFirstMicroop()))
754            instCnt++;
755        advanceInst(fault);
756    } else {
757        advanceInst(NoFault);
758    }
759
760    if (pkt) {
761        delete pkt->req;
762        delete pkt;
763    }
764}
765
766void
767TimingSimpleCPU::IcachePort::ITickEvent::process()
768{
769    cpu->completeIfetch(pkt);
770}
771
772bool
773TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt)
774{
775    DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr());
776    // we should only ever see one response per cycle since we only
777    // issue a new request once this response is sunk
778    assert(!tickEvent.scheduled());
779    // delay processing of returned data until next CPU clock edge
780    tickEvent.schedule(pkt, cpu->clockEdge());
781
782    return true;
783}
784
785void
786TimingSimpleCPU::IcachePort::recvReqRetry()
787{
788    // we shouldn't get a retry unless we have a packet that we're
789    // waiting to transmit
790    assert(cpu->ifetch_pkt != NULL);
791    assert(cpu->_status == IcacheRetry);
792    PacketPtr tmp = cpu->ifetch_pkt;
793    if (sendTimingReq(tmp)) {
794        cpu->_status = IcacheWaitResponse;
795        cpu->ifetch_pkt = NULL;
796    }
797}
798
799void
800TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
801{
802    // received a response from the dcache: complete the load or store
803    // instruction
804    assert(!pkt->isError());
805    assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
806           pkt->req->getFlags().isSet(Request::NO_ACCESS));
807
808    pkt->req->setAccessLatency();
809
810    updateCycleCounts();
811
812    if (pkt->senderState) {
813        SplitFragmentSenderState * send_state =
814            dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
815        assert(send_state);
816        delete pkt->req;
817        delete pkt;
818        PacketPtr big_pkt = send_state->bigPkt;
819        delete send_state;
820
821        SplitMainSenderState * main_send_state =
822            dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
823        assert(main_send_state);
824        // Record the fact that this packet is no longer outstanding.
825        assert(main_send_state->outstanding != 0);
826        main_send_state->outstanding--;
827
828        if (main_send_state->outstanding) {
829            return;
830        } else {
831            delete main_send_state;
832            big_pkt->senderState = NULL;
833            pkt = big_pkt;
834        }
835    }
836
837    _status = BaseSimpleCPU::Running;
838
839    Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread],
840                                             traceData);
841
842    // keep an instruction count
843    if (fault == NoFault)
844        countInst();
845    else if (traceData) {
846        // If there was a fault, we shouldn't trace this instruction.
847        delete traceData;
848        traceData = NULL;
849    }
850
851    delete pkt->req;
852    delete pkt;
853
854    postExecute();
855
856    advanceInst(fault);
857}
858
859void
860TimingSimpleCPU::updateCycleCounts()
861{
862    const Cycles delta(curCycle() - previousCycle);
863
864    numCycles += delta;
865    ppCycles->notify(delta);
866
867    previousCycle = curCycle();
868}
869
870void
871TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
872{
873    for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
874        if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
875            cpu->wakeup(tid);
876        }
877    }
878
879    for (auto &t_info : cpu->threadInfo) {
880        TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
881    }
882}
883
884void
885TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt)
886{
887    for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
888        if(cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
889            cpu->wakeup(tid);
890        }
891    }
892}
893
894bool
895TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
896{
897    DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr());
898
899    // The timing CPU is not really ticked, instead it relies on the
900    // memory system (fetch and load/store) to set the pace.
901    if (!tickEvent.scheduled()) {
902        // Delay processing of returned data until next CPU clock edge
903        tickEvent.schedule(pkt, cpu->clockEdge());
904        return true;
905    } else {
906        // In the case of a split transaction and a cache that is
907        // faster than a CPU we could get two responses in the
908        // same tick, delay the second one
909        if (!retryRespEvent.scheduled())
910            cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1)));
911        return false;
912    }
913}
914
915void
916TimingSimpleCPU::DcachePort::DTickEvent::process()
917{
918    cpu->completeDataAccess(pkt);
919}
920
921void
922TimingSimpleCPU::DcachePort::recvReqRetry()
923{
924    // we shouldn't get a retry unless we have a packet that we're
925    // waiting to transmit
926    assert(cpu->dcache_pkt != NULL);
927    assert(cpu->_status == DcacheRetry);
928    PacketPtr tmp = cpu->dcache_pkt;
929    if (tmp->senderState) {
930        // This is a packet from a split access.
931        SplitFragmentSenderState * send_state =
932            dynamic_cast<SplitFragmentSenderState *>(tmp->senderState);
933        assert(send_state);
934        PacketPtr big_pkt = send_state->bigPkt;
935
936        SplitMainSenderState * main_send_state =
937            dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
938        assert(main_send_state);
939
940        if (sendTimingReq(tmp)) {
941            // If we were able to send without retrying, record that fact
942            // and try sending the other fragment.
943            send_state->clearFromParent();
944            int other_index = main_send_state->getPendingFragment();
945            if (other_index > 0) {
946                tmp = main_send_state->fragments[other_index];
947                cpu->dcache_pkt = tmp;
948                if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) ||
949                        (big_pkt->isWrite() && cpu->handleWritePacket())) {
950                    main_send_state->fragments[other_index] = NULL;
951                }
952            } else {
953                cpu->_status = DcacheWaitResponse;
954                // memory system takes ownership of packet
955                cpu->dcache_pkt = NULL;
956            }
957        }
958    } else if (sendTimingReq(tmp)) {
959        cpu->_status = DcacheWaitResponse;
960        // memory system takes ownership of packet
961        cpu->dcache_pkt = NULL;
962    }
963}
964
965TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu,
966    Tick t)
967    : pkt(_pkt), cpu(_cpu)
968{
969    cpu->schedule(this, t);
970}
971
972void
973TimingSimpleCPU::IprEvent::process()
974{
975    cpu->completeDataAccess(pkt);
976}
977
978const char *
979TimingSimpleCPU::IprEvent::description() const
980{
981    return "Timing Simple CPU Delay IPR event";
982}
983
984
985void
986TimingSimpleCPU::printAddr(Addr a)
987{
988    dcachePort.printAddr(a);
989}
990
991
992////////////////////////////////////////////////////////////////////////
993//
994//  TimingSimpleCPU Simulation Object
995//
996TimingSimpleCPU *
997TimingSimpleCPUParams::create()
998{
999    return new TimingSimpleCPU(this);
1000}
1001