timing.cc revision 11147
113481Sgiacomo.travaglini@arm.com/* 213481Sgiacomo.travaglini@arm.com * Copyright 2014 Google, Inc. 313481Sgiacomo.travaglini@arm.com * Copyright (c) 2010-2013,2015 ARM Limited 413481Sgiacomo.travaglini@arm.com * All rights reserved 513481Sgiacomo.travaglini@arm.com * 613481Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 713481Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 813481Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 913481Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 1013481Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1113481Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1213481Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1313481Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1413481Sgiacomo.travaglini@arm.com * 1513481Sgiacomo.travaglini@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1613481Sgiacomo.travaglini@arm.com * All rights reserved. 1713481Sgiacomo.travaglini@arm.com * 1813481Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 1913481Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 2013481Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 2113481Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 2213481Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 2313481Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 2413481Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 2513481Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 2613481Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 2713481Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 2813481Sgiacomo.travaglini@arm.com * 2913481Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3013481Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3113481Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3213481Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3313481Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3413481Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3513481Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3613481Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3713481Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3813481Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3913481Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4013481Sgiacomo.travaglini@arm.com * 4113481Sgiacomo.travaglini@arm.com * Authors: Steve Reinhardt 4213481Sgiacomo.travaglini@arm.com */ 4313481Sgiacomo.travaglini@arm.com 4413481Sgiacomo.travaglini@arm.com#include "arch/locked_mem.hh" 4513481Sgiacomo.travaglini@arm.com#include "arch/mmapped_ipr.hh" 4613481Sgiacomo.travaglini@arm.com#include "arch/utility.hh" 4713481Sgiacomo.travaglini@arm.com#include "base/bigint.hh" 4813481Sgiacomo.travaglini@arm.com#include "config/the_isa.hh" 4913481Sgiacomo.travaglini@arm.com#include "cpu/simple/timing.hh" 5013481Sgiacomo.travaglini@arm.com#include "cpu/exetrace.hh" 5113481Sgiacomo.travaglini@arm.com#include "debug/Config.hh" 5213481Sgiacomo.travaglini@arm.com#include "debug/Drain.hh" 5313481Sgiacomo.travaglini@arm.com#include "debug/ExecFaulting.hh" 5413481Sgiacomo.travaglini@arm.com#include "debug/SimpleCPU.hh" 5513481Sgiacomo.travaglini@arm.com#include "mem/packet.hh" 5613481Sgiacomo.travaglini@arm.com#include "mem/packet_access.hh" 5713481Sgiacomo.travaglini@arm.com#include "params/TimingSimpleCPU.hh" 5813481Sgiacomo.travaglini@arm.com#include "sim/faults.hh" 5913481Sgiacomo.travaglini@arm.com#include "sim/full_system.hh" 6013481Sgiacomo.travaglini@arm.com#include "sim/system.hh" 6113481Sgiacomo.travaglini@arm.com 6213481Sgiacomo.travaglini@arm.com#include "debug/Mwait.hh" 6313481Sgiacomo.travaglini@arm.com 6413481Sgiacomo.travaglini@arm.comusing namespace std; 6513481Sgiacomo.travaglini@arm.comusing namespace TheISA; 6613481Sgiacomo.travaglini@arm.com 6713481Sgiacomo.travaglini@arm.comvoid 6813481Sgiacomo.travaglini@arm.comTimingSimpleCPU::init() 6913481Sgiacomo.travaglini@arm.com{ 7013481Sgiacomo.travaglini@arm.com BaseSimpleCPU::init(); 7113481Sgiacomo.travaglini@arm.com} 7213481Sgiacomo.travaglini@arm.com 7313481Sgiacomo.travaglini@arm.comvoid 7413481Sgiacomo.travaglini@arm.comTimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 7513481Sgiacomo.travaglini@arm.com{ 7613481Sgiacomo.travaglini@arm.com pkt = _pkt; 7713481Sgiacomo.travaglini@arm.com cpu->schedule(this, t); 7813481Sgiacomo.travaglini@arm.com} 7913481Sgiacomo.travaglini@arm.com 8013481Sgiacomo.travaglini@arm.comTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 8113481Sgiacomo.travaglini@arm.com : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 8213481Sgiacomo.travaglini@arm.com dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 8313481Sgiacomo.travaglini@arm.com fetchEvent(this) 8413481Sgiacomo.travaglini@arm.com{ 8513481Sgiacomo.travaglini@arm.com _status = Idle; 8613481Sgiacomo.travaglini@arm.com} 8713481Sgiacomo.travaglini@arm.com 8813481Sgiacomo.travaglini@arm.com 8913481Sgiacomo.travaglini@arm.com 9013481Sgiacomo.travaglini@arm.comTimingSimpleCPU::~TimingSimpleCPU() 9113481Sgiacomo.travaglini@arm.com{ 9213481Sgiacomo.travaglini@arm.com} 9313481Sgiacomo.travaglini@arm.com 9413481Sgiacomo.travaglini@arm.comDrainState 9513481Sgiacomo.travaglini@arm.comTimingSimpleCPU::drain() 9613481Sgiacomo.travaglini@arm.com{ 9713481Sgiacomo.travaglini@arm.com if (switchedOut()) 9813481Sgiacomo.travaglini@arm.com return DrainState::Drained; 9913481Sgiacomo.travaglini@arm.com 10013481Sgiacomo.travaglini@arm.com if (_status == Idle || 10113481Sgiacomo.travaglini@arm.com (_status == BaseSimpleCPU::Running && isDrained())) { 10213481Sgiacomo.travaglini@arm.com DPRINTF(Drain, "No need to drain.\n"); 10313481Sgiacomo.travaglini@arm.com activeThreads.clear(); 10413481Sgiacomo.travaglini@arm.com return DrainState::Drained; 10513481Sgiacomo.travaglini@arm.com } else { 10613481Sgiacomo.travaglini@arm.com DPRINTF(Drain, "Requesting drain.\n"); 10713481Sgiacomo.travaglini@arm.com 10813481Sgiacomo.travaglini@arm.com // The fetch event can become descheduled if a drain didn't 10913481Sgiacomo.travaglini@arm.com // succeed on the first attempt. We need to reschedule it if 11013481Sgiacomo.travaglini@arm.com // the CPU is waiting for a microcode routine to complete. 11113481Sgiacomo.travaglini@arm.com if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 11213481Sgiacomo.travaglini@arm.com schedule(fetchEvent, clockEdge()); 11313481Sgiacomo.travaglini@arm.com 11413481Sgiacomo.travaglini@arm.com return DrainState::Draining; 11513481Sgiacomo.travaglini@arm.com } 11613481Sgiacomo.travaglini@arm.com} 11713481Sgiacomo.travaglini@arm.com 11813481Sgiacomo.travaglini@arm.comvoid 11913481Sgiacomo.travaglini@arm.comTimingSimpleCPU::drainResume() 12013481Sgiacomo.travaglini@arm.com{ 12113481Sgiacomo.travaglini@arm.com assert(!fetchEvent.scheduled()); 12213481Sgiacomo.travaglini@arm.com if (switchedOut()) 12313481Sgiacomo.travaglini@arm.com return; 12413481Sgiacomo.travaglini@arm.com 12513481Sgiacomo.travaglini@arm.com DPRINTF(SimpleCPU, "Resume\n"); 12613481Sgiacomo.travaglini@arm.com verifyMemoryMode(); 12713481Sgiacomo.travaglini@arm.com 12813481Sgiacomo.travaglini@arm.com assert(!threadContexts.empty()); 12913481Sgiacomo.travaglini@arm.com 13013481Sgiacomo.travaglini@arm.com _status = BaseSimpleCPU::Idle; 13113481Sgiacomo.travaglini@arm.com 13213481Sgiacomo.travaglini@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 13313481Sgiacomo.travaglini@arm.com if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 13413481Sgiacomo.travaglini@arm.com threadInfo[tid]->notIdleFraction = 1; 13513481Sgiacomo.travaglini@arm.com 13613481Sgiacomo.travaglini@arm.com activeThreads.push_back(tid); 13713481Sgiacomo.travaglini@arm.com 13813481Sgiacomo.travaglini@arm.com _status = BaseSimpleCPU::Running; 13913481Sgiacomo.travaglini@arm.com 14013481Sgiacomo.travaglini@arm.com // Fetch if any threads active 14113481Sgiacomo.travaglini@arm.com if (!fetchEvent.scheduled()) { 14213481Sgiacomo.travaglini@arm.com schedule(fetchEvent, nextCycle()); 14313481Sgiacomo.travaglini@arm.com } 14413481Sgiacomo.travaglini@arm.com } else { 14513481Sgiacomo.travaglini@arm.com threadInfo[tid]->notIdleFraction = 0; 14613481Sgiacomo.travaglini@arm.com } 14713481Sgiacomo.travaglini@arm.com } 14813481Sgiacomo.travaglini@arm.com 14913481Sgiacomo.travaglini@arm.com system->totalNumInsts = 0; 15013481Sgiacomo.travaglini@arm.com} 15113481Sgiacomo.travaglini@arm.com 15213481Sgiacomo.travaglini@arm.combool 15313481Sgiacomo.travaglini@arm.comTimingSimpleCPU::tryCompleteDrain() 15413481Sgiacomo.travaglini@arm.com{ 15513481Sgiacomo.travaglini@arm.com if (drainState() != DrainState::Draining) 15613481Sgiacomo.travaglini@arm.com return false; 15713481Sgiacomo.travaglini@arm.com 15813481Sgiacomo.travaglini@arm.com DPRINTF(Drain, "tryCompleteDrain.\n"); 15913481Sgiacomo.travaglini@arm.com if (!isDrained()) 16013481Sgiacomo.travaglini@arm.com return false; 16113481Sgiacomo.travaglini@arm.com 16213481Sgiacomo.travaglini@arm.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 16313481Sgiacomo.travaglini@arm.com signalDrainDone(); 16413481Sgiacomo.travaglini@arm.com 16513481Sgiacomo.travaglini@arm.com return true; 16613481Sgiacomo.travaglini@arm.com} 16713481Sgiacomo.travaglini@arm.com 16813481Sgiacomo.travaglini@arm.comvoid 16913481Sgiacomo.travaglini@arm.comTimingSimpleCPU::switchOut() 17013481Sgiacomo.travaglini@arm.com{ 17113481Sgiacomo.travaglini@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 17213481Sgiacomo.travaglini@arm.com M5_VAR_USED SimpleThread* thread = t_info.thread; 17313481Sgiacomo.travaglini@arm.com 17413481Sgiacomo.travaglini@arm.com BaseSimpleCPU::switchOut(); 17513481Sgiacomo.travaglini@arm.com 17613481Sgiacomo.travaglini@arm.com assert(!fetchEvent.scheduled()); 17713481Sgiacomo.travaglini@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 17813481Sgiacomo.travaglini@arm.com assert(!t_info.stayAtPC); 17913481Sgiacomo.travaglini@arm.com assert(thread->microPC() == 0); 18013481Sgiacomo.travaglini@arm.com 18113481Sgiacomo.travaglini@arm.com updateCycleCounts(); 18213481Sgiacomo.travaglini@arm.com} 18313481Sgiacomo.travaglini@arm.com 18413481Sgiacomo.travaglini@arm.com 18513481Sgiacomo.travaglini@arm.comvoid 18613481Sgiacomo.travaglini@arm.comTimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 18713481Sgiacomo.travaglini@arm.com{ 18813481Sgiacomo.travaglini@arm.com BaseSimpleCPU::takeOverFrom(oldCPU); 18913481Sgiacomo.travaglini@arm.com 19013481Sgiacomo.travaglini@arm.com previousCycle = curCycle(); 19113481Sgiacomo.travaglini@arm.com} 19213481Sgiacomo.travaglini@arm.com 19313481Sgiacomo.travaglini@arm.comvoid 19413481Sgiacomo.travaglini@arm.comTimingSimpleCPU::verifyMemoryMode() const 19513481Sgiacomo.travaglini@arm.com{ 19613481Sgiacomo.travaglini@arm.com if (!system->isTimingMode()) { 19713481Sgiacomo.travaglini@arm.com fatal("The timing CPU requires the memory system to be in " 19813481Sgiacomo.travaglini@arm.com "'timing' mode.\n"); 19913481Sgiacomo.travaglini@arm.com } 20013481Sgiacomo.travaglini@arm.com} 20113481Sgiacomo.travaglini@arm.com 20213481Sgiacomo.travaglini@arm.comvoid 20313481Sgiacomo.travaglini@arm.comTimingSimpleCPU::activateContext(ThreadID thread_num) 20413481Sgiacomo.travaglini@arm.com{ 20513481Sgiacomo.travaglini@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 20613481Sgiacomo.travaglini@arm.com 20713481Sgiacomo.travaglini@arm.com assert(thread_num < numThreads); 20813481Sgiacomo.travaglini@arm.com 20913481Sgiacomo.travaglini@arm.com threadInfo[thread_num]->notIdleFraction = 1; 21013481Sgiacomo.travaglini@arm.com if (_status == BaseSimpleCPU::Idle) 21113481Sgiacomo.travaglini@arm.com _status = BaseSimpleCPU::Running; 21213481Sgiacomo.travaglini@arm.com 21313481Sgiacomo.travaglini@arm.com // kick things off by initiating the fetch of the next instruction 21413481Sgiacomo.travaglini@arm.com if (!fetchEvent.scheduled()) 21513481Sgiacomo.travaglini@arm.com schedule(fetchEvent, clockEdge(Cycles(0))); 21613481Sgiacomo.travaglini@arm.com 21713481Sgiacomo.travaglini@arm.com if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 21813481Sgiacomo.travaglini@arm.com == activeThreads.end()) { 21913481Sgiacomo.travaglini@arm.com activeThreads.push_back(thread_num); 22013481Sgiacomo.travaglini@arm.com } 22113481Sgiacomo.travaglini@arm.com} 22213481Sgiacomo.travaglini@arm.com 22313481Sgiacomo.travaglini@arm.com 22413481Sgiacomo.travaglini@arm.comvoid 22513481Sgiacomo.travaglini@arm.comTimingSimpleCPU::suspendContext(ThreadID thread_num) 22613481Sgiacomo.travaglini@arm.com{ 22713481Sgiacomo.travaglini@arm.com DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 22813481Sgiacomo.travaglini@arm.com 22913481Sgiacomo.travaglini@arm.com assert(thread_num < numThreads); 23013481Sgiacomo.travaglini@arm.com activeThreads.remove(thread_num); 23113481Sgiacomo.travaglini@arm.com 23213481Sgiacomo.travaglini@arm.com if (_status == Idle) 23313481Sgiacomo.travaglini@arm.com return; 23413481Sgiacomo.travaglini@arm.com 23513481Sgiacomo.travaglini@arm.com assert(_status == BaseSimpleCPU::Running); 23613481Sgiacomo.travaglini@arm.com 23713481Sgiacomo.travaglini@arm.com threadInfo[thread_num]->notIdleFraction = 0; 23813481Sgiacomo.travaglini@arm.com 23913481Sgiacomo.travaglini@arm.com if (activeThreads.empty()) { 24013481Sgiacomo.travaglini@arm.com _status = Idle; 24113481Sgiacomo.travaglini@arm.com 24213481Sgiacomo.travaglini@arm.com if (fetchEvent.scheduled()) { 24313481Sgiacomo.travaglini@arm.com deschedule(fetchEvent); 24413481Sgiacomo.travaglini@arm.com } 24513481Sgiacomo.travaglini@arm.com } 24613481Sgiacomo.travaglini@arm.com} 24713481Sgiacomo.travaglini@arm.com 24813481Sgiacomo.travaglini@arm.combool 24913481Sgiacomo.travaglini@arm.comTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 25013481Sgiacomo.travaglini@arm.com{ 25113481Sgiacomo.travaglini@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 25213481Sgiacomo.travaglini@arm.com SimpleThread* thread = t_info.thread; 25313481Sgiacomo.travaglini@arm.com 25413481Sgiacomo.travaglini@arm.com RequestPtr req = pkt->req; 25513481Sgiacomo.travaglini@arm.com 25613481Sgiacomo.travaglini@arm.com // We're about the issues a locked load, so tell the monitor 25713481Sgiacomo.travaglini@arm.com // to start caring about this address 25813481Sgiacomo.travaglini@arm.com if (pkt->isRead() && pkt->req->isLLSC()) { 25913481Sgiacomo.travaglini@arm.com TheISA::handleLockedRead(thread, pkt->req); 26013481Sgiacomo.travaglini@arm.com } 26113481Sgiacomo.travaglini@arm.com if (req->isMmappedIpr()) { 26213481Sgiacomo.travaglini@arm.com Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 26313481Sgiacomo.travaglini@arm.com new IprEvent(pkt, this, clockEdge(delay)); 26413481Sgiacomo.travaglini@arm.com _status = DcacheWaitResponse; 26513481Sgiacomo.travaglini@arm.com dcache_pkt = NULL; 26613481Sgiacomo.travaglini@arm.com } else if (!dcachePort.sendTimingReq(pkt)) { 26713481Sgiacomo.travaglini@arm.com _status = DcacheRetry; 26813481Sgiacomo.travaglini@arm.com dcache_pkt = pkt; 26913481Sgiacomo.travaglini@arm.com } else { 27013481Sgiacomo.travaglini@arm.com _status = DcacheWaitResponse; 27113481Sgiacomo.travaglini@arm.com // memory system takes ownership of packet 27213481Sgiacomo.travaglini@arm.com dcache_pkt = NULL; 27313481Sgiacomo.travaglini@arm.com } 27413481Sgiacomo.travaglini@arm.com return dcache_pkt == NULL; 27513481Sgiacomo.travaglini@arm.com} 27613481Sgiacomo.travaglini@arm.com 27713481Sgiacomo.travaglini@arm.comvoid 27813481Sgiacomo.travaglini@arm.comTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 27913481Sgiacomo.travaglini@arm.com bool read) 28013481Sgiacomo.travaglini@arm.com{ 28113481Sgiacomo.travaglini@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 28213481Sgiacomo.travaglini@arm.com SimpleThread* thread = t_info.thread; 28313481Sgiacomo.travaglini@arm.com 28413481Sgiacomo.travaglini@arm.com PacketPtr pkt = buildPacket(req, read); 28513481Sgiacomo.travaglini@arm.com pkt->dataDynamic<uint8_t>(data); 28613481Sgiacomo.travaglini@arm.com if (req->getFlags().isSet(Request::NO_ACCESS)) { 28713481Sgiacomo.travaglini@arm.com assert(!dcache_pkt); 28813481Sgiacomo.travaglini@arm.com pkt->makeResponse(); 28913481Sgiacomo.travaglini@arm.com completeDataAccess(pkt); 29013481Sgiacomo.travaglini@arm.com } else if (read) { 29113481Sgiacomo.travaglini@arm.com handleReadPacket(pkt); 29213481Sgiacomo.travaglini@arm.com } else { 29313481Sgiacomo.travaglini@arm.com bool do_access = true; // flag to suppress cache access 29413481Sgiacomo.travaglini@arm.com 29513481Sgiacomo.travaglini@arm.com if (req->isLLSC()) { 29613481Sgiacomo.travaglini@arm.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 29713481Sgiacomo.travaglini@arm.com } else if (req->isCondSwap()) { 29813481Sgiacomo.travaglini@arm.com assert(res); 29913481Sgiacomo.travaglini@arm.com req->setExtraData(*res); 30013481Sgiacomo.travaglini@arm.com } 30113481Sgiacomo.travaglini@arm.com 30213481Sgiacomo.travaglini@arm.com if (do_access) { 30313481Sgiacomo.travaglini@arm.com dcache_pkt = pkt; 30413481Sgiacomo.travaglini@arm.com handleWritePacket(); 30513481Sgiacomo.travaglini@arm.com } else { 30613481Sgiacomo.travaglini@arm.com _status = DcacheWaitResponse; 30713481Sgiacomo.travaglini@arm.com completeDataAccess(pkt); 30813481Sgiacomo.travaglini@arm.com } 30913481Sgiacomo.travaglini@arm.com } 31013481Sgiacomo.travaglini@arm.com} 31113481Sgiacomo.travaglini@arm.com 31213481Sgiacomo.travaglini@arm.comvoid 31313481Sgiacomo.travaglini@arm.comTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 31413481Sgiacomo.travaglini@arm.com RequestPtr req, uint8_t *data, bool read) 31513481Sgiacomo.travaglini@arm.com{ 31613481Sgiacomo.travaglini@arm.com PacketPtr pkt1, pkt2; 31713481Sgiacomo.travaglini@arm.com buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 31813481Sgiacomo.travaglini@arm.com if (req->getFlags().isSet(Request::NO_ACCESS)) { 31913481Sgiacomo.travaglini@arm.com assert(!dcache_pkt); 32013481Sgiacomo.travaglini@arm.com pkt1->makeResponse(); 32113481Sgiacomo.travaglini@arm.com completeDataAccess(pkt1); 32213481Sgiacomo.travaglini@arm.com } else if (read) { 32313481Sgiacomo.travaglini@arm.com SplitFragmentSenderState * send_state = 32413481Sgiacomo.travaglini@arm.com dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 32513481Sgiacomo.travaglini@arm.com if (handleReadPacket(pkt1)) { 32613481Sgiacomo.travaglini@arm.com send_state->clearFromParent(); 32713481Sgiacomo.travaglini@arm.com send_state = dynamic_cast<SplitFragmentSenderState *>( 32813481Sgiacomo.travaglini@arm.com pkt2->senderState); 32913481Sgiacomo.travaglini@arm.com if (handleReadPacket(pkt2)) { 33013481Sgiacomo.travaglini@arm.com send_state->clearFromParent(); 33113481Sgiacomo.travaglini@arm.com } 33213481Sgiacomo.travaglini@arm.com } 33313481Sgiacomo.travaglini@arm.com } else { 33413481Sgiacomo.travaglini@arm.com dcache_pkt = pkt1; 33513481Sgiacomo.travaglini@arm.com SplitFragmentSenderState * send_state = 33613481Sgiacomo.travaglini@arm.com dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 33713481Sgiacomo.travaglini@arm.com if (handleWritePacket()) { 33813481Sgiacomo.travaglini@arm.com send_state->clearFromParent(); 33913481Sgiacomo.travaglini@arm.com dcache_pkt = pkt2; 34013481Sgiacomo.travaglini@arm.com send_state = dynamic_cast<SplitFragmentSenderState *>( 34113481Sgiacomo.travaglini@arm.com pkt2->senderState); 34213481Sgiacomo.travaglini@arm.com if (handleWritePacket()) { 34313481Sgiacomo.travaglini@arm.com send_state->clearFromParent(); 34413481Sgiacomo.travaglini@arm.com } 34513481Sgiacomo.travaglini@arm.com } 34613481Sgiacomo.travaglini@arm.com } 34713481Sgiacomo.travaglini@arm.com} 34813481Sgiacomo.travaglini@arm.com 34913481Sgiacomo.travaglini@arm.comvoid 35013481Sgiacomo.travaglini@arm.comTimingSimpleCPU::translationFault(const Fault &fault) 35113481Sgiacomo.travaglini@arm.com{ 35213481Sgiacomo.travaglini@arm.com // fault may be NoFault in cases where a fault is suppressed, 35313481Sgiacomo.travaglini@arm.com // for instance prefetches. 35413481Sgiacomo.travaglini@arm.com updateCycleCounts(); 35513481Sgiacomo.travaglini@arm.com 35613481Sgiacomo.travaglini@arm.com if (traceData) { 35713481Sgiacomo.travaglini@arm.com // Since there was a fault, we shouldn't trace this instruction. 35813481Sgiacomo.travaglini@arm.com delete traceData; 35913481Sgiacomo.travaglini@arm.com traceData = NULL; 36013481Sgiacomo.travaglini@arm.com } 36113481Sgiacomo.travaglini@arm.com 36213481Sgiacomo.travaglini@arm.com postExecute(); 36313481Sgiacomo.travaglini@arm.com 36413481Sgiacomo.travaglini@arm.com advanceInst(fault); 36513481Sgiacomo.travaglini@arm.com} 36613481Sgiacomo.travaglini@arm.com 36713481Sgiacomo.travaglini@arm.comPacketPtr 36813481Sgiacomo.travaglini@arm.comTimingSimpleCPU::buildPacket(RequestPtr req, bool read) 36913481Sgiacomo.travaglini@arm.com{ 37013481Sgiacomo.travaglini@arm.com return read ? Packet::createRead(req) : Packet::createWrite(req); 37113481Sgiacomo.travaglini@arm.com} 37213481Sgiacomo.travaglini@arm.com 37313481Sgiacomo.travaglini@arm.comvoid 37413481Sgiacomo.travaglini@arm.comTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 37513481Sgiacomo.travaglini@arm.com RequestPtr req1, RequestPtr req2, RequestPtr req, 37613481Sgiacomo.travaglini@arm.com uint8_t *data, bool read) 37713481Sgiacomo.travaglini@arm.com{ 37813481Sgiacomo.travaglini@arm.com pkt1 = pkt2 = NULL; 37913481Sgiacomo.travaglini@arm.com 38013481Sgiacomo.travaglini@arm.com assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 38113481Sgiacomo.travaglini@arm.com 38213481Sgiacomo.travaglini@arm.com if (req->getFlags().isSet(Request::NO_ACCESS)) { 38313481Sgiacomo.travaglini@arm.com pkt1 = buildPacket(req, read); 38413481Sgiacomo.travaglini@arm.com return; 38513481Sgiacomo.travaglini@arm.com } 38613481Sgiacomo.travaglini@arm.com 38713481Sgiacomo.travaglini@arm.com pkt1 = buildPacket(req1, read); 38813481Sgiacomo.travaglini@arm.com pkt2 = buildPacket(req2, read); 38913481Sgiacomo.travaglini@arm.com 39013481Sgiacomo.travaglini@arm.com PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 39113481Sgiacomo.travaglini@arm.com 39213481Sgiacomo.travaglini@arm.com pkt->dataDynamic<uint8_t>(data); 39313481Sgiacomo.travaglini@arm.com pkt1->dataStatic<uint8_t>(data); 39413481Sgiacomo.travaglini@arm.com pkt2->dataStatic<uint8_t>(data + req1->getSize()); 39513481Sgiacomo.travaglini@arm.com 39613481Sgiacomo.travaglini@arm.com SplitMainSenderState * main_send_state = new SplitMainSenderState; 39713481Sgiacomo.travaglini@arm.com pkt->senderState = main_send_state; 39813481Sgiacomo.travaglini@arm.com main_send_state->fragments[0] = pkt1; 39913481Sgiacomo.travaglini@arm.com main_send_state->fragments[1] = pkt2; 40013481Sgiacomo.travaglini@arm.com main_send_state->outstanding = 2; 40113481Sgiacomo.travaglini@arm.com pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 40213481Sgiacomo.travaglini@arm.com pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 40313481Sgiacomo.travaglini@arm.com} 40413481Sgiacomo.travaglini@arm.com 40513481Sgiacomo.travaglini@arm.comFault 40613481Sgiacomo.travaglini@arm.comTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 40713481Sgiacomo.travaglini@arm.com unsigned size, unsigned flags) 40813481Sgiacomo.travaglini@arm.com{ 40913481Sgiacomo.travaglini@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 41013481Sgiacomo.travaglini@arm.com SimpleThread* thread = t_info.thread; 41113481Sgiacomo.travaglini@arm.com 41213481Sgiacomo.travaglini@arm.com Fault fault; 41313481Sgiacomo.travaglini@arm.com const int asid = 0; 41413481Sgiacomo.travaglini@arm.com const ThreadID tid = curThread; 41513481Sgiacomo.travaglini@arm.com const Addr pc = thread->instAddr(); 41613481Sgiacomo.travaglini@arm.com unsigned block_size = cacheLineSize(); 41713481Sgiacomo.travaglini@arm.com BaseTLB::Mode mode = BaseTLB::Read; 41813481Sgiacomo.travaglini@arm.com 41913481Sgiacomo.travaglini@arm.com if (traceData) 42013481Sgiacomo.travaglini@arm.com traceData->setMem(addr, size, flags); 42113481Sgiacomo.travaglini@arm.com 42213481Sgiacomo.travaglini@arm.com RequestPtr req = new Request(asid, addr, size, 42313481Sgiacomo.travaglini@arm.com flags, dataMasterId(), pc, 42413481Sgiacomo.travaglini@arm.com thread->contextId(), tid); 42513481Sgiacomo.travaglini@arm.com 42613481Sgiacomo.travaglini@arm.com req->taskId(taskId()); 42713481Sgiacomo.travaglini@arm.com 42813481Sgiacomo.travaglini@arm.com Addr split_addr = roundDown(addr + size - 1, block_size); 42913481Sgiacomo.travaglini@arm.com assert(split_addr <= addr || split_addr - addr < block_size); 43013481Sgiacomo.travaglini@arm.com 43113481Sgiacomo.travaglini@arm.com _status = DTBWaitResponse; 43213481Sgiacomo.travaglini@arm.com if (split_addr > addr) { 43313481Sgiacomo.travaglini@arm.com RequestPtr req1, req2; 43413481Sgiacomo.travaglini@arm.com assert(!req->isLLSC() && !req->isSwap()); 43513481Sgiacomo.travaglini@arm.com req->splitOnVaddr(split_addr, req1, req2); 43613481Sgiacomo.travaglini@arm.com 43713481Sgiacomo.travaglini@arm.com WholeTranslationState *state = 43813481Sgiacomo.travaglini@arm.com new WholeTranslationState(req, req1, req2, new uint8_t[size], 43913481Sgiacomo.travaglini@arm.com NULL, mode); 44013481Sgiacomo.travaglini@arm.com DataTranslation<TimingSimpleCPU *> *trans1 = 44113481Sgiacomo.travaglini@arm.com new DataTranslation<TimingSimpleCPU *>(this, state, 0); 44213481Sgiacomo.travaglini@arm.com DataTranslation<TimingSimpleCPU *> *trans2 = 44313481Sgiacomo.travaglini@arm.com new DataTranslation<TimingSimpleCPU *>(this, state, 1); 44413481Sgiacomo.travaglini@arm.com 44513481Sgiacomo.travaglini@arm.com thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 44613481Sgiacomo.travaglini@arm.com thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 44713481Sgiacomo.travaglini@arm.com } else { 44813481Sgiacomo.travaglini@arm.com WholeTranslationState *state = 44913481Sgiacomo.travaglini@arm.com new WholeTranslationState(req, new uint8_t[size], NULL, mode); 45013481Sgiacomo.travaglini@arm.com DataTranslation<TimingSimpleCPU *> *translation 45113481Sgiacomo.travaglini@arm.com = new DataTranslation<TimingSimpleCPU *>(this, state); 45213481Sgiacomo.travaglini@arm.com thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 45313481Sgiacomo.travaglini@arm.com } 45413481Sgiacomo.travaglini@arm.com 45513481Sgiacomo.travaglini@arm.com return NoFault; 45613481Sgiacomo.travaglini@arm.com} 45713481Sgiacomo.travaglini@arm.com 45813481Sgiacomo.travaglini@arm.combool 45913481Sgiacomo.travaglini@arm.comTimingSimpleCPU::handleWritePacket() 46013481Sgiacomo.travaglini@arm.com{ 46113481Sgiacomo.travaglini@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 46213481Sgiacomo.travaglini@arm.com SimpleThread* thread = t_info.thread; 46313481Sgiacomo.travaglini@arm.com 46413481Sgiacomo.travaglini@arm.com RequestPtr req = dcache_pkt->req; 46513481Sgiacomo.travaglini@arm.com if (req->isMmappedIpr()) { 46613481Sgiacomo.travaglini@arm.com Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 46713481Sgiacomo.travaglini@arm.com new IprEvent(dcache_pkt, this, clockEdge(delay)); 46813481Sgiacomo.travaglini@arm.com _status = DcacheWaitResponse; 46913481Sgiacomo.travaglini@arm.com dcache_pkt = NULL; 47013481Sgiacomo.travaglini@arm.com } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 47113481Sgiacomo.travaglini@arm.com _status = DcacheRetry; 47213481Sgiacomo.travaglini@arm.com } else { 47313481Sgiacomo.travaglini@arm.com _status = DcacheWaitResponse; 47413481Sgiacomo.travaglini@arm.com // memory system takes ownership of packet 47513481Sgiacomo.travaglini@arm.com dcache_pkt = NULL; 47613481Sgiacomo.travaglini@arm.com } 47713481Sgiacomo.travaglini@arm.com return dcache_pkt == NULL; 47813481Sgiacomo.travaglini@arm.com} 47913481Sgiacomo.travaglini@arm.com 48013481Sgiacomo.travaglini@arm.comFault 48113481Sgiacomo.travaglini@arm.comTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 48213481Sgiacomo.travaglini@arm.com Addr addr, unsigned flags, uint64_t *res) 48313481Sgiacomo.travaglini@arm.com{ 48413481Sgiacomo.travaglini@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 48513481Sgiacomo.travaglini@arm.com SimpleThread* thread = t_info.thread; 48613481Sgiacomo.travaglini@arm.com 48713481Sgiacomo.travaglini@arm.com uint8_t *newData = new uint8_t[size]; 48813481Sgiacomo.travaglini@arm.com const int asid = 0; 48913481Sgiacomo.travaglini@arm.com const ThreadID tid = curThread; 49013481Sgiacomo.travaglini@arm.com const Addr pc = thread->instAddr(); 49113481Sgiacomo.travaglini@arm.com unsigned block_size = cacheLineSize(); 49213481Sgiacomo.travaglini@arm.com BaseTLB::Mode mode = BaseTLB::Write; 49313481Sgiacomo.travaglini@arm.com 49413481Sgiacomo.travaglini@arm.com if (data == NULL) { 49513481Sgiacomo.travaglini@arm.com assert(flags & Request::CACHE_BLOCK_ZERO); 49613481Sgiacomo.travaglini@arm.com // This must be a cache block cleaning request 49713481Sgiacomo.travaglini@arm.com memset(newData, 0, size); 498 } else { 499 memcpy(newData, data, size); 500 } 501 502 if (traceData) 503 traceData->setMem(addr, size, flags); 504 505 RequestPtr req = new Request(asid, addr, size, 506 flags, dataMasterId(), pc, 507 thread->contextId(), tid); 508 509 req->taskId(taskId()); 510 511 Addr split_addr = roundDown(addr + size - 1, block_size); 512 assert(split_addr <= addr || split_addr - addr < block_size); 513 514 _status = DTBWaitResponse; 515 if (split_addr > addr) { 516 RequestPtr req1, req2; 517 assert(!req->isLLSC() && !req->isSwap()); 518 req->splitOnVaddr(split_addr, req1, req2); 519 520 WholeTranslationState *state = 521 new WholeTranslationState(req, req1, req2, newData, res, mode); 522 DataTranslation<TimingSimpleCPU *> *trans1 = 523 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 524 DataTranslation<TimingSimpleCPU *> *trans2 = 525 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 526 527 thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 528 thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 529 } else { 530 WholeTranslationState *state = 531 new WholeTranslationState(req, newData, res, mode); 532 DataTranslation<TimingSimpleCPU *> *translation = 533 new DataTranslation<TimingSimpleCPU *>(this, state); 534 thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 535 } 536 537 // Translation faults will be returned via finishTranslation() 538 return NoFault; 539} 540 541 542void 543TimingSimpleCPU::finishTranslation(WholeTranslationState *state) 544{ 545 _status = BaseSimpleCPU::Running; 546 547 if (state->getFault() != NoFault) { 548 if (state->isPrefetch()) { 549 state->setNoFault(); 550 } 551 delete [] state->data; 552 state->deleteReqs(); 553 translationFault(state->getFault()); 554 } else { 555 if (!state->isSplit) { 556 sendData(state->mainReq, state->data, state->res, 557 state->mode == BaseTLB::Read); 558 } else { 559 sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 560 state->data, state->mode == BaseTLB::Read); 561 } 562 } 563 564 delete state; 565} 566 567 568void 569TimingSimpleCPU::fetch() 570{ 571 // Change thread if multi-threaded 572 swapActiveThread(); 573 574 SimpleExecContext &t_info = *threadInfo[curThread]; 575 SimpleThread* thread = t_info.thread; 576 577 DPRINTF(SimpleCPU, "Fetch\n"); 578 579 if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 580 checkForInterrupts(); 581 checkPcEventQueue(); 582 } 583 584 // We must have just got suspended by a PC event 585 if (_status == Idle) 586 return; 587 588 TheISA::PCState pcState = thread->pcState(); 589 bool needToFetch = !isRomMicroPC(pcState.microPC()) && 590 !curMacroStaticInst; 591 592 if (needToFetch) { 593 _status = BaseSimpleCPU::Running; 594 Request *ifetch_req = new Request(); 595 ifetch_req->taskId(taskId()); 596 ifetch_req->setThreadContext(thread->contextId(), curThread); 597 setupFetchRequest(ifetch_req); 598 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 599 thread->itb->translateTiming(ifetch_req, thread->getTC(), 600 &fetchTranslation, BaseTLB::Execute); 601 } else { 602 _status = IcacheWaitResponse; 603 completeIfetch(NULL); 604 605 updateCycleCounts(); 606 } 607} 608 609 610void 611TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, 612 ThreadContext *tc) 613{ 614 if (fault == NoFault) { 615 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 616 req->getVaddr(), req->getPaddr()); 617 ifetch_pkt = new Packet(req, MemCmd::ReadReq); 618 ifetch_pkt->dataStatic(&inst); 619 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 620 621 if (!icachePort.sendTimingReq(ifetch_pkt)) { 622 // Need to wait for retry 623 _status = IcacheRetry; 624 } else { 625 // Need to wait for cache to respond 626 _status = IcacheWaitResponse; 627 // ownership of packet transferred to memory system 628 ifetch_pkt = NULL; 629 } 630 } else { 631 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 632 delete req; 633 // fetch fault: advance directly to next instruction (fault handler) 634 _status = BaseSimpleCPU::Running; 635 advanceInst(fault); 636 } 637 638 updateCycleCounts(); 639} 640 641 642void 643TimingSimpleCPU::advanceInst(const Fault &fault) 644{ 645 SimpleExecContext &t_info = *threadInfo[curThread]; 646 647 if (_status == Faulting) 648 return; 649 650 if (fault != NoFault) { 651 advancePC(fault); 652 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 653 reschedule(fetchEvent, clockEdge(), true); 654 _status = Faulting; 655 return; 656 } 657 658 659 if (!t_info.stayAtPC) 660 advancePC(fault); 661 662 if (tryCompleteDrain()) 663 return; 664 665 if (_status == BaseSimpleCPU::Running) { 666 // kick off fetch of next instruction... callback from icache 667 // response will cause that instruction to be executed, 668 // keeping the CPU running. 669 fetch(); 670 } 671} 672 673 674void 675TimingSimpleCPU::completeIfetch(PacketPtr pkt) 676{ 677 SimpleExecContext& t_info = *threadInfo[curThread]; 678 679 DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 680 pkt->getAddr() : 0); 681 682 // received a response from the icache: execute the received 683 // instruction 684 assert(!pkt || !pkt->isError()); 685 assert(_status == IcacheWaitResponse); 686 687 _status = BaseSimpleCPU::Running; 688 689 updateCycleCounts(); 690 691 if (pkt) 692 pkt->req->setAccessLatency(); 693 694 695 preExecute(); 696 if (curStaticInst && curStaticInst->isMemRef()) { 697 // load or store: just send to dcache 698 Fault fault = curStaticInst->initiateAcc(&t_info, traceData); 699 700 // If we're not running now the instruction will complete in a dcache 701 // response callback or the instruction faulted and has started an 702 // ifetch 703 if (_status == BaseSimpleCPU::Running) { 704 if (fault != NoFault && traceData) { 705 // If there was a fault, we shouldn't trace this instruction. 706 delete traceData; 707 traceData = NULL; 708 } 709 710 postExecute(); 711 // @todo remove me after debugging with legion done 712 if (curStaticInst && (!curStaticInst->isMicroop() || 713 curStaticInst->isFirstMicroop())) 714 instCnt++; 715 advanceInst(fault); 716 } 717 } else if (curStaticInst) { 718 // non-memory instruction: execute completely now 719 Fault fault = curStaticInst->execute(&t_info, traceData); 720 721 // keep an instruction count 722 if (fault == NoFault) 723 countInst(); 724 else if (traceData && !DTRACE(ExecFaulting)) { 725 delete traceData; 726 traceData = NULL; 727 } 728 729 postExecute(); 730 // @todo remove me after debugging with legion done 731 if (curStaticInst && (!curStaticInst->isMicroop() || 732 curStaticInst->isFirstMicroop())) 733 instCnt++; 734 advanceInst(fault); 735 } else { 736 advanceInst(NoFault); 737 } 738 739 if (pkt) { 740 delete pkt->req; 741 delete pkt; 742 } 743} 744 745void 746TimingSimpleCPU::IcachePort::ITickEvent::process() 747{ 748 cpu->completeIfetch(pkt); 749} 750 751bool 752TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 753{ 754 DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr()); 755 // we should only ever see one response per cycle since we only 756 // issue a new request once this response is sunk 757 assert(!tickEvent.scheduled()); 758 // delay processing of returned data until next CPU clock edge 759 tickEvent.schedule(pkt, cpu->clockEdge()); 760 761 return true; 762} 763 764void 765TimingSimpleCPU::IcachePort::recvReqRetry() 766{ 767 // we shouldn't get a retry unless we have a packet that we're 768 // waiting to transmit 769 assert(cpu->ifetch_pkt != NULL); 770 assert(cpu->_status == IcacheRetry); 771 PacketPtr tmp = cpu->ifetch_pkt; 772 if (sendTimingReq(tmp)) { 773 cpu->_status = IcacheWaitResponse; 774 cpu->ifetch_pkt = NULL; 775 } 776} 777 778void 779TimingSimpleCPU::completeDataAccess(PacketPtr pkt) 780{ 781 // received a response from the dcache: complete the load or store 782 // instruction 783 assert(!pkt->isError()); 784 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 785 pkt->req->getFlags().isSet(Request::NO_ACCESS)); 786 787 pkt->req->setAccessLatency(); 788 789 updateCycleCounts(); 790 791 if (pkt->senderState) { 792 SplitFragmentSenderState * send_state = 793 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 794 assert(send_state); 795 delete pkt->req; 796 delete pkt; 797 PacketPtr big_pkt = send_state->bigPkt; 798 delete send_state; 799 800 SplitMainSenderState * main_send_state = 801 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 802 assert(main_send_state); 803 // Record the fact that this packet is no longer outstanding. 804 assert(main_send_state->outstanding != 0); 805 main_send_state->outstanding--; 806 807 if (main_send_state->outstanding) { 808 return; 809 } else { 810 delete main_send_state; 811 big_pkt->senderState = NULL; 812 pkt = big_pkt; 813 } 814 } 815 816 _status = BaseSimpleCPU::Running; 817 818 Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread], 819 traceData); 820 821 // keep an instruction count 822 if (fault == NoFault) 823 countInst(); 824 else if (traceData) { 825 // If there was a fault, we shouldn't trace this instruction. 826 delete traceData; 827 traceData = NULL; 828 } 829 830 delete pkt->req; 831 delete pkt; 832 833 postExecute(); 834 835 advanceInst(fault); 836} 837 838void 839TimingSimpleCPU::updateCycleCounts() 840{ 841 const Cycles delta(curCycle() - previousCycle); 842 843 numCycles += delta; 844 ppCycles->notify(delta); 845 846 previousCycle = curCycle(); 847} 848 849void 850TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 851{ 852 // X86 ISA: Snooping an invalidation for monitor/mwait 853 if(cpu->getCpuAddrMonitor()->doMonitor(pkt)) { 854 cpu->wakeup(); 855 } 856 857 for (auto &t_info : cpu->threadInfo) { 858 TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 859 } 860} 861 862void 863TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) 864{ 865 // X86 ISA: Snooping an invalidation for monitor/mwait 866 if(cpu->getCpuAddrMonitor()->doMonitor(pkt)) { 867 cpu->wakeup(); 868 } 869} 870 871bool 872TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 873{ 874 DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr()); 875 876 // The timing CPU is not really ticked, instead it relies on the 877 // memory system (fetch and load/store) to set the pace. 878 if (!tickEvent.scheduled()) { 879 // Delay processing of returned data until next CPU clock edge 880 tickEvent.schedule(pkt, cpu->clockEdge()); 881 return true; 882 } else { 883 // In the case of a split transaction and a cache that is 884 // faster than a CPU we could get two responses in the 885 // same tick, delay the second one 886 if (!retryRespEvent.scheduled()) 887 cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1))); 888 return false; 889 } 890} 891 892void 893TimingSimpleCPU::DcachePort::DTickEvent::process() 894{ 895 cpu->completeDataAccess(pkt); 896} 897 898void 899TimingSimpleCPU::DcachePort::recvReqRetry() 900{ 901 // we shouldn't get a retry unless we have a packet that we're 902 // waiting to transmit 903 assert(cpu->dcache_pkt != NULL); 904 assert(cpu->_status == DcacheRetry); 905 PacketPtr tmp = cpu->dcache_pkt; 906 if (tmp->senderState) { 907 // This is a packet from a split access. 908 SplitFragmentSenderState * send_state = 909 dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 910 assert(send_state); 911 PacketPtr big_pkt = send_state->bigPkt; 912 913 SplitMainSenderState * main_send_state = 914 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 915 assert(main_send_state); 916 917 if (sendTimingReq(tmp)) { 918 // If we were able to send without retrying, record that fact 919 // and try sending the other fragment. 920 send_state->clearFromParent(); 921 int other_index = main_send_state->getPendingFragment(); 922 if (other_index > 0) { 923 tmp = main_send_state->fragments[other_index]; 924 cpu->dcache_pkt = tmp; 925 if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 926 (big_pkt->isWrite() && cpu->handleWritePacket())) { 927 main_send_state->fragments[other_index] = NULL; 928 } 929 } else { 930 cpu->_status = DcacheWaitResponse; 931 // memory system takes ownership of packet 932 cpu->dcache_pkt = NULL; 933 } 934 } 935 } else if (sendTimingReq(tmp)) { 936 cpu->_status = DcacheWaitResponse; 937 // memory system takes ownership of packet 938 cpu->dcache_pkt = NULL; 939 } 940} 941 942TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 943 Tick t) 944 : pkt(_pkt), cpu(_cpu) 945{ 946 cpu->schedule(this, t); 947} 948 949void 950TimingSimpleCPU::IprEvent::process() 951{ 952 cpu->completeDataAccess(pkt); 953} 954 955const char * 956TimingSimpleCPU::IprEvent::description() const 957{ 958 return "Timing Simple CPU Delay IPR event"; 959} 960 961 962void 963TimingSimpleCPU::printAddr(Addr a) 964{ 965 dcachePort.printAddr(a); 966} 967 968 969//////////////////////////////////////////////////////////////////////// 970// 971// TimingSimpleCPU Simulation Object 972// 973TimingSimpleCPU * 974TimingSimpleCPUParams::create() 975{ 976 return new TimingSimpleCPU(this); 977} 978