timing.cc revision 10913:38dbdeea7f1f
1/* 2 * Copyright 2014 Google, Inc. 3 * Copyright (c) 2010-2013 ARM Limited 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2002-2005 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 */ 43 44#include "arch/locked_mem.hh" 45#include "arch/mmapped_ipr.hh" 46#include "arch/utility.hh" 47#include "base/bigint.hh" 48#include "config/the_isa.hh" 49#include "cpu/simple/timing.hh" 50#include "cpu/exetrace.hh" 51#include "debug/Config.hh" 52#include "debug/Drain.hh" 53#include "debug/ExecFaulting.hh" 54#include "debug/SimpleCPU.hh" 55#include "mem/packet.hh" 56#include "mem/packet_access.hh" 57#include "params/TimingSimpleCPU.hh" 58#include "sim/faults.hh" 59#include "sim/full_system.hh" 60#include "sim/system.hh" 61 62#include "debug/Mwait.hh" 63 64using namespace std; 65using namespace TheISA; 66 67void 68TimingSimpleCPU::init() 69{ 70 BaseCPU::init(); 71 72 // Initialise the ThreadContext's memory proxies 73 tcBase()->initMemProxies(tcBase()); 74 75 if (FullSystem && !params()->switched_out) { 76 for (int i = 0; i < threadContexts.size(); ++i) { 77 ThreadContext *tc = threadContexts[i]; 78 // initialize CPU, including PC 79 TheISA::initCPU(tc, _cpuId); 80 } 81 } 82} 83 84void 85TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 86{ 87 pkt = _pkt; 88 cpu->schedule(this, t); 89} 90 91TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 92 : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 93 dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 94 fetchEvent(this) 95{ 96 _status = Idle; 97} 98 99 100 101TimingSimpleCPU::~TimingSimpleCPU() 102{ 103} 104 105DrainState 106TimingSimpleCPU::drain() 107{ 108 if (switchedOut()) 109 return DrainState::Drained; 110 111 if (_status == Idle || 112 (_status == BaseSimpleCPU::Running && isDrained())) { 113 DPRINTF(Drain, "No need to drain.\n"); 114 return DrainState::Drained; 115 } else { 116 DPRINTF(Drain, "Requesting drain: %s\n", pcState()); 117 118 // The fetch event can become descheduled if a drain didn't 119 // succeed on the first attempt. We need to reschedule it if 120 // the CPU is waiting for a microcode routine to complete. 121 if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 122 schedule(fetchEvent, clockEdge()); 123 124 return DrainState::Draining; 125 } 126} 127 128void 129TimingSimpleCPU::drainResume() 130{ 131 assert(!fetchEvent.scheduled()); 132 if (switchedOut()) 133 return; 134 135 DPRINTF(SimpleCPU, "Resume\n"); 136 verifyMemoryMode(); 137 138 assert(!threadContexts.empty()); 139 if (threadContexts.size() > 1) 140 fatal("The timing CPU only supports one thread.\n"); 141 142 if (thread->status() == ThreadContext::Active) { 143 schedule(fetchEvent, nextCycle()); 144 _status = BaseSimpleCPU::Running; 145 notIdleFraction = 1; 146 } else { 147 _status = BaseSimpleCPU::Idle; 148 notIdleFraction = 0; 149 } 150} 151 152bool 153TimingSimpleCPU::tryCompleteDrain() 154{ 155 if (drainState() != DrainState::Draining) 156 return false; 157 158 DPRINTF(Drain, "tryCompleteDrain: %s\n", pcState()); 159 if (!isDrained()) 160 return false; 161 162 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 163 signalDrainDone(); 164 165 return true; 166} 167 168void 169TimingSimpleCPU::switchOut() 170{ 171 BaseSimpleCPU::switchOut(); 172 173 assert(!fetchEvent.scheduled()); 174 assert(_status == BaseSimpleCPU::Running || _status == Idle); 175 assert(!stayAtPC); 176 assert(microPC() == 0); 177 178 updateCycleCounts(); 179} 180 181 182void 183TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 184{ 185 BaseSimpleCPU::takeOverFrom(oldCPU); 186 187 previousCycle = curCycle(); 188} 189 190void 191TimingSimpleCPU::verifyMemoryMode() const 192{ 193 if (!system->isTimingMode()) { 194 fatal("The timing CPU requires the memory system to be in " 195 "'timing' mode.\n"); 196 } 197} 198 199void 200TimingSimpleCPU::activateContext(ThreadID thread_num) 201{ 202 DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 203 204 assert(thread_num == 0); 205 assert(thread); 206 207 assert(_status == Idle); 208 209 notIdleFraction = 1; 210 _status = BaseSimpleCPU::Running; 211 212 // kick things off by initiating the fetch of the next instruction 213 schedule(fetchEvent, clockEdge(Cycles(0))); 214} 215 216 217void 218TimingSimpleCPU::suspendContext(ThreadID thread_num) 219{ 220 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 221 222 assert(thread_num == 0); 223 assert(thread); 224 225 if (_status == Idle) 226 return; 227 228 assert(_status == BaseSimpleCPU::Running); 229 230 // just change status to Idle... if status != Running, 231 // completeInst() will not initiate fetch of next instruction. 232 233 notIdleFraction = 0; 234 _status = Idle; 235} 236 237bool 238TimingSimpleCPU::handleReadPacket(PacketPtr pkt) 239{ 240 RequestPtr req = pkt->req; 241 242 // We're about the issues a locked load, so tell the monitor 243 // to start caring about this address 244 if (pkt->isRead() && pkt->req->isLLSC()) { 245 TheISA::handleLockedRead(thread, pkt->req); 246 } 247 if (req->isMmappedIpr()) { 248 Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 249 new IprEvent(pkt, this, clockEdge(delay)); 250 _status = DcacheWaitResponse; 251 dcache_pkt = NULL; 252 } else if (!dcachePort.sendTimingReq(pkt)) { 253 _status = DcacheRetry; 254 dcache_pkt = pkt; 255 } else { 256 _status = DcacheWaitResponse; 257 // memory system takes ownership of packet 258 dcache_pkt = NULL; 259 } 260 return dcache_pkt == NULL; 261} 262 263void 264TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 265 bool read) 266{ 267 PacketPtr pkt = buildPacket(req, read); 268 pkt->dataDynamic<uint8_t>(data); 269 if (req->getFlags().isSet(Request::NO_ACCESS)) { 270 assert(!dcache_pkt); 271 pkt->makeResponse(); 272 completeDataAccess(pkt); 273 } else if (read) { 274 handleReadPacket(pkt); 275 } else { 276 bool do_access = true; // flag to suppress cache access 277 278 if (req->isLLSC()) { 279 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 280 } else if (req->isCondSwap()) { 281 assert(res); 282 req->setExtraData(*res); 283 } 284 285 if (do_access) { 286 dcache_pkt = pkt; 287 handleWritePacket(); 288 } else { 289 _status = DcacheWaitResponse; 290 completeDataAccess(pkt); 291 } 292 } 293} 294 295void 296TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 297 RequestPtr req, uint8_t *data, bool read) 298{ 299 PacketPtr pkt1, pkt2; 300 buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 301 if (req->getFlags().isSet(Request::NO_ACCESS)) { 302 assert(!dcache_pkt); 303 pkt1->makeResponse(); 304 completeDataAccess(pkt1); 305 } else if (read) { 306 SplitFragmentSenderState * send_state = 307 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 308 if (handleReadPacket(pkt1)) { 309 send_state->clearFromParent(); 310 send_state = dynamic_cast<SplitFragmentSenderState *>( 311 pkt2->senderState); 312 if (handleReadPacket(pkt2)) { 313 send_state->clearFromParent(); 314 } 315 } 316 } else { 317 dcache_pkt = pkt1; 318 SplitFragmentSenderState * send_state = 319 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 320 if (handleWritePacket()) { 321 send_state->clearFromParent(); 322 dcache_pkt = pkt2; 323 send_state = dynamic_cast<SplitFragmentSenderState *>( 324 pkt2->senderState); 325 if (handleWritePacket()) { 326 send_state->clearFromParent(); 327 } 328 } 329 } 330} 331 332void 333TimingSimpleCPU::translationFault(const Fault &fault) 334{ 335 // fault may be NoFault in cases where a fault is suppressed, 336 // for instance prefetches. 337 updateCycleCounts(); 338 339 if (traceData) { 340 // Since there was a fault, we shouldn't trace this instruction. 341 delete traceData; 342 traceData = NULL; 343 } 344 345 postExecute(); 346 347 advanceInst(fault); 348} 349 350PacketPtr 351TimingSimpleCPU::buildPacket(RequestPtr req, bool read) 352{ 353 return read ? Packet::createRead(req) : Packet::createWrite(req); 354} 355 356void 357TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 358 RequestPtr req1, RequestPtr req2, RequestPtr req, 359 uint8_t *data, bool read) 360{ 361 pkt1 = pkt2 = NULL; 362 363 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 364 365 if (req->getFlags().isSet(Request::NO_ACCESS)) { 366 pkt1 = buildPacket(req, read); 367 return; 368 } 369 370 pkt1 = buildPacket(req1, read); 371 pkt2 = buildPacket(req2, read); 372 373 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 374 375 pkt->dataDynamic<uint8_t>(data); 376 pkt1->dataStatic<uint8_t>(data); 377 pkt2->dataStatic<uint8_t>(data + req1->getSize()); 378 379 SplitMainSenderState * main_send_state = new SplitMainSenderState; 380 pkt->senderState = main_send_state; 381 main_send_state->fragments[0] = pkt1; 382 main_send_state->fragments[1] = pkt2; 383 main_send_state->outstanding = 2; 384 pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 385 pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 386} 387 388Fault 389TimingSimpleCPU::readMem(Addr addr, uint8_t *data, 390 unsigned size, unsigned flags) 391{ 392 Fault fault; 393 const int asid = 0; 394 const ThreadID tid = 0; 395 const Addr pc = thread->instAddr(); 396 unsigned block_size = cacheLineSize(); 397 BaseTLB::Mode mode = BaseTLB::Read; 398 399 if (traceData) 400 traceData->setMem(addr, size, flags); 401 402 RequestPtr req = new Request(asid, addr, size, 403 flags, dataMasterId(), pc, _cpuId, tid); 404 405 req->taskId(taskId()); 406 407 Addr split_addr = roundDown(addr + size - 1, block_size); 408 assert(split_addr <= addr || split_addr - addr < block_size); 409 410 _status = DTBWaitResponse; 411 if (split_addr > addr) { 412 RequestPtr req1, req2; 413 assert(!req->isLLSC() && !req->isSwap()); 414 req->splitOnVaddr(split_addr, req1, req2); 415 416 WholeTranslationState *state = 417 new WholeTranslationState(req, req1, req2, new uint8_t[size], 418 NULL, mode); 419 DataTranslation<TimingSimpleCPU *> *trans1 = 420 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 421 DataTranslation<TimingSimpleCPU *> *trans2 = 422 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 423 424 thread->dtb->translateTiming(req1, tc, trans1, mode); 425 thread->dtb->translateTiming(req2, tc, trans2, mode); 426 } else { 427 WholeTranslationState *state = 428 new WholeTranslationState(req, new uint8_t[size], NULL, mode); 429 DataTranslation<TimingSimpleCPU *> *translation 430 = new DataTranslation<TimingSimpleCPU *>(this, state); 431 thread->dtb->translateTiming(req, tc, translation, mode); 432 } 433 434 return NoFault; 435} 436 437bool 438TimingSimpleCPU::handleWritePacket() 439{ 440 RequestPtr req = dcache_pkt->req; 441 if (req->isMmappedIpr()) { 442 Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 443 new IprEvent(dcache_pkt, this, clockEdge(delay)); 444 _status = DcacheWaitResponse; 445 dcache_pkt = NULL; 446 } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 447 _status = DcacheRetry; 448 } else { 449 _status = DcacheWaitResponse; 450 // memory system takes ownership of packet 451 dcache_pkt = NULL; 452 } 453 return dcache_pkt == NULL; 454} 455 456Fault 457TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 458 Addr addr, unsigned flags, uint64_t *res) 459{ 460 uint8_t *newData = new uint8_t[size]; 461 const int asid = 0; 462 const ThreadID tid = 0; 463 const Addr pc = thread->instAddr(); 464 unsigned block_size = cacheLineSize(); 465 BaseTLB::Mode mode = BaseTLB::Write; 466 467 if (data == NULL) { 468 assert(flags & Request::CACHE_BLOCK_ZERO); 469 // This must be a cache block cleaning request 470 memset(newData, 0, size); 471 } else { 472 memcpy(newData, data, size); 473 } 474 475 if (traceData) 476 traceData->setMem(addr, size, flags); 477 478 RequestPtr req = new Request(asid, addr, size, 479 flags, dataMasterId(), pc, _cpuId, tid); 480 481 req->taskId(taskId()); 482 483 Addr split_addr = roundDown(addr + size - 1, block_size); 484 assert(split_addr <= addr || split_addr - addr < block_size); 485 486 _status = DTBWaitResponse; 487 if (split_addr > addr) { 488 RequestPtr req1, req2; 489 assert(!req->isLLSC() && !req->isSwap()); 490 req->splitOnVaddr(split_addr, req1, req2); 491 492 WholeTranslationState *state = 493 new WholeTranslationState(req, req1, req2, newData, res, mode); 494 DataTranslation<TimingSimpleCPU *> *trans1 = 495 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 496 DataTranslation<TimingSimpleCPU *> *trans2 = 497 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 498 499 thread->dtb->translateTiming(req1, tc, trans1, mode); 500 thread->dtb->translateTiming(req2, tc, trans2, mode); 501 } else { 502 WholeTranslationState *state = 503 new WholeTranslationState(req, newData, res, mode); 504 DataTranslation<TimingSimpleCPU *> *translation = 505 new DataTranslation<TimingSimpleCPU *>(this, state); 506 thread->dtb->translateTiming(req, tc, translation, mode); 507 } 508 509 // Translation faults will be returned via finishTranslation() 510 return NoFault; 511} 512 513 514void 515TimingSimpleCPU::finishTranslation(WholeTranslationState *state) 516{ 517 _status = BaseSimpleCPU::Running; 518 519 if (state->getFault() != NoFault) { 520 if (state->isPrefetch()) { 521 state->setNoFault(); 522 } 523 delete [] state->data; 524 state->deleteReqs(); 525 translationFault(state->getFault()); 526 } else { 527 if (!state->isSplit) { 528 sendData(state->mainReq, state->data, state->res, 529 state->mode == BaseTLB::Read); 530 } else { 531 sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 532 state->data, state->mode == BaseTLB::Read); 533 } 534 } 535 536 delete state; 537} 538 539 540void 541TimingSimpleCPU::fetch() 542{ 543 DPRINTF(SimpleCPU, "Fetch\n"); 544 545 if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 546 checkForInterrupts(); 547 checkPcEventQueue(); 548 } 549 550 // We must have just got suspended by a PC event 551 if (_status == Idle) 552 return; 553 554 TheISA::PCState pcState = thread->pcState(); 555 bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 556 557 if (needToFetch) { 558 _status = BaseSimpleCPU::Running; 559 Request *ifetch_req = new Request(); 560 ifetch_req->taskId(taskId()); 561 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 562 setupFetchRequest(ifetch_req); 563 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 564 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 565 BaseTLB::Execute); 566 } else { 567 _status = IcacheWaitResponse; 568 completeIfetch(NULL); 569 570 updateCycleCounts(); 571 } 572} 573 574 575void 576TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, 577 ThreadContext *tc) 578{ 579 if (fault == NoFault) { 580 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 581 req->getVaddr(), req->getPaddr()); 582 ifetch_pkt = new Packet(req, MemCmd::ReadReq); 583 ifetch_pkt->dataStatic(&inst); 584 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 585 586 if (!icachePort.sendTimingReq(ifetch_pkt)) { 587 // Need to wait for retry 588 _status = IcacheRetry; 589 } else { 590 // Need to wait for cache to respond 591 _status = IcacheWaitResponse; 592 // ownership of packet transferred to memory system 593 ifetch_pkt = NULL; 594 } 595 } else { 596 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 597 delete req; 598 // fetch fault: advance directly to next instruction (fault handler) 599 _status = BaseSimpleCPU::Running; 600 advanceInst(fault); 601 } 602 603 updateCycleCounts(); 604} 605 606 607void 608TimingSimpleCPU::advanceInst(const Fault &fault) 609{ 610 if (_status == Faulting) 611 return; 612 613 if (fault != NoFault) { 614 advancePC(fault); 615 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 616 reschedule(fetchEvent, clockEdge(), true); 617 _status = Faulting; 618 return; 619 } 620 621 622 if (!stayAtPC) 623 advancePC(fault); 624 625 if (tryCompleteDrain()) 626 return; 627 628 if (_status == BaseSimpleCPU::Running) { 629 // kick off fetch of next instruction... callback from icache 630 // response will cause that instruction to be executed, 631 // keeping the CPU running. 632 fetch(); 633 } 634} 635 636 637void 638TimingSimpleCPU::completeIfetch(PacketPtr pkt) 639{ 640 DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 641 pkt->getAddr() : 0); 642 643 // received a response from the icache: execute the received 644 // instruction 645 assert(!pkt || !pkt->isError()); 646 assert(_status == IcacheWaitResponse); 647 648 _status = BaseSimpleCPU::Running; 649 650 updateCycleCounts(); 651 652 if (pkt) 653 pkt->req->setAccessLatency(); 654 655 656 preExecute(); 657 if (curStaticInst && curStaticInst->isMemRef()) { 658 // load or store: just send to dcache 659 Fault fault = curStaticInst->initiateAcc(this, traceData); 660 661 // If we're not running now the instruction will complete in a dcache 662 // response callback or the instruction faulted and has started an 663 // ifetch 664 if (_status == BaseSimpleCPU::Running) { 665 if (fault != NoFault && traceData) { 666 // If there was a fault, we shouldn't trace this instruction. 667 delete traceData; 668 traceData = NULL; 669 } 670 671 postExecute(); 672 // @todo remove me after debugging with legion done 673 if (curStaticInst && (!curStaticInst->isMicroop() || 674 curStaticInst->isFirstMicroop())) 675 instCnt++; 676 advanceInst(fault); 677 } 678 } else if (curStaticInst) { 679 // non-memory instruction: execute completely now 680 Fault fault = curStaticInst->execute(this, traceData); 681 682 // keep an instruction count 683 if (fault == NoFault) 684 countInst(); 685 else if (traceData && !DTRACE(ExecFaulting)) { 686 delete traceData; 687 traceData = NULL; 688 } 689 690 postExecute(); 691 // @todo remove me after debugging with legion done 692 if (curStaticInst && (!curStaticInst->isMicroop() || 693 curStaticInst->isFirstMicroop())) 694 instCnt++; 695 advanceInst(fault); 696 } else { 697 advanceInst(NoFault); 698 } 699 700 if (pkt) { 701 delete pkt->req; 702 delete pkt; 703 } 704} 705 706void 707TimingSimpleCPU::IcachePort::ITickEvent::process() 708{ 709 cpu->completeIfetch(pkt); 710} 711 712bool 713TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 714{ 715 DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr()); 716 // we should only ever see one response per cycle since we only 717 // issue a new request once this response is sunk 718 assert(!tickEvent.scheduled()); 719 // delay processing of returned data until next CPU clock edge 720 tickEvent.schedule(pkt, cpu->clockEdge()); 721 722 return true; 723} 724 725void 726TimingSimpleCPU::IcachePort::recvReqRetry() 727{ 728 // we shouldn't get a retry unless we have a packet that we're 729 // waiting to transmit 730 assert(cpu->ifetch_pkt != NULL); 731 assert(cpu->_status == IcacheRetry); 732 PacketPtr tmp = cpu->ifetch_pkt; 733 if (sendTimingReq(tmp)) { 734 cpu->_status = IcacheWaitResponse; 735 cpu->ifetch_pkt = NULL; 736 } 737} 738 739void 740TimingSimpleCPU::completeDataAccess(PacketPtr pkt) 741{ 742 // received a response from the dcache: complete the load or store 743 // instruction 744 assert(!pkt->isError()); 745 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 746 pkt->req->getFlags().isSet(Request::NO_ACCESS)); 747 748 pkt->req->setAccessLatency(); 749 750 updateCycleCounts(); 751 752 if (pkt->senderState) { 753 SplitFragmentSenderState * send_state = 754 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 755 assert(send_state); 756 delete pkt->req; 757 delete pkt; 758 PacketPtr big_pkt = send_state->bigPkt; 759 delete send_state; 760 761 SplitMainSenderState * main_send_state = 762 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 763 assert(main_send_state); 764 // Record the fact that this packet is no longer outstanding. 765 assert(main_send_state->outstanding != 0); 766 main_send_state->outstanding--; 767 768 if (main_send_state->outstanding) { 769 return; 770 } else { 771 delete main_send_state; 772 big_pkt->senderState = NULL; 773 pkt = big_pkt; 774 } 775 } 776 777 _status = BaseSimpleCPU::Running; 778 779 Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 780 781 // keep an instruction count 782 if (fault == NoFault) 783 countInst(); 784 else if (traceData) { 785 // If there was a fault, we shouldn't trace this instruction. 786 delete traceData; 787 traceData = NULL; 788 } 789 790 delete pkt->req; 791 delete pkt; 792 793 postExecute(); 794 795 advanceInst(fault); 796} 797 798void 799TimingSimpleCPU::updateCycleCounts() 800{ 801 const Cycles delta(curCycle() - previousCycle); 802 803 numCycles += delta; 804 ppCycles->notify(delta); 805 806 previousCycle = curCycle(); 807} 808 809void 810TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 811{ 812 // X86 ISA: Snooping an invalidation for monitor/mwait 813 if(cpu->getAddrMonitor()->doMonitor(pkt)) { 814 cpu->wakeup(); 815 } 816 TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 817} 818 819void 820TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) 821{ 822 // X86 ISA: Snooping an invalidation for monitor/mwait 823 if(cpu->getAddrMonitor()->doMonitor(pkt)) { 824 cpu->wakeup(); 825 } 826} 827 828bool 829TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 830{ 831 DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr()); 832 833 // The timing CPU is not really ticked, instead it relies on the 834 // memory system (fetch and load/store) to set the pace. 835 if (!tickEvent.scheduled()) { 836 // Delay processing of returned data until next CPU clock edge 837 tickEvent.schedule(pkt, cpu->clockEdge()); 838 return true; 839 } else { 840 // In the case of a split transaction and a cache that is 841 // faster than a CPU we could get two responses in the 842 // same tick, delay the second one 843 if (!retryRespEvent.scheduled()) 844 cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1))); 845 return false; 846 } 847} 848 849void 850TimingSimpleCPU::DcachePort::DTickEvent::process() 851{ 852 cpu->completeDataAccess(pkt); 853} 854 855void 856TimingSimpleCPU::DcachePort::recvReqRetry() 857{ 858 // we shouldn't get a retry unless we have a packet that we're 859 // waiting to transmit 860 assert(cpu->dcache_pkt != NULL); 861 assert(cpu->_status == DcacheRetry); 862 PacketPtr tmp = cpu->dcache_pkt; 863 if (tmp->senderState) { 864 // This is a packet from a split access. 865 SplitFragmentSenderState * send_state = 866 dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 867 assert(send_state); 868 PacketPtr big_pkt = send_state->bigPkt; 869 870 SplitMainSenderState * main_send_state = 871 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 872 assert(main_send_state); 873 874 if (sendTimingReq(tmp)) { 875 // If we were able to send without retrying, record that fact 876 // and try sending the other fragment. 877 send_state->clearFromParent(); 878 int other_index = main_send_state->getPendingFragment(); 879 if (other_index > 0) { 880 tmp = main_send_state->fragments[other_index]; 881 cpu->dcache_pkt = tmp; 882 if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 883 (big_pkt->isWrite() && cpu->handleWritePacket())) { 884 main_send_state->fragments[other_index] = NULL; 885 } 886 } else { 887 cpu->_status = DcacheWaitResponse; 888 // memory system takes ownership of packet 889 cpu->dcache_pkt = NULL; 890 } 891 } 892 } else if (sendTimingReq(tmp)) { 893 cpu->_status = DcacheWaitResponse; 894 // memory system takes ownership of packet 895 cpu->dcache_pkt = NULL; 896 } 897} 898 899TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 900 Tick t) 901 : pkt(_pkt), cpu(_cpu) 902{ 903 cpu->schedule(this, t); 904} 905 906void 907TimingSimpleCPU::IprEvent::process() 908{ 909 cpu->completeDataAccess(pkt); 910} 911 912const char * 913TimingSimpleCPU::IprEvent::description() const 914{ 915 return "Timing Simple CPU Delay IPR event"; 916} 917 918 919void 920TimingSimpleCPU::printAddr(Addr a) 921{ 922 dcachePort.printAddr(a); 923} 924 925 926//////////////////////////////////////////////////////////////////////// 927// 928// TimingSimpleCPU Simulation Object 929// 930TimingSimpleCPU * 931TimingSimpleCPUParams::create() 932{ 933 numThreads = 1; 934 if (!FullSystem && workload.size() != 1) 935 panic("only one workload allowed"); 936 return new TimingSimpleCPU(this); 937} 938