timing.cc revision 10379:c00f6d7e2681
1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 */ 42 43#include "arch/locked_mem.hh" 44#include "arch/mmapped_ipr.hh" 45#include "arch/utility.hh" 46#include "base/bigint.hh" 47#include "config/the_isa.hh" 48#include "cpu/simple/timing.hh" 49#include "cpu/exetrace.hh" 50#include "debug/Config.hh" 51#include "debug/Drain.hh" 52#include "debug/ExecFaulting.hh" 53#include "debug/SimpleCPU.hh" 54#include "mem/packet.hh" 55#include "mem/packet_access.hh" 56#include "params/TimingSimpleCPU.hh" 57#include "sim/faults.hh" 58#include "sim/full_system.hh" 59#include "sim/system.hh" 60 61using namespace std; 62using namespace TheISA; 63 64void 65TimingSimpleCPU::init() 66{ 67 BaseCPU::init(); 68 69 // Initialise the ThreadContext's memory proxies 70 tcBase()->initMemProxies(tcBase()); 71 72 if (FullSystem && !params()->switched_out) { 73 for (int i = 0; i < threadContexts.size(); ++i) { 74 ThreadContext *tc = threadContexts[i]; 75 // initialize CPU, including PC 76 TheISA::initCPU(tc, _cpuId); 77 } 78 } 79} 80 81void 82TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 83{ 84 pkt = _pkt; 85 cpu->schedule(this, t); 86} 87 88TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 89 : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 90 dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 91 fetchEvent(this), drainManager(NULL) 92{ 93 _status = Idle; 94 95 system->totalNumInsts = 0; 96} 97 98 99 100TimingSimpleCPU::~TimingSimpleCPU() 101{ 102} 103 104unsigned int 105TimingSimpleCPU::drain(DrainManager *drain_manager) 106{ 107 assert(!drainManager); 108 if (switchedOut()) 109 return 0; 110 111 if (_status == Idle || 112 (_status == BaseSimpleCPU::Running && isDrained())) { 113 DPRINTF(Drain, "No need to drain.\n"); 114 return 0; 115 } else { 116 drainManager = drain_manager; 117 DPRINTF(Drain, "Requesting drain: %s\n", pcState()); 118 119 // The fetch event can become descheduled if a drain didn't 120 // succeed on the first attempt. We need to reschedule it if 121 // the CPU is waiting for a microcode routine to complete. 122 if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 123 schedule(fetchEvent, clockEdge()); 124 125 return 1; 126 } 127} 128 129void 130TimingSimpleCPU::drainResume() 131{ 132 assert(!fetchEvent.scheduled()); 133 assert(!drainManager); 134 if (switchedOut()) 135 return; 136 137 DPRINTF(SimpleCPU, "Resume\n"); 138 verifyMemoryMode(); 139 140 assert(!threadContexts.empty()); 141 if (threadContexts.size() > 1) 142 fatal("The timing CPU only supports one thread.\n"); 143 144 if (thread->status() == ThreadContext::Active) { 145 schedule(fetchEvent, nextCycle()); 146 _status = BaseSimpleCPU::Running; 147 notIdleFraction = 1; 148 } else { 149 _status = BaseSimpleCPU::Idle; 150 notIdleFraction = 0; 151 } 152} 153 154bool 155TimingSimpleCPU::tryCompleteDrain() 156{ 157 if (!drainManager) 158 return false; 159 160 DPRINTF(Drain, "tryCompleteDrain: %s\n", pcState()); 161 if (!isDrained()) 162 return false; 163 164 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 165 drainManager->signalDrainDone(); 166 drainManager = NULL; 167 168 return true; 169} 170 171void 172TimingSimpleCPU::switchOut() 173{ 174 BaseSimpleCPU::switchOut(); 175 176 assert(!fetchEvent.scheduled()); 177 assert(_status == BaseSimpleCPU::Running || _status == Idle); 178 assert(!stayAtPC); 179 assert(microPC() == 0); 180 181 numCycles += curCycle() - previousCycle; 182} 183 184 185void 186TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 187{ 188 BaseSimpleCPU::takeOverFrom(oldCPU); 189 190 previousCycle = curCycle(); 191} 192 193void 194TimingSimpleCPU::verifyMemoryMode() const 195{ 196 if (!system->isTimingMode()) { 197 fatal("The timing CPU requires the memory system to be in " 198 "'timing' mode.\n"); 199 } 200} 201 202void 203TimingSimpleCPU::activateContext(ThreadID thread_num, Cycles delay) 204{ 205 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 206 207 assert(thread_num == 0); 208 assert(thread); 209 210 assert(_status == Idle); 211 212 notIdleFraction = 1; 213 _status = BaseSimpleCPU::Running; 214 215 // kick things off by initiating the fetch of the next instruction 216 schedule(fetchEvent, clockEdge(delay)); 217} 218 219 220void 221TimingSimpleCPU::suspendContext(ThreadID thread_num) 222{ 223 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 224 225 assert(thread_num == 0); 226 assert(thread); 227 228 if (_status == Idle) 229 return; 230 231 assert(_status == BaseSimpleCPU::Running); 232 233 // just change status to Idle... if status != Running, 234 // completeInst() will not initiate fetch of next instruction. 235 236 notIdleFraction = 0; 237 _status = Idle; 238} 239 240bool 241TimingSimpleCPU::handleReadPacket(PacketPtr pkt) 242{ 243 RequestPtr req = pkt->req; 244 if (req->isMmappedIpr()) { 245 Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 246 new IprEvent(pkt, this, clockEdge(delay)); 247 _status = DcacheWaitResponse; 248 dcache_pkt = NULL; 249 } else if (!dcachePort.sendTimingReq(pkt)) { 250 _status = DcacheRetry; 251 dcache_pkt = pkt; 252 } else { 253 _status = DcacheWaitResponse; 254 // memory system takes ownership of packet 255 dcache_pkt = NULL; 256 } 257 return dcache_pkt == NULL; 258} 259 260void 261TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 262 bool read) 263{ 264 PacketPtr pkt; 265 buildPacket(pkt, req, read); 266 pkt->dataDynamicArray<uint8_t>(data); 267 if (req->getFlags().isSet(Request::NO_ACCESS)) { 268 assert(!dcache_pkt); 269 pkt->makeResponse(); 270 completeDataAccess(pkt); 271 } else if (read) { 272 handleReadPacket(pkt); 273 } else { 274 bool do_access = true; // flag to suppress cache access 275 276 if (req->isLLSC()) { 277 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 278 } else if (req->isCondSwap()) { 279 assert(res); 280 req->setExtraData(*res); 281 } 282 283 if (do_access) { 284 dcache_pkt = pkt; 285 handleWritePacket(); 286 } else { 287 _status = DcacheWaitResponse; 288 completeDataAccess(pkt); 289 } 290 } 291} 292 293void 294TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 295 RequestPtr req, uint8_t *data, bool read) 296{ 297 PacketPtr pkt1, pkt2; 298 buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 299 if (req->getFlags().isSet(Request::NO_ACCESS)) { 300 assert(!dcache_pkt); 301 pkt1->makeResponse(); 302 completeDataAccess(pkt1); 303 } else if (read) { 304 SplitFragmentSenderState * send_state = 305 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 306 if (handleReadPacket(pkt1)) { 307 send_state->clearFromParent(); 308 send_state = dynamic_cast<SplitFragmentSenderState *>( 309 pkt2->senderState); 310 if (handleReadPacket(pkt2)) { 311 send_state->clearFromParent(); 312 } 313 } 314 } else { 315 dcache_pkt = pkt1; 316 SplitFragmentSenderState * send_state = 317 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 318 if (handleWritePacket()) { 319 send_state->clearFromParent(); 320 dcache_pkt = pkt2; 321 send_state = dynamic_cast<SplitFragmentSenderState *>( 322 pkt2->senderState); 323 if (handleWritePacket()) { 324 send_state->clearFromParent(); 325 } 326 } 327 } 328} 329 330void 331TimingSimpleCPU::translationFault(const Fault &fault) 332{ 333 // fault may be NoFault in cases where a fault is suppressed, 334 // for instance prefetches. 335 numCycles += curCycle() - previousCycle; 336 previousCycle = curCycle(); 337 338 if (traceData) { 339 // Since there was a fault, we shouldn't trace this instruction. 340 delete traceData; 341 traceData = NULL; 342 } 343 344 postExecute(); 345 346 advanceInst(fault); 347} 348 349void 350TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 351{ 352 pkt = read ? Packet::createRead(req) : Packet::createWrite(req); 353} 354 355void 356TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 357 RequestPtr req1, RequestPtr req2, RequestPtr req, 358 uint8_t *data, bool read) 359{ 360 pkt1 = pkt2 = NULL; 361 362 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 363 364 if (req->getFlags().isSet(Request::NO_ACCESS)) { 365 buildPacket(pkt1, req, read); 366 return; 367 } 368 369 buildPacket(pkt1, req1, read); 370 buildPacket(pkt2, req2, read); 371 372 req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId()); 373 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 374 375 pkt->dataDynamicArray<uint8_t>(data); 376 pkt1->dataStatic<uint8_t>(data); 377 pkt2->dataStatic<uint8_t>(data + req1->getSize()); 378 379 SplitMainSenderState * main_send_state = new SplitMainSenderState; 380 pkt->senderState = main_send_state; 381 main_send_state->fragments[0] = pkt1; 382 main_send_state->fragments[1] = pkt2; 383 main_send_state->outstanding = 2; 384 pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 385 pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 386} 387 388Fault 389TimingSimpleCPU::readMem(Addr addr, uint8_t *data, 390 unsigned size, unsigned flags) 391{ 392 Fault fault; 393 const int asid = 0; 394 const ThreadID tid = 0; 395 const Addr pc = thread->instAddr(); 396 unsigned block_size = cacheLineSize(); 397 BaseTLB::Mode mode = BaseTLB::Read; 398 399 if (traceData) { 400 traceData->setAddr(addr); 401 } 402 403 RequestPtr req = new Request(asid, addr, size, 404 flags, dataMasterId(), pc, _cpuId, tid); 405 406 req->taskId(taskId()); 407 408 Addr split_addr = roundDown(addr + size - 1, block_size); 409 assert(split_addr <= addr || split_addr - addr < block_size); 410 411 _status = DTBWaitResponse; 412 if (split_addr > addr) { 413 RequestPtr req1, req2; 414 assert(!req->isLLSC() && !req->isSwap()); 415 req->splitOnVaddr(split_addr, req1, req2); 416 417 WholeTranslationState *state = 418 new WholeTranslationState(req, req1, req2, new uint8_t[size], 419 NULL, mode); 420 DataTranslation<TimingSimpleCPU *> *trans1 = 421 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 422 DataTranslation<TimingSimpleCPU *> *trans2 = 423 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 424 425 thread->dtb->translateTiming(req1, tc, trans1, mode); 426 thread->dtb->translateTiming(req2, tc, trans2, mode); 427 } else { 428 WholeTranslationState *state = 429 new WholeTranslationState(req, new uint8_t[size], NULL, mode); 430 DataTranslation<TimingSimpleCPU *> *translation 431 = new DataTranslation<TimingSimpleCPU *>(this, state); 432 thread->dtb->translateTiming(req, tc, translation, mode); 433 } 434 435 return NoFault; 436} 437 438bool 439TimingSimpleCPU::handleWritePacket() 440{ 441 RequestPtr req = dcache_pkt->req; 442 if (req->isMmappedIpr()) { 443 Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 444 new IprEvent(dcache_pkt, this, clockEdge(delay)); 445 _status = DcacheWaitResponse; 446 dcache_pkt = NULL; 447 } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 448 _status = DcacheRetry; 449 } else { 450 _status = DcacheWaitResponse; 451 // memory system takes ownership of packet 452 dcache_pkt = NULL; 453 } 454 return dcache_pkt == NULL; 455} 456 457Fault 458TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 459 Addr addr, unsigned flags, uint64_t *res) 460{ 461 uint8_t *newData = new uint8_t[size]; 462 const int asid = 0; 463 const ThreadID tid = 0; 464 const Addr pc = thread->instAddr(); 465 unsigned block_size = cacheLineSize(); 466 BaseTLB::Mode mode = BaseTLB::Write; 467 468 if (data == NULL) { 469 assert(flags & Request::CACHE_BLOCK_ZERO); 470 // This must be a cache block cleaning request 471 memset(newData, 0, size); 472 } else { 473 memcpy(newData, data, size); 474 } 475 476 if (traceData) { 477 traceData->setAddr(addr); 478 } 479 480 RequestPtr req = new Request(asid, addr, size, 481 flags, dataMasterId(), pc, _cpuId, tid); 482 483 req->taskId(taskId()); 484 485 Addr split_addr = roundDown(addr + size - 1, block_size); 486 assert(split_addr <= addr || split_addr - addr < block_size); 487 488 _status = DTBWaitResponse; 489 if (split_addr > addr) { 490 RequestPtr req1, req2; 491 assert(!req->isLLSC() && !req->isSwap()); 492 req->splitOnVaddr(split_addr, req1, req2); 493 494 WholeTranslationState *state = 495 new WholeTranslationState(req, req1, req2, newData, res, mode); 496 DataTranslation<TimingSimpleCPU *> *trans1 = 497 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 498 DataTranslation<TimingSimpleCPU *> *trans2 = 499 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 500 501 thread->dtb->translateTiming(req1, tc, trans1, mode); 502 thread->dtb->translateTiming(req2, tc, trans2, mode); 503 } else { 504 WholeTranslationState *state = 505 new WholeTranslationState(req, newData, res, mode); 506 DataTranslation<TimingSimpleCPU *> *translation = 507 new DataTranslation<TimingSimpleCPU *>(this, state); 508 thread->dtb->translateTiming(req, tc, translation, mode); 509 } 510 511 // Translation faults will be returned via finishTranslation() 512 return NoFault; 513} 514 515 516void 517TimingSimpleCPU::finishTranslation(WholeTranslationState *state) 518{ 519 _status = BaseSimpleCPU::Running; 520 521 if (state->getFault() != NoFault) { 522 if (state->isPrefetch()) { 523 state->setNoFault(); 524 } 525 delete [] state->data; 526 state->deleteReqs(); 527 translationFault(state->getFault()); 528 } else { 529 if (!state->isSplit) { 530 sendData(state->mainReq, state->data, state->res, 531 state->mode == BaseTLB::Read); 532 } else { 533 sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 534 state->data, state->mode == BaseTLB::Read); 535 } 536 } 537 538 delete state; 539} 540 541 542void 543TimingSimpleCPU::fetch() 544{ 545 DPRINTF(SimpleCPU, "Fetch\n"); 546 547 if (!curStaticInst || !curStaticInst->isDelayedCommit()) 548 checkForInterrupts(); 549 550 checkPcEventQueue(); 551 552 // We must have just got suspended by a PC event 553 if (_status == Idle) 554 return; 555 556 TheISA::PCState pcState = thread->pcState(); 557 bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 558 559 if (needToFetch) { 560 _status = BaseSimpleCPU::Running; 561 Request *ifetch_req = new Request(); 562 ifetch_req->taskId(taskId()); 563 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 564 setupFetchRequest(ifetch_req); 565 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 566 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 567 BaseTLB::Execute); 568 } else { 569 _status = IcacheWaitResponse; 570 completeIfetch(NULL); 571 572 numCycles += curCycle() - previousCycle; 573 previousCycle = curCycle(); 574 } 575} 576 577 578void 579TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, 580 ThreadContext *tc) 581{ 582 if (fault == NoFault) { 583 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 584 req->getVaddr(), req->getPaddr()); 585 ifetch_pkt = new Packet(req, MemCmd::ReadReq); 586 ifetch_pkt->dataStatic(&inst); 587 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 588 589 if (!icachePort.sendTimingReq(ifetch_pkt)) { 590 // Need to wait for retry 591 _status = IcacheRetry; 592 } else { 593 // Need to wait for cache to respond 594 _status = IcacheWaitResponse; 595 // ownership of packet transferred to memory system 596 ifetch_pkt = NULL; 597 } 598 } else { 599 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 600 delete req; 601 // fetch fault: advance directly to next instruction (fault handler) 602 _status = BaseSimpleCPU::Running; 603 advanceInst(fault); 604 } 605 606 numCycles += curCycle() - previousCycle; 607 previousCycle = curCycle(); 608} 609 610 611void 612TimingSimpleCPU::advanceInst(const Fault &fault) 613{ 614 if (_status == Faulting) 615 return; 616 617 if (fault != NoFault) { 618 advancePC(fault); 619 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 620 reschedule(fetchEvent, clockEdge(), true); 621 _status = Faulting; 622 return; 623 } 624 625 626 if (!stayAtPC) 627 advancePC(fault); 628 629 if (tryCompleteDrain()) 630 return; 631 632 if (_status == BaseSimpleCPU::Running) { 633 // kick off fetch of next instruction... callback from icache 634 // response will cause that instruction to be executed, 635 // keeping the CPU running. 636 fetch(); 637 } 638} 639 640 641void 642TimingSimpleCPU::completeIfetch(PacketPtr pkt) 643{ 644 DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 645 pkt->getAddr() : 0); 646 647 // received a response from the icache: execute the received 648 // instruction 649 assert(!pkt || !pkt->isError()); 650 assert(_status == IcacheWaitResponse); 651 652 _status = BaseSimpleCPU::Running; 653 654 numCycles += curCycle() - previousCycle; 655 previousCycle = curCycle(); 656 657 if (pkt) 658 pkt->req->setAccessLatency(); 659 660 661 preExecute(); 662 if (curStaticInst && curStaticInst->isMemRef()) { 663 // load or store: just send to dcache 664 Fault fault = curStaticInst->initiateAcc(this, traceData); 665 666 // If we're not running now the instruction will complete in a dcache 667 // response callback or the instruction faulted and has started an 668 // ifetch 669 if (_status == BaseSimpleCPU::Running) { 670 if (fault != NoFault && traceData) { 671 // If there was a fault, we shouldn't trace this instruction. 672 delete traceData; 673 traceData = NULL; 674 } 675 676 postExecute(); 677 // @todo remove me after debugging with legion done 678 if (curStaticInst && (!curStaticInst->isMicroop() || 679 curStaticInst->isFirstMicroop())) 680 instCnt++; 681 advanceInst(fault); 682 } 683 } else if (curStaticInst) { 684 // non-memory instruction: execute completely now 685 Fault fault = curStaticInst->execute(this, traceData); 686 687 // keep an instruction count 688 if (fault == NoFault) 689 countInst(); 690 else if (traceData && !DTRACE(ExecFaulting)) { 691 delete traceData; 692 traceData = NULL; 693 } 694 695 postExecute(); 696 // @todo remove me after debugging with legion done 697 if (curStaticInst && (!curStaticInst->isMicroop() || 698 curStaticInst->isFirstMicroop())) 699 instCnt++; 700 advanceInst(fault); 701 } else { 702 advanceInst(NoFault); 703 } 704 705 if (pkt) { 706 delete pkt->req; 707 delete pkt; 708 } 709} 710 711void 712TimingSimpleCPU::IcachePort::ITickEvent::process() 713{ 714 cpu->completeIfetch(pkt); 715} 716 717bool 718TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 719{ 720 DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); 721 // delay processing of returned data until next CPU clock edge 722 Tick next_tick = cpu->clockEdge(); 723 724 if (next_tick == curTick()) 725 cpu->completeIfetch(pkt); 726 else 727 tickEvent.schedule(pkt, next_tick); 728 729 return true; 730} 731 732void 733TimingSimpleCPU::IcachePort::recvRetry() 734{ 735 // we shouldn't get a retry unless we have a packet that we're 736 // waiting to transmit 737 assert(cpu->ifetch_pkt != NULL); 738 assert(cpu->_status == IcacheRetry); 739 PacketPtr tmp = cpu->ifetch_pkt; 740 if (sendTimingReq(tmp)) { 741 cpu->_status = IcacheWaitResponse; 742 cpu->ifetch_pkt = NULL; 743 } 744} 745 746void 747TimingSimpleCPU::completeDataAccess(PacketPtr pkt) 748{ 749 // received a response from the dcache: complete the load or store 750 // instruction 751 assert(!pkt->isError()); 752 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 753 pkt->req->getFlags().isSet(Request::NO_ACCESS)); 754 755 pkt->req->setAccessLatency(); 756 numCycles += curCycle() - previousCycle; 757 previousCycle = curCycle(); 758 759 if (pkt->senderState) { 760 SplitFragmentSenderState * send_state = 761 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 762 assert(send_state); 763 delete pkt->req; 764 delete pkt; 765 PacketPtr big_pkt = send_state->bigPkt; 766 delete send_state; 767 768 SplitMainSenderState * main_send_state = 769 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 770 assert(main_send_state); 771 // Record the fact that this packet is no longer outstanding. 772 assert(main_send_state->outstanding != 0); 773 main_send_state->outstanding--; 774 775 if (main_send_state->outstanding) { 776 return; 777 } else { 778 delete main_send_state; 779 big_pkt->senderState = NULL; 780 pkt = big_pkt; 781 } 782 } 783 784 _status = BaseSimpleCPU::Running; 785 786 Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 787 788 // keep an instruction count 789 if (fault == NoFault) 790 countInst(); 791 else if (traceData) { 792 // If there was a fault, we shouldn't trace this instruction. 793 delete traceData; 794 traceData = NULL; 795 } 796 797 // the locked flag may be cleared on the response packet, so check 798 // pkt->req and not pkt to see if it was a load-locked 799 if (pkt->isRead() && pkt->req->isLLSC()) { 800 TheISA::handleLockedRead(thread, pkt->req); 801 } 802 803 delete pkt->req; 804 delete pkt; 805 806 postExecute(); 807 808 advanceInst(fault); 809} 810 811void 812TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 813{ 814 TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 815} 816 817 818bool 819TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 820{ 821 // delay processing of returned data until next CPU clock edge 822 Tick next_tick = cpu->clockEdge(); 823 824 if (next_tick == curTick()) { 825 cpu->completeDataAccess(pkt); 826 } else { 827 if (!tickEvent.scheduled()) { 828 tickEvent.schedule(pkt, next_tick); 829 } else { 830 // In the case of a split transaction and a cache that is 831 // faster than a CPU we could get two responses before 832 // next_tick expires 833 if (!retryEvent.scheduled()) 834 cpu->schedule(retryEvent, next_tick); 835 return false; 836 } 837 } 838 839 return true; 840} 841 842void 843TimingSimpleCPU::DcachePort::DTickEvent::process() 844{ 845 cpu->completeDataAccess(pkt); 846} 847 848void 849TimingSimpleCPU::DcachePort::recvRetry() 850{ 851 // we shouldn't get a retry unless we have a packet that we're 852 // waiting to transmit 853 assert(cpu->dcache_pkt != NULL); 854 assert(cpu->_status == DcacheRetry); 855 PacketPtr tmp = cpu->dcache_pkt; 856 if (tmp->senderState) { 857 // This is a packet from a split access. 858 SplitFragmentSenderState * send_state = 859 dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 860 assert(send_state); 861 PacketPtr big_pkt = send_state->bigPkt; 862 863 SplitMainSenderState * main_send_state = 864 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 865 assert(main_send_state); 866 867 if (sendTimingReq(tmp)) { 868 // If we were able to send without retrying, record that fact 869 // and try sending the other fragment. 870 send_state->clearFromParent(); 871 int other_index = main_send_state->getPendingFragment(); 872 if (other_index > 0) { 873 tmp = main_send_state->fragments[other_index]; 874 cpu->dcache_pkt = tmp; 875 if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 876 (big_pkt->isWrite() && cpu->handleWritePacket())) { 877 main_send_state->fragments[other_index] = NULL; 878 } 879 } else { 880 cpu->_status = DcacheWaitResponse; 881 // memory system takes ownership of packet 882 cpu->dcache_pkt = NULL; 883 } 884 } 885 } else if (sendTimingReq(tmp)) { 886 cpu->_status = DcacheWaitResponse; 887 // memory system takes ownership of packet 888 cpu->dcache_pkt = NULL; 889 } 890} 891 892TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 893 Tick t) 894 : pkt(_pkt), cpu(_cpu) 895{ 896 cpu->schedule(this, t); 897} 898 899void 900TimingSimpleCPU::IprEvent::process() 901{ 902 cpu->completeDataAccess(pkt); 903} 904 905const char * 906TimingSimpleCPU::IprEvent::description() const 907{ 908 return "Timing Simple CPU Delay IPR event"; 909} 910 911 912void 913TimingSimpleCPU::printAddr(Addr a) 914{ 915 dcachePort.printAddr(a); 916} 917 918 919//////////////////////////////////////////////////////////////////////// 920// 921// TimingSimpleCPU Simulation Object 922// 923TimingSimpleCPU * 924TimingSimpleCPUParams::create() 925{ 926 numThreads = 1; 927 if (!FullSystem && workload.size() != 1) 928 panic("only one workload allowed"); 929 return new TimingSimpleCPU(this); 930} 931