timing.cc revision 9442
12623SN/A/* 28948Sandreas.hansson@arm.com * Copyright (c) 2010-2012 ARM Limited 37725SAli.Saidi@ARM.com * All rights reserved 47725SAli.Saidi@ARM.com * 57725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137725SAli.Saidi@ARM.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 433170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 448105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 452623SN/A#include "arch/utility.hh" 464040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/simple/timing.hh" 492623SN/A#include "cpu/exetrace.hh" 508232Snate@binkert.org#include "debug/Config.hh" 519152Satgutier@umich.edu#include "debug/Drain.hh" 528232Snate@binkert.org#include "debug/ExecFaulting.hh" 538232Snate@binkert.org#include "debug/SimpleCPU.hh" 543348Sbinkertn@umich.edu#include "mem/packet.hh" 553348Sbinkertn@umich.edu#include "mem/packet_access.hh" 564762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 577678Sgblack@eecs.umich.edu#include "sim/faults.hh" 588779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 592901Ssaidi@eecs.umich.edu#include "sim/system.hh" 602623SN/A 612623SN/Ausing namespace std; 622623SN/Ausing namespace TheISA; 632623SN/A 642623SN/Avoid 652623SN/ATimingSimpleCPU::init() 662623SN/A{ 672623SN/A BaseCPU::init(); 688921Sandreas.hansson@arm.com 699433SAndreas.Sandberg@ARM.com if (!params()->switched_out && 709424SAndreas.Sandberg@ARM.com system->getMemoryMode() != Enums::timing) { 719424SAndreas.Sandberg@ARM.com fatal("The timing CPU requires the memory system to be in " 729424SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 739424SAndreas.Sandberg@ARM.com } 749424SAndreas.Sandberg@ARM.com 758921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 768921Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 778921Sandreas.hansson@arm.com 789433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 798779Sgblack@eecs.umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 808779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 818779Sgblack@eecs.umich.edu // initialize CPU, including PC 828779Sgblack@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 838779Sgblack@eecs.umich.edu } 842623SN/A } 852623SN/A} 862623SN/A 872623SN/Avoid 888707Sandreas.hansson@arm.comTimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 892948Ssaidi@eecs.umich.edu{ 902948Ssaidi@eecs.umich.edu pkt = _pkt; 915606Snate@binkert.org cpu->schedule(this, t); 922948Ssaidi@eecs.umich.edu} 932948Ssaidi@eecs.umich.edu 945529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 958707Sandreas.hansson@arm.com : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 969179Sandreas.hansson@arm.com dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 979442SAndreas.Sandberg@ARM.com fetchEvent(this), drainManager(NULL) 982623SN/A{ 992623SN/A _status = Idle; 1003647Srdreslin@umich.edu 1017897Shestness@cs.utexas.edu system->totalNumInsts = 0; 1022623SN/A} 1032623SN/A 1042623SN/A 1052623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1062623SN/A{ 1072623SN/A} 1082623SN/A 1092901Ssaidi@eecs.umich.eduunsigned int 1109342SAndreas.Sandberg@arm.comTimingSimpleCPU::drain(DrainManager *drain_manager) 1112798Sktlim@umich.edu{ 1129342SAndreas.Sandberg@arm.com if (_status == Idle || 1139442SAndreas.Sandberg@ARM.com (_status == BaseSimpleCPU::Running && isDrained()) || 1149342SAndreas.Sandberg@arm.com _status == SwitchedOut) { 1159442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1169442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "No need to drain.\n"); 1172901Ssaidi@eecs.umich.edu return 0; 1182798Sktlim@umich.edu } else { 1199342SAndreas.Sandberg@arm.com drainManager = drain_manager; 1209442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Requesting drain: %s\n", pcState()); 1219442SAndreas.Sandberg@ARM.com 1229442SAndreas.Sandberg@ARM.com // The fetch event can become descheduled if a drain didn't 1239442SAndreas.Sandberg@ARM.com // succeed on the first attempt. We need to reschedule it if 1249442SAndreas.Sandberg@ARM.com // the CPU is waiting for a microcode routine to complete. 1259442SAndreas.Sandberg@ARM.com if (_status == BaseSimpleCPU::Running && !isDrained() && 1269442SAndreas.Sandberg@ARM.com !fetchEvent.scheduled()) { 1279442SAndreas.Sandberg@ARM.com schedule(fetchEvent, nextCycle()); 1289442SAndreas.Sandberg@ARM.com } 1299442SAndreas.Sandberg@ARM.com 1302901Ssaidi@eecs.umich.edu return 1; 1312798Sktlim@umich.edu } 1322623SN/A} 1332623SN/A 1342623SN/Avoid 1359342SAndreas.Sandberg@arm.comTimingSimpleCPU::drainResume() 1362623SN/A{ 1379442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1389442SAndreas.Sandberg@ARM.com 1395221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1402798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1419424SAndreas.Sandberg@ARM.com if (system->getMemoryMode() != Enums::timing) { 1429424SAndreas.Sandberg@ARM.com fatal("The timing CPU requires the memory system to be in " 1439424SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 1449424SAndreas.Sandberg@ARM.com } 1453201Shsul@eecs.umich.edu 1465710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1472623SN/A } 1489442SAndreas.Sandberg@ARM.com} 1492798Sktlim@umich.edu 1509442SAndreas.Sandberg@ARM.combool 1519442SAndreas.Sandberg@ARM.comTimingSimpleCPU::tryCompleteDrain() 1529442SAndreas.Sandberg@ARM.com{ 1539442SAndreas.Sandberg@ARM.com if (!drainManager) 1549442SAndreas.Sandberg@ARM.com return false; 1559442SAndreas.Sandberg@ARM.com 1569442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "tryCompleteDrain: %s\n", pcState()); 1579442SAndreas.Sandberg@ARM.com if (!isDrained()) 1589442SAndreas.Sandberg@ARM.com return false; 1599442SAndreas.Sandberg@ARM.com 1609442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 1619442SAndreas.Sandberg@ARM.com drainManager->signalDrainDone(); 1629442SAndreas.Sandberg@ARM.com drainManager = NULL; 1639442SAndreas.Sandberg@ARM.com 1649442SAndreas.Sandberg@ARM.com return true; 1652798Sktlim@umich.edu} 1662798Sktlim@umich.edu 1672798Sktlim@umich.eduvoid 1682798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1692798Sktlim@umich.edu{ 1709429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1719429SAndreas.Sandberg@ARM.com 1729442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1739342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 1749442SAndreas.Sandberg@ARM.com assert(!stayAtPC); 1759442SAndreas.Sandberg@ARM.com assert(microPC() == 0); 1769442SAndreas.Sandberg@ARM.com 1772798Sktlim@umich.edu _status = SwitchedOut; 1789179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 1792623SN/A} 1802623SN/A 1812623SN/A 1822623SN/Avoid 1832623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1842623SN/A{ 1859429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 1862623SN/A 1872680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1882623SN/A // running and schedule its tick event. 1892680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1902680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1919342SAndreas.Sandberg@arm.com if (tc->status() == ThreadContext::Active && 1929342SAndreas.Sandberg@arm.com _status != BaseSimpleCPU::Running) { 1939342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 1942623SN/A break; 1952623SN/A } 1962623SN/A } 1973201Shsul@eecs.umich.edu 1989342SAndreas.Sandberg@arm.com if (_status != BaseSimpleCPU::Running) { 1993201Shsul@eecs.umich.edu _status = Idle; 2003201Shsul@eecs.umich.edu } 2015169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2029179Sandreas.hansson@arm.com previousCycle = curCycle(); 2032623SN/A} 2042623SN/A 2052623SN/A 2062623SN/Avoid 2079180Sandreas.hansson@arm.comTimingSimpleCPU::activateContext(ThreadID thread_num, Cycles delay) 2082623SN/A{ 2095221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2105221Ssaidi@eecs.umich.edu 2112623SN/A assert(thread_num == 0); 2122683Sktlim@umich.edu assert(thread); 2132623SN/A 2142623SN/A assert(_status == Idle); 2152623SN/A 2162623SN/A notIdleFraction++; 2179342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 2183686Sktlim@umich.edu 2192623SN/A // kick things off by initiating the fetch of the next instruction 2209179Sandreas.hansson@arm.com schedule(fetchEvent, clockEdge(delay)); 2212623SN/A} 2222623SN/A 2232623SN/A 2242623SN/Avoid 2258737Skoansin.tan@gmail.comTimingSimpleCPU::suspendContext(ThreadID thread_num) 2262623SN/A{ 2275221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2285221Ssaidi@eecs.umich.edu 2292623SN/A assert(thread_num == 0); 2302683Sktlim@umich.edu assert(thread); 2312623SN/A 2326043Sgblack@eecs.umich.edu if (_status == Idle) 2336043Sgblack@eecs.umich.edu return; 2346043Sgblack@eecs.umich.edu 2359342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2362623SN/A 2372644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2382644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2392623SN/A 2402623SN/A notIdleFraction--; 2412623SN/A _status = Idle; 2422623SN/A} 2432623SN/A 2445728Sgblack@eecs.umich.edubool 2455728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2465728Sgblack@eecs.umich.edu{ 2475728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 2488105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2499180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 2509179Sandreas.hansson@arm.com new IprEvent(pkt, this, clockEdge(delay)); 2515728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2525728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2538975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(pkt)) { 2545728Sgblack@eecs.umich.edu _status = DcacheRetry; 2555728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2565728Sgblack@eecs.umich.edu } else { 2575728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2585728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2595728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2605728Sgblack@eecs.umich.edu } 2615728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2625728Sgblack@eecs.umich.edu} 2632623SN/A 2645894Sgblack@eecs.umich.eduvoid 2656973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2666973Stjones1@inf.ed.ac.uk bool read) 2675744Sgblack@eecs.umich.edu{ 2685894Sgblack@eecs.umich.edu PacketPtr pkt; 2695894Sgblack@eecs.umich.edu buildPacket(pkt, req, read); 2707691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 2715894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2725894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2735894Sgblack@eecs.umich.edu pkt->makeResponse(); 2745894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2755894Sgblack@eecs.umich.edu } else if (read) { 2765894Sgblack@eecs.umich.edu handleReadPacket(pkt); 2775894Sgblack@eecs.umich.edu } else { 2785894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 2795894Sgblack@eecs.umich.edu 2806102Sgblack@eecs.umich.edu if (req->isLLSC()) { 2815894Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 2825894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 2835894Sgblack@eecs.umich.edu assert(res); 2845894Sgblack@eecs.umich.edu req->setExtraData(*res); 2855894Sgblack@eecs.umich.edu } 2865894Sgblack@eecs.umich.edu 2875894Sgblack@eecs.umich.edu if (do_access) { 2885894Sgblack@eecs.umich.edu dcache_pkt = pkt; 2895894Sgblack@eecs.umich.edu handleWritePacket(); 2905894Sgblack@eecs.umich.edu } else { 2915894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2925894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2935894Sgblack@eecs.umich.edu } 2945894Sgblack@eecs.umich.edu } 2955894Sgblack@eecs.umich.edu} 2965894Sgblack@eecs.umich.edu 2975894Sgblack@eecs.umich.eduvoid 2986973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 2996973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 3005894Sgblack@eecs.umich.edu{ 3015894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3025894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3035894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3045894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3055894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3065894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3075894Sgblack@eecs.umich.edu } else if (read) { 3087911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3097911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3105894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3115894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3127911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3137911Shestness@cs.utexas.edu pkt2->senderState); 3145894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3155894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3165894Sgblack@eecs.umich.edu } 3175894Sgblack@eecs.umich.edu } 3185894Sgblack@eecs.umich.edu } else { 3195894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3207911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3217911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3225894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3235894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3245894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3257911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3267911Shestness@cs.utexas.edu pkt2->senderState); 3275894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3285894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3295894Sgblack@eecs.umich.edu } 3305894Sgblack@eecs.umich.edu } 3315894Sgblack@eecs.umich.edu } 3325894Sgblack@eecs.umich.edu} 3335894Sgblack@eecs.umich.edu 3345894Sgblack@eecs.umich.eduvoid 3355894Sgblack@eecs.umich.eduTimingSimpleCPU::translationFault(Fault fault) 3365894Sgblack@eecs.umich.edu{ 3376739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3386739Sgblack@eecs.umich.edu // for instance prefetches. 3399179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 3409179Sandreas.hansson@arm.com previousCycle = curCycle(); 3415894Sgblack@eecs.umich.edu 3425894Sgblack@eecs.umich.edu if (traceData) { 3435894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3445894Sgblack@eecs.umich.edu delete traceData; 3455894Sgblack@eecs.umich.edu traceData = NULL; 3465744Sgblack@eecs.umich.edu } 3475744Sgblack@eecs.umich.edu 3485894Sgblack@eecs.umich.edu postExecute(); 3495894Sgblack@eecs.umich.edu 3509442SAndreas.Sandberg@ARM.com advanceInst(fault); 3515894Sgblack@eecs.umich.edu} 3525894Sgblack@eecs.umich.edu 3535894Sgblack@eecs.umich.eduvoid 3545894Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 3555894Sgblack@eecs.umich.edu{ 3565894Sgblack@eecs.umich.edu MemCmd cmd; 3575894Sgblack@eecs.umich.edu if (read) { 3585894Sgblack@eecs.umich.edu cmd = MemCmd::ReadReq; 3596102Sgblack@eecs.umich.edu if (req->isLLSC()) 3605894Sgblack@eecs.umich.edu cmd = MemCmd::LoadLockedReq; 3615894Sgblack@eecs.umich.edu } else { 3625894Sgblack@eecs.umich.edu cmd = MemCmd::WriteReq; 3636102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3645894Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3655894Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3665894Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3675894Sgblack@eecs.umich.edu } 3685894Sgblack@eecs.umich.edu } 3698949Sandreas.hansson@arm.com pkt = new Packet(req, cmd); 3705894Sgblack@eecs.umich.edu} 3715894Sgblack@eecs.umich.edu 3725894Sgblack@eecs.umich.eduvoid 3735894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3745894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 3755894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3765894Sgblack@eecs.umich.edu{ 3775894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3785894Sgblack@eecs.umich.edu 3798105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 3805744Sgblack@eecs.umich.edu 3815894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3825894Sgblack@eecs.umich.edu buildPacket(pkt1, req, read); 3835894Sgblack@eecs.umich.edu return; 3845894Sgblack@eecs.umich.edu } 3855894Sgblack@eecs.umich.edu 3865894Sgblack@eecs.umich.edu buildPacket(pkt1, req1, read); 3875894Sgblack@eecs.umich.edu buildPacket(pkt2, req2, read); 3885894Sgblack@eecs.umich.edu 3898832SAli.Saidi@ARM.com req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId()); 3908949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 3915744Sgblack@eecs.umich.edu 3927691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 3935744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 3945744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 3955744Sgblack@eecs.umich.edu 3965744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 3975744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 3985744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 3995744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 4005744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 4015744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 4025744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 4035744Sgblack@eecs.umich.edu} 4045744Sgblack@eecs.umich.edu 4052623SN/AFault 4068444Sgblack@eecs.umich.eduTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 4078444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 4082623SN/A{ 4095728Sgblack@eecs.umich.edu Fault fault; 4105728Sgblack@eecs.umich.edu const int asid = 0; 4116221Snate@binkert.org const ThreadID tid = 0; 4127720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4136227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 4146973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4152623SN/A 4167045Ssteve.reinhardt@amd.com if (traceData) { 4177045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4187045Ssteve.reinhardt@amd.com } 4197045Ssteve.reinhardt@amd.com 4207520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4218832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4225728Sgblack@eecs.umich.edu 4237520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4245744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4255728Sgblack@eecs.umich.edu 4265894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4275744Sgblack@eecs.umich.edu if (split_addr > addr) { 4285894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4296102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4305894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4315894Sgblack@eecs.umich.edu 4326973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4337520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4346973Stjones1@inf.ed.ac.uk NULL, mode); 4358486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4368486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4378486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4388486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4396973Stjones1@inf.ed.ac.uk 4406973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 4416973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 4425744Sgblack@eecs.umich.edu } else { 4436973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4447520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4458486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4468486Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 4476973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 4482623SN/A } 4492623SN/A 4505728Sgblack@eecs.umich.edu return NoFault; 4512623SN/A} 4522623SN/A 4535728Sgblack@eecs.umich.edubool 4545728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4555728Sgblack@eecs.umich.edu{ 4565728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4578105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4589180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4599179Sandreas.hansson@arm.com new IprEvent(dcache_pkt, this, clockEdge(delay)); 4605728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4615728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4628975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 4635728Sgblack@eecs.umich.edu _status = DcacheRetry; 4645728Sgblack@eecs.umich.edu } else { 4655728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4665728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4675728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4685728Sgblack@eecs.umich.edu } 4695728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4705728Sgblack@eecs.umich.edu} 4712623SN/A 4722623SN/AFault 4738444Sgblack@eecs.umich.eduTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 4748444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 4752623SN/A{ 4768443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 4778443Sgblack@eecs.umich.edu memcpy(newData, data, size); 4788443Sgblack@eecs.umich.edu 4795728Sgblack@eecs.umich.edu const int asid = 0; 4806221Snate@binkert.org const ThreadID tid = 0; 4817720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4826227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 4836973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 4843169Sstever@eecs.umich.edu 4857045Ssteve.reinhardt@amd.com if (traceData) { 4867045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4877045Ssteve.reinhardt@amd.com } 4887045Ssteve.reinhardt@amd.com 4897520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4908832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4915728Sgblack@eecs.umich.edu 4927520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4935744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4945728Sgblack@eecs.umich.edu 4955894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4965744Sgblack@eecs.umich.edu if (split_addr > addr) { 4975894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4986102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4995894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5005894Sgblack@eecs.umich.edu 5016973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5028443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 5038486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 5048486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 5058486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 5068486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 5076973Stjones1@inf.ed.ac.uk 5086973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 5096973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 5105744Sgblack@eecs.umich.edu } else { 5116973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5128443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5138486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation = 5148486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state); 5156973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 5162623SN/A } 5172623SN/A 5187045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5195728Sgblack@eecs.umich.edu return NoFault; 5202623SN/A} 5212623SN/A 5222623SN/A 5232623SN/Avoid 5246973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5256973Stjones1@inf.ed.ac.uk{ 5269342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5276973Stjones1@inf.ed.ac.uk 5286973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 5296973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 5306973Stjones1@inf.ed.ac.uk state->setNoFault(); 5316973Stjones1@inf.ed.ac.uk } 5327691SAli.Saidi@ARM.com delete [] state->data; 5336973Stjones1@inf.ed.ac.uk state->deleteReqs(); 5346973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 5356973Stjones1@inf.ed.ac.uk } else { 5366973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 5376973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 5386973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 5396973Stjones1@inf.ed.ac.uk } else { 5406973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5416973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 5426973Stjones1@inf.ed.ac.uk } 5436973Stjones1@inf.ed.ac.uk } 5446973Stjones1@inf.ed.ac.uk 5456973Stjones1@inf.ed.ac.uk delete state; 5466973Stjones1@inf.ed.ac.uk} 5476973Stjones1@inf.ed.ac.uk 5486973Stjones1@inf.ed.ac.uk 5496973Stjones1@inf.ed.ac.ukvoid 5502623SN/ATimingSimpleCPU::fetch() 5512623SN/A{ 5525221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5535221Ssaidi@eecs.umich.edu 5543387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5553387Sgblack@eecs.umich.edu checkForInterrupts(); 5562631SN/A 5575348Ssaidi@eecs.umich.edu checkPcEventQueue(); 5585348Ssaidi@eecs.umich.edu 5598143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5608143SAli.Saidi@ARM.com if (_status == Idle) 5618143SAli.Saidi@ARM.com return; 5628143SAli.Saidi@ARM.com 5637720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5647720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 5652623SN/A 5667720Sgblack@eecs.umich.edu if (needToFetch) { 5679342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5685669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 5695712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 5705894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 5718277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 5726023Snate@binkert.org thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 5736023Snate@binkert.org BaseTLB::Execute); 5742623SN/A } else { 5755669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5765669Sgblack@eecs.umich.edu completeIfetch(NULL); 5775894Sgblack@eecs.umich.edu 5789179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 5799179Sandreas.hansson@arm.com previousCycle = curCycle(); 5805894Sgblack@eecs.umich.edu } 5815894Sgblack@eecs.umich.edu} 5825894Sgblack@eecs.umich.edu 5835894Sgblack@eecs.umich.edu 5845894Sgblack@eecs.umich.eduvoid 5855894Sgblack@eecs.umich.eduTimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc) 5865894Sgblack@eecs.umich.edu{ 5875894Sgblack@eecs.umich.edu if (fault == NoFault) { 5888277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 5898277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 5908949Sandreas.hansson@arm.com ifetch_pkt = new Packet(req, MemCmd::ReadReq); 5915894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 5928277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 5935894Sgblack@eecs.umich.edu 5948975Sandreas.hansson@arm.com if (!icachePort.sendTimingReq(ifetch_pkt)) { 5955894Sgblack@eecs.umich.edu // Need to wait for retry 5965894Sgblack@eecs.umich.edu _status = IcacheRetry; 5975894Sgblack@eecs.umich.edu } else { 5985894Sgblack@eecs.umich.edu // Need to wait for cache to respond 5995894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6005894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 6015894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 6025894Sgblack@eecs.umich.edu } 6035894Sgblack@eecs.umich.edu } else { 6048277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 6055894Sgblack@eecs.umich.edu delete req; 6065894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 6079342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6085894Sgblack@eecs.umich.edu advanceInst(fault); 6092623SN/A } 6103222Sktlim@umich.edu 6119179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 6129179Sandreas.hansson@arm.com previousCycle = curCycle(); 6132623SN/A} 6142623SN/A 6152623SN/A 6162623SN/Avoid 6172644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 6182623SN/A{ 6198276SAli.Saidi@ARM.com if (_status == Faulting) 6208276SAli.Saidi@ARM.com return; 6218276SAli.Saidi@ARM.com 6228276SAli.Saidi@ARM.com if (fault != NoFault) { 6238276SAli.Saidi@ARM.com advancePC(fault); 6248276SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 6258276SAli.Saidi@ARM.com reschedule(fetchEvent, nextCycle(), true); 6268276SAli.Saidi@ARM.com _status = Faulting; 6278276SAli.Saidi@ARM.com return; 6288276SAli.Saidi@ARM.com } 6298276SAli.Saidi@ARM.com 6308276SAli.Saidi@ARM.com 6318276SAli.Saidi@ARM.com if (!stayAtPC) 6325726Sgblack@eecs.umich.edu advancePC(fault); 6332623SN/A 6349442SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6359442SAndreas.Sandberg@ARM.com return; 6369442SAndreas.Sandberg@ARM.com 6379342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6382631SN/A // kick off fetch of next instruction... callback from icache 6392631SN/A // response will cause that instruction to be executed, 6402631SN/A // keeping the CPU running. 6412631SN/A fetch(); 6422631SN/A } 6432623SN/A} 6442623SN/A 6452623SN/A 6462623SN/Avoid 6473349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 6482623SN/A{ 6498277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 6508277SAli.Saidi@ARM.com pkt->getAddr() : 0); 6518277SAli.Saidi@ARM.com 6522623SN/A // received a response from the icache: execute the received 6532623SN/A // instruction 6545669Sgblack@eecs.umich.edu 6555669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 6562623SN/A assert(_status == IcacheWaitResponse); 6572798Sktlim@umich.edu 6589342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6592644Sstever@eecs.umich.edu 6609179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 6619179Sandreas.hansson@arm.com previousCycle = curCycle(); 6623222Sktlim@umich.edu 6632623SN/A preExecute(); 6647725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 6652623SN/A // load or store: just send to dcache 6662623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 6677945SAli.Saidi@ARM.com 6687945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 6697945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 6707945SAli.Saidi@ARM.com // ifetch 6719342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6725894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 6735001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6745001Sgblack@eecs.umich.edu delete traceData; 6755001Sgblack@eecs.umich.edu traceData = NULL; 6763170Sstever@eecs.umich.edu } 6774998Sgblack@eecs.umich.edu 6782644Sstever@eecs.umich.edu postExecute(); 6795103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6805103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6815103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6825103Ssaidi@eecs.umich.edu instCnt++; 6832644Sstever@eecs.umich.edu advanceInst(fault); 6842644Sstever@eecs.umich.edu } 6855726Sgblack@eecs.umich.edu } else if (curStaticInst) { 6862623SN/A // non-memory instruction: execute completely now 6872623SN/A Fault fault = curStaticInst->execute(this, traceData); 6884998Sgblack@eecs.umich.edu 6894998Sgblack@eecs.umich.edu // keep an instruction count 6904998Sgblack@eecs.umich.edu if (fault == NoFault) 6914998Sgblack@eecs.umich.edu countInst(); 6927655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 6935001Sgblack@eecs.umich.edu delete traceData; 6945001Sgblack@eecs.umich.edu traceData = NULL; 6955001Sgblack@eecs.umich.edu } 6964998Sgblack@eecs.umich.edu 6972644Sstever@eecs.umich.edu postExecute(); 6985103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6995103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7005103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7015103Ssaidi@eecs.umich.edu instCnt++; 7022644Sstever@eecs.umich.edu advanceInst(fault); 7035726Sgblack@eecs.umich.edu } else { 7045726Sgblack@eecs.umich.edu advanceInst(NoFault); 7052623SN/A } 7063658Sktlim@umich.edu 7075669Sgblack@eecs.umich.edu if (pkt) { 7085669Sgblack@eecs.umich.edu delete pkt->req; 7095669Sgblack@eecs.umich.edu delete pkt; 7105669Sgblack@eecs.umich.edu } 7112623SN/A} 7122623SN/A 7132948Ssaidi@eecs.umich.eduvoid 7142948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7152948Ssaidi@eecs.umich.edu{ 7162948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7172948Ssaidi@eecs.umich.edu} 7182623SN/A 7192623SN/Abool 7208975Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 7212623SN/A{ 7229165Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); 7239165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 7249165Sandreas.hansson@arm.com Tick next_tick = cpu->nextCycle(); 7252948Ssaidi@eecs.umich.edu 7269165Sandreas.hansson@arm.com if (next_tick == curTick()) 7279165Sandreas.hansson@arm.com cpu->completeIfetch(pkt); 7289165Sandreas.hansson@arm.com else 7299165Sandreas.hansson@arm.com tickEvent.schedule(pkt, next_tick); 7308948Sandreas.hansson@arm.com 7314433Ssaidi@eecs.umich.edu return true; 7322623SN/A} 7332623SN/A 7342657Ssaidi@eecs.umich.eduvoid 7352623SN/ATimingSimpleCPU::IcachePort::recvRetry() 7362623SN/A{ 7372623SN/A // we shouldn't get a retry unless we have a packet that we're 7382623SN/A // waiting to transmit 7392623SN/A assert(cpu->ifetch_pkt != NULL); 7402623SN/A assert(cpu->_status == IcacheRetry); 7413349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7428975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 7432657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7442657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7452657Ssaidi@eecs.umich.edu } 7462623SN/A} 7472623SN/A 7482623SN/Avoid 7493349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 7502623SN/A{ 7512623SN/A // received a response from the dcache: complete the load or store 7522623SN/A // instruction 7534870Sstever@eecs.umich.edu assert(!pkt->isError()); 7547516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 7557516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 7562623SN/A 7579179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 7589179Sandreas.hansson@arm.com previousCycle = curCycle(); 7593184Srdreslin@umich.edu 7605728Sgblack@eecs.umich.edu if (pkt->senderState) { 7615728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 7625728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 7635728Sgblack@eecs.umich.edu assert(send_state); 7645728Sgblack@eecs.umich.edu delete pkt->req; 7655728Sgblack@eecs.umich.edu delete pkt; 7665728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 7675728Sgblack@eecs.umich.edu delete send_state; 7685728Sgblack@eecs.umich.edu 7695728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 7705728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 7715728Sgblack@eecs.umich.edu assert(main_send_state); 7725728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 7735728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 7745728Sgblack@eecs.umich.edu main_send_state->outstanding--; 7755728Sgblack@eecs.umich.edu 7765728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 7775728Sgblack@eecs.umich.edu return; 7785728Sgblack@eecs.umich.edu } else { 7795728Sgblack@eecs.umich.edu delete main_send_state; 7805728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 7815728Sgblack@eecs.umich.edu pkt = big_pkt; 7825728Sgblack@eecs.umich.edu } 7835728Sgblack@eecs.umich.edu } 7845728Sgblack@eecs.umich.edu 7859342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 7865728Sgblack@eecs.umich.edu 7872623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 7882623SN/A 7894998Sgblack@eecs.umich.edu // keep an instruction count 7904998Sgblack@eecs.umich.edu if (fault == NoFault) 7914998Sgblack@eecs.umich.edu countInst(); 7925001Sgblack@eecs.umich.edu else if (traceData) { 7935001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7945001Sgblack@eecs.umich.edu delete traceData; 7955001Sgblack@eecs.umich.edu traceData = NULL; 7965001Sgblack@eecs.umich.edu } 7974998Sgblack@eecs.umich.edu 7985507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 7995507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 8006102Sgblack@eecs.umich.edu if (pkt->isRead() && pkt->req->isLLSC()) { 8013170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 8023170Sstever@eecs.umich.edu } 8033170Sstever@eecs.umich.edu 8042644Sstever@eecs.umich.edu delete pkt->req; 8052644Sstever@eecs.umich.edu delete pkt; 8062644Sstever@eecs.umich.edu 8073184Srdreslin@umich.edu postExecute(); 8083227Sktlim@umich.edu 8092644Sstever@eecs.umich.edu advanceInst(fault); 8102623SN/A} 8112623SN/A 8122623SN/Abool 8138975Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 8142623SN/A{ 8159165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 8169165Sandreas.hansson@arm.com Tick next_tick = cpu->nextCycle(); 8172948Ssaidi@eecs.umich.edu 8189165Sandreas.hansson@arm.com if (next_tick == curTick()) { 8199165Sandreas.hansson@arm.com cpu->completeDataAccess(pkt); 8209165Sandreas.hansson@arm.com } else { 8219165Sandreas.hansson@arm.com if (!tickEvent.scheduled()) { 8229165Sandreas.hansson@arm.com tickEvent.schedule(pkt, next_tick); 8235728Sgblack@eecs.umich.edu } else { 8249165Sandreas.hansson@arm.com // In the case of a split transaction and a cache that is 8259165Sandreas.hansson@arm.com // faster than a CPU we could get two responses before 8269165Sandreas.hansson@arm.com // next_tick expires 8279165Sandreas.hansson@arm.com if (!retryEvent.scheduled()) 8289165Sandreas.hansson@arm.com cpu->schedule(retryEvent, next_tick); 8299165Sandreas.hansson@arm.com return false; 8304433Ssaidi@eecs.umich.edu } 8313310Srdreslin@umich.edu } 8328948Sandreas.hansson@arm.com 8334433Ssaidi@eecs.umich.edu return true; 8342948Ssaidi@eecs.umich.edu} 8352948Ssaidi@eecs.umich.edu 8362948Ssaidi@eecs.umich.eduvoid 8372948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 8382948Ssaidi@eecs.umich.edu{ 8392630SN/A cpu->completeDataAccess(pkt); 8402623SN/A} 8412623SN/A 8422657Ssaidi@eecs.umich.eduvoid 8432623SN/ATimingSimpleCPU::DcachePort::recvRetry() 8442623SN/A{ 8452623SN/A // we shouldn't get a retry unless we have a packet that we're 8462623SN/A // waiting to transmit 8472623SN/A assert(cpu->dcache_pkt != NULL); 8482623SN/A assert(cpu->_status == DcacheRetry); 8493349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 8505728Sgblack@eecs.umich.edu if (tmp->senderState) { 8515728Sgblack@eecs.umich.edu // This is a packet from a split access. 8525728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8535728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 8545728Sgblack@eecs.umich.edu assert(send_state); 8555728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8565728Sgblack@eecs.umich.edu 8575728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8585728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8595728Sgblack@eecs.umich.edu assert(main_send_state); 8605728Sgblack@eecs.umich.edu 8618975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 8625728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 8635728Sgblack@eecs.umich.edu // and try sending the other fragment. 8645728Sgblack@eecs.umich.edu send_state->clearFromParent(); 8655728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 8665728Sgblack@eecs.umich.edu if (other_index > 0) { 8675728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 8685728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 8695728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 8705728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 8715728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 8725728Sgblack@eecs.umich.edu } 8735728Sgblack@eecs.umich.edu } else { 8745728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 8755728Sgblack@eecs.umich.edu // memory system takes ownership of packet 8765728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 8775728Sgblack@eecs.umich.edu } 8785728Sgblack@eecs.umich.edu } 8798975Sandreas.hansson@arm.com } else if (sendTimingReq(tmp)) { 8802657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 8813170Sstever@eecs.umich.edu // memory system takes ownership of packet 8822657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 8832657Ssaidi@eecs.umich.edu } 8842623SN/A} 8852623SN/A 8865606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 8875606Snate@binkert.org Tick t) 8885606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 8895103Ssaidi@eecs.umich.edu{ 8905606Snate@binkert.org cpu->schedule(this, t); 8915103Ssaidi@eecs.umich.edu} 8925103Ssaidi@eecs.umich.edu 8935103Ssaidi@eecs.umich.eduvoid 8945103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 8955103Ssaidi@eecs.umich.edu{ 8965103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 8975103Ssaidi@eecs.umich.edu} 8985103Ssaidi@eecs.umich.edu 8995103Ssaidi@eecs.umich.educonst char * 9005336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 9015103Ssaidi@eecs.umich.edu{ 9025103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 9035103Ssaidi@eecs.umich.edu} 9045103Ssaidi@eecs.umich.edu 9052623SN/A 9065315Sstever@gmail.comvoid 9075315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 9085315Sstever@gmail.com{ 9095315Sstever@gmail.com dcachePort.printAddr(a); 9105315Sstever@gmail.com} 9115315Sstever@gmail.com 9125315Sstever@gmail.com 9132623SN/A//////////////////////////////////////////////////////////////////////// 9142623SN/A// 9152623SN/A// TimingSimpleCPU Simulation Object 9162623SN/A// 9174762Snate@binkert.orgTimingSimpleCPU * 9184762Snate@binkert.orgTimingSimpleCPUParams::create() 9192623SN/A{ 9205529Snate@binkert.org numThreads = 1; 9218779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 9224762Snate@binkert.org panic("only one workload allowed"); 9235529Snate@binkert.org return new TimingSimpleCPU(this); 9242623SN/A} 925