timing.cc revision 9429
12623SN/A/* 28948Sandreas.hansson@arm.com * Copyright (c) 2010-2012 ARM Limited 37725SAli.Saidi@ARM.com * All rights reserved 47725SAli.Saidi@ARM.com * 57725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137725SAli.Saidi@ARM.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 433170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 448105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 452623SN/A#include "arch/utility.hh" 464040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/simple/timing.hh" 492623SN/A#include "cpu/exetrace.hh" 508232Snate@binkert.org#include "debug/Config.hh" 519152Satgutier@umich.edu#include "debug/Drain.hh" 528232Snate@binkert.org#include "debug/ExecFaulting.hh" 538232Snate@binkert.org#include "debug/SimpleCPU.hh" 543348Sbinkertn@umich.edu#include "mem/packet.hh" 553348Sbinkertn@umich.edu#include "mem/packet_access.hh" 564762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 577678Sgblack@eecs.umich.edu#include "sim/faults.hh" 588779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 592901Ssaidi@eecs.umich.edu#include "sim/system.hh" 602623SN/A 612623SN/Ausing namespace std; 622623SN/Ausing namespace TheISA; 632623SN/A 642623SN/Avoid 652623SN/ATimingSimpleCPU::init() 662623SN/A{ 672623SN/A BaseCPU::init(); 688921Sandreas.hansson@arm.com 699424SAndreas.Sandberg@ARM.com if (!params()->defer_registration && 709424SAndreas.Sandberg@ARM.com system->getMemoryMode() != Enums::timing) { 719424SAndreas.Sandberg@ARM.com fatal("The timing CPU requires the memory system to be in " 729424SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 739424SAndreas.Sandberg@ARM.com } 749424SAndreas.Sandberg@ARM.com 758921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 768921Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 778921Sandreas.hansson@arm.com 789058Satgutier@umich.edu if (FullSystem && !params()->defer_registration) { 798779Sgblack@eecs.umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 808779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 818779Sgblack@eecs.umich.edu // initialize CPU, including PC 828779Sgblack@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 838779Sgblack@eecs.umich.edu } 842623SN/A } 852623SN/A} 862623SN/A 872623SN/Avoid 888707Sandreas.hansson@arm.comTimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 892948Ssaidi@eecs.umich.edu{ 902948Ssaidi@eecs.umich.edu pkt = _pkt; 915606Snate@binkert.org cpu->schedule(this, t); 922948Ssaidi@eecs.umich.edu} 932948Ssaidi@eecs.umich.edu 945529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 958707Sandreas.hansson@arm.com : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 969179Sandreas.hansson@arm.com dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 979179Sandreas.hansson@arm.com fetchEvent(this) 982623SN/A{ 992623SN/A _status = Idle; 1003647Srdreslin@umich.edu 1019342SAndreas.Sandberg@arm.com setDrainState(Drainable::Running); 1027897Shestness@cs.utexas.edu system->totalNumInsts = 0; 1032623SN/A} 1042623SN/A 1052623SN/A 1062623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1072623SN/A{ 1082623SN/A} 1092623SN/A 1102623SN/Avoid 1112623SN/ATimingSimpleCPU::serialize(ostream &os) 1122623SN/A{ 1139342SAndreas.Sandberg@arm.com Drainable::State so_state(getDrainState()); 1142915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1152623SN/A BaseSimpleCPU::serialize(os); 1162623SN/A} 1172623SN/A 1182623SN/Avoid 1192623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1202623SN/A{ 1219342SAndreas.Sandberg@arm.com Drainable::State so_state; 1222915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1232623SN/A BaseSimpleCPU::unserialize(cp, section); 1242798Sktlim@umich.edu} 1252798Sktlim@umich.edu 1262901Ssaidi@eecs.umich.eduunsigned int 1279342SAndreas.Sandberg@arm.comTimingSimpleCPU::drain(DrainManager *drain_manager) 1282798Sktlim@umich.edu{ 1292839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1302798Sktlim@umich.edu // an access to complete. 1319342SAndreas.Sandberg@arm.com if (_status == Idle || 1329342SAndreas.Sandberg@arm.com _status == BaseSimpleCPU::Running || 1339342SAndreas.Sandberg@arm.com _status == SwitchedOut) { 1349342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 1352901Ssaidi@eecs.umich.edu return 0; 1362798Sktlim@umich.edu } else { 1379342SAndreas.Sandberg@arm.com setDrainState(Drainable::Draining); 1389342SAndreas.Sandberg@arm.com drainManager = drain_manager; 1399152Satgutier@umich.edu DPRINTF(Drain, "CPU not drained\n"); 1402901Ssaidi@eecs.umich.edu return 1; 1412798Sktlim@umich.edu } 1422623SN/A} 1432623SN/A 1442623SN/Avoid 1459342SAndreas.Sandberg@arm.comTimingSimpleCPU::drainResume() 1462623SN/A{ 1475221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1482798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1499424SAndreas.Sandberg@ARM.com if (system->getMemoryMode() != Enums::timing) { 1509424SAndreas.Sandberg@ARM.com fatal("The timing CPU requires the memory system to be in " 1519424SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 1529424SAndreas.Sandberg@ARM.com } 1533201Shsul@eecs.umich.edu 1545710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1555710Scws3k@cs.virginia.edu deschedule(fetchEvent); 1562915Sktlim@umich.edu 1575710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1582623SN/A } 1592798Sktlim@umich.edu 1609342SAndreas.Sandberg@arm.com setDrainState(Drainable::Running); 1612798Sktlim@umich.edu} 1622798Sktlim@umich.edu 1632798Sktlim@umich.eduvoid 1642798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1652798Sktlim@umich.edu{ 1669429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1679429SAndreas.Sandberg@ARM.com 1689342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 1692798Sktlim@umich.edu _status = SwitchedOut; 1709179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 1712867Sktlim@umich.edu 1722867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1732867Sktlim@umich.edu // we'll need to cancel it. 1745710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1755606Snate@binkert.org deschedule(fetchEvent); 1762623SN/A} 1772623SN/A 1782623SN/A 1792623SN/Avoid 1802623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1812623SN/A{ 1829429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 1832623SN/A 1842680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1852623SN/A // running and schedule its tick event. 1862680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1872680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1889342SAndreas.Sandberg@arm.com if (tc->status() == ThreadContext::Active && 1899342SAndreas.Sandberg@arm.com _status != BaseSimpleCPU::Running) { 1909342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 1912623SN/A break; 1922623SN/A } 1932623SN/A } 1943201Shsul@eecs.umich.edu 1959342SAndreas.Sandberg@arm.com if (_status != BaseSimpleCPU::Running) { 1963201Shsul@eecs.umich.edu _status = Idle; 1973201Shsul@eecs.umich.edu } 1985169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 1999179Sandreas.hansson@arm.com previousCycle = curCycle(); 2002623SN/A} 2012623SN/A 2022623SN/A 2032623SN/Avoid 2049180Sandreas.hansson@arm.comTimingSimpleCPU::activateContext(ThreadID thread_num, Cycles delay) 2052623SN/A{ 2065221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2075221Ssaidi@eecs.umich.edu 2082623SN/A assert(thread_num == 0); 2092683Sktlim@umich.edu assert(thread); 2102623SN/A 2112623SN/A assert(_status == Idle); 2122623SN/A 2132623SN/A notIdleFraction++; 2149342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 2153686Sktlim@umich.edu 2162623SN/A // kick things off by initiating the fetch of the next instruction 2179179Sandreas.hansson@arm.com schedule(fetchEvent, clockEdge(delay)); 2182623SN/A} 2192623SN/A 2202623SN/A 2212623SN/Avoid 2228737Skoansin.tan@gmail.comTimingSimpleCPU::suspendContext(ThreadID thread_num) 2232623SN/A{ 2245221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2255221Ssaidi@eecs.umich.edu 2262623SN/A assert(thread_num == 0); 2272683Sktlim@umich.edu assert(thread); 2282623SN/A 2296043Sgblack@eecs.umich.edu if (_status == Idle) 2306043Sgblack@eecs.umich.edu return; 2316043Sgblack@eecs.umich.edu 2329342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2332623SN/A 2342644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2352644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2362623SN/A 2372623SN/A notIdleFraction--; 2382623SN/A _status = Idle; 2392623SN/A} 2402623SN/A 2415728Sgblack@eecs.umich.edubool 2425728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2435728Sgblack@eecs.umich.edu{ 2445728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 2458105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2469180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 2479179Sandreas.hansson@arm.com new IprEvent(pkt, this, clockEdge(delay)); 2485728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2495728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2508975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(pkt)) { 2515728Sgblack@eecs.umich.edu _status = DcacheRetry; 2525728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2535728Sgblack@eecs.umich.edu } else { 2545728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2555728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2565728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2575728Sgblack@eecs.umich.edu } 2585728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2595728Sgblack@eecs.umich.edu} 2602623SN/A 2615894Sgblack@eecs.umich.eduvoid 2626973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2636973Stjones1@inf.ed.ac.uk bool read) 2645744Sgblack@eecs.umich.edu{ 2655894Sgblack@eecs.umich.edu PacketPtr pkt; 2665894Sgblack@eecs.umich.edu buildPacket(pkt, req, read); 2677691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 2685894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2695894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2705894Sgblack@eecs.umich.edu pkt->makeResponse(); 2715894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2725894Sgblack@eecs.umich.edu } else if (read) { 2735894Sgblack@eecs.umich.edu handleReadPacket(pkt); 2745894Sgblack@eecs.umich.edu } else { 2755894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 2765894Sgblack@eecs.umich.edu 2776102Sgblack@eecs.umich.edu if (req->isLLSC()) { 2785894Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 2795894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 2805894Sgblack@eecs.umich.edu assert(res); 2815894Sgblack@eecs.umich.edu req->setExtraData(*res); 2825894Sgblack@eecs.umich.edu } 2835894Sgblack@eecs.umich.edu 2845894Sgblack@eecs.umich.edu if (do_access) { 2855894Sgblack@eecs.umich.edu dcache_pkt = pkt; 2865894Sgblack@eecs.umich.edu handleWritePacket(); 2875894Sgblack@eecs.umich.edu } else { 2885894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2895894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2905894Sgblack@eecs.umich.edu } 2915894Sgblack@eecs.umich.edu } 2925894Sgblack@eecs.umich.edu} 2935894Sgblack@eecs.umich.edu 2945894Sgblack@eecs.umich.eduvoid 2956973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 2966973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 2975894Sgblack@eecs.umich.edu{ 2985894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 2995894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3005894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3015894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3025894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3035894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3045894Sgblack@eecs.umich.edu } else if (read) { 3057911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3067911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3075894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3085894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3097911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3107911Shestness@cs.utexas.edu pkt2->senderState); 3115894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3125894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3135894Sgblack@eecs.umich.edu } 3145894Sgblack@eecs.umich.edu } 3155894Sgblack@eecs.umich.edu } else { 3165894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3177911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3187911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3195894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3205894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3215894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3227911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3237911Shestness@cs.utexas.edu pkt2->senderState); 3245894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3255894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3265894Sgblack@eecs.umich.edu } 3275894Sgblack@eecs.umich.edu } 3285894Sgblack@eecs.umich.edu } 3295894Sgblack@eecs.umich.edu} 3305894Sgblack@eecs.umich.edu 3315894Sgblack@eecs.umich.eduvoid 3325894Sgblack@eecs.umich.eduTimingSimpleCPU::translationFault(Fault fault) 3335894Sgblack@eecs.umich.edu{ 3346739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3356739Sgblack@eecs.umich.edu // for instance prefetches. 3369179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 3379179Sandreas.hansson@arm.com previousCycle = curCycle(); 3385894Sgblack@eecs.umich.edu 3395894Sgblack@eecs.umich.edu if (traceData) { 3405894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3415894Sgblack@eecs.umich.edu delete traceData; 3425894Sgblack@eecs.umich.edu traceData = NULL; 3435744Sgblack@eecs.umich.edu } 3445744Sgblack@eecs.umich.edu 3455894Sgblack@eecs.umich.edu postExecute(); 3465894Sgblack@eecs.umich.edu 3479342SAndreas.Sandberg@arm.com if (getDrainState() == Drainable::Draining) { 3485894Sgblack@eecs.umich.edu advancePC(fault); 3495894Sgblack@eecs.umich.edu completeDrain(); 3505894Sgblack@eecs.umich.edu } else { 3515894Sgblack@eecs.umich.edu advanceInst(fault); 3525894Sgblack@eecs.umich.edu } 3535894Sgblack@eecs.umich.edu} 3545894Sgblack@eecs.umich.edu 3555894Sgblack@eecs.umich.eduvoid 3565894Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 3575894Sgblack@eecs.umich.edu{ 3585894Sgblack@eecs.umich.edu MemCmd cmd; 3595894Sgblack@eecs.umich.edu if (read) { 3605894Sgblack@eecs.umich.edu cmd = MemCmd::ReadReq; 3616102Sgblack@eecs.umich.edu if (req->isLLSC()) 3625894Sgblack@eecs.umich.edu cmd = MemCmd::LoadLockedReq; 3635894Sgblack@eecs.umich.edu } else { 3645894Sgblack@eecs.umich.edu cmd = MemCmd::WriteReq; 3656102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3665894Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3675894Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3685894Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3695894Sgblack@eecs.umich.edu } 3705894Sgblack@eecs.umich.edu } 3718949Sandreas.hansson@arm.com pkt = new Packet(req, cmd); 3725894Sgblack@eecs.umich.edu} 3735894Sgblack@eecs.umich.edu 3745894Sgblack@eecs.umich.eduvoid 3755894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3765894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 3775894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3785894Sgblack@eecs.umich.edu{ 3795894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3805894Sgblack@eecs.umich.edu 3818105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 3825744Sgblack@eecs.umich.edu 3835894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3845894Sgblack@eecs.umich.edu buildPacket(pkt1, req, read); 3855894Sgblack@eecs.umich.edu return; 3865894Sgblack@eecs.umich.edu } 3875894Sgblack@eecs.umich.edu 3885894Sgblack@eecs.umich.edu buildPacket(pkt1, req1, read); 3895894Sgblack@eecs.umich.edu buildPacket(pkt2, req2, read); 3905894Sgblack@eecs.umich.edu 3918832SAli.Saidi@ARM.com req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId()); 3928949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 3935744Sgblack@eecs.umich.edu 3947691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 3955744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 3965744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 3975744Sgblack@eecs.umich.edu 3985744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 3995744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 4005744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 4015744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 4025744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 4035744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 4045744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 4055744Sgblack@eecs.umich.edu} 4065744Sgblack@eecs.umich.edu 4072623SN/AFault 4088444Sgblack@eecs.umich.eduTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 4098444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 4102623SN/A{ 4115728Sgblack@eecs.umich.edu Fault fault; 4125728Sgblack@eecs.umich.edu const int asid = 0; 4136221Snate@binkert.org const ThreadID tid = 0; 4147720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4156227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 4166973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4172623SN/A 4187045Ssteve.reinhardt@amd.com if (traceData) { 4197045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4207045Ssteve.reinhardt@amd.com } 4217045Ssteve.reinhardt@amd.com 4227520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4238832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4245728Sgblack@eecs.umich.edu 4257520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4265744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4275728Sgblack@eecs.umich.edu 4285894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4295744Sgblack@eecs.umich.edu if (split_addr > addr) { 4305894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4316102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4325894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4335894Sgblack@eecs.umich.edu 4346973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4357520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4366973Stjones1@inf.ed.ac.uk NULL, mode); 4378486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4388486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4398486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4408486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4416973Stjones1@inf.ed.ac.uk 4426973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 4436973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 4445744Sgblack@eecs.umich.edu } else { 4456973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4467520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4478486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4488486Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 4496973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 4502623SN/A } 4512623SN/A 4525728Sgblack@eecs.umich.edu return NoFault; 4532623SN/A} 4542623SN/A 4555728Sgblack@eecs.umich.edubool 4565728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4575728Sgblack@eecs.umich.edu{ 4585728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4598105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4609180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4619179Sandreas.hansson@arm.com new IprEvent(dcache_pkt, this, clockEdge(delay)); 4625728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4635728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4648975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 4655728Sgblack@eecs.umich.edu _status = DcacheRetry; 4665728Sgblack@eecs.umich.edu } else { 4675728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4685728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4695728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4705728Sgblack@eecs.umich.edu } 4715728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4725728Sgblack@eecs.umich.edu} 4732623SN/A 4742623SN/AFault 4758444Sgblack@eecs.umich.eduTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 4768444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 4772623SN/A{ 4788443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 4798443Sgblack@eecs.umich.edu memcpy(newData, data, size); 4808443Sgblack@eecs.umich.edu 4815728Sgblack@eecs.umich.edu const int asid = 0; 4826221Snate@binkert.org const ThreadID tid = 0; 4837720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4846227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 4856973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 4863169Sstever@eecs.umich.edu 4877045Ssteve.reinhardt@amd.com if (traceData) { 4887045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4897045Ssteve.reinhardt@amd.com } 4907045Ssteve.reinhardt@amd.com 4917520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4928832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4935728Sgblack@eecs.umich.edu 4947520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4955744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4965728Sgblack@eecs.umich.edu 4975894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4985744Sgblack@eecs.umich.edu if (split_addr > addr) { 4995894Sgblack@eecs.umich.edu RequestPtr req1, req2; 5006102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 5015894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5025894Sgblack@eecs.umich.edu 5036973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5048443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 5058486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 5068486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 5078486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 5088486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 5096973Stjones1@inf.ed.ac.uk 5106973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 5116973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 5125744Sgblack@eecs.umich.edu } else { 5136973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5148443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5158486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation = 5168486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state); 5176973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 5182623SN/A } 5192623SN/A 5207045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5215728Sgblack@eecs.umich.edu return NoFault; 5222623SN/A} 5232623SN/A 5242623SN/A 5252623SN/Avoid 5266973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5276973Stjones1@inf.ed.ac.uk{ 5289342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5296973Stjones1@inf.ed.ac.uk 5306973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 5316973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 5326973Stjones1@inf.ed.ac.uk state->setNoFault(); 5336973Stjones1@inf.ed.ac.uk } 5347691SAli.Saidi@ARM.com delete [] state->data; 5356973Stjones1@inf.ed.ac.uk state->deleteReqs(); 5366973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 5376973Stjones1@inf.ed.ac.uk } else { 5386973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 5396973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 5406973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 5416973Stjones1@inf.ed.ac.uk } else { 5426973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5436973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 5446973Stjones1@inf.ed.ac.uk } 5456973Stjones1@inf.ed.ac.uk } 5466973Stjones1@inf.ed.ac.uk 5476973Stjones1@inf.ed.ac.uk delete state; 5486973Stjones1@inf.ed.ac.uk} 5496973Stjones1@inf.ed.ac.uk 5506973Stjones1@inf.ed.ac.uk 5516973Stjones1@inf.ed.ac.ukvoid 5522623SN/ATimingSimpleCPU::fetch() 5532623SN/A{ 5545221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5555221Ssaidi@eecs.umich.edu 5563387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5573387Sgblack@eecs.umich.edu checkForInterrupts(); 5582631SN/A 5595348Ssaidi@eecs.umich.edu checkPcEventQueue(); 5605348Ssaidi@eecs.umich.edu 5618143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5628143SAli.Saidi@ARM.com if (_status == Idle) 5638143SAli.Saidi@ARM.com return; 5648143SAli.Saidi@ARM.com 5657720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5667720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 5672623SN/A 5687720Sgblack@eecs.umich.edu if (needToFetch) { 5699342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5705669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 5715712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 5725894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 5738277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 5746023Snate@binkert.org thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 5756023Snate@binkert.org BaseTLB::Execute); 5762623SN/A } else { 5775669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5785669Sgblack@eecs.umich.edu completeIfetch(NULL); 5795894Sgblack@eecs.umich.edu 5809179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 5819179Sandreas.hansson@arm.com previousCycle = curCycle(); 5825894Sgblack@eecs.umich.edu } 5835894Sgblack@eecs.umich.edu} 5845894Sgblack@eecs.umich.edu 5855894Sgblack@eecs.umich.edu 5865894Sgblack@eecs.umich.eduvoid 5875894Sgblack@eecs.umich.eduTimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc) 5885894Sgblack@eecs.umich.edu{ 5895894Sgblack@eecs.umich.edu if (fault == NoFault) { 5908277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 5918277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 5928949Sandreas.hansson@arm.com ifetch_pkt = new Packet(req, MemCmd::ReadReq); 5935894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 5948277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 5955894Sgblack@eecs.umich.edu 5968975Sandreas.hansson@arm.com if (!icachePort.sendTimingReq(ifetch_pkt)) { 5975894Sgblack@eecs.umich.edu // Need to wait for retry 5985894Sgblack@eecs.umich.edu _status = IcacheRetry; 5995894Sgblack@eecs.umich.edu } else { 6005894Sgblack@eecs.umich.edu // Need to wait for cache to respond 6015894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6025894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 6035894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 6045894Sgblack@eecs.umich.edu } 6055894Sgblack@eecs.umich.edu } else { 6068277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 6075894Sgblack@eecs.umich.edu delete req; 6085894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 6099342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6105894Sgblack@eecs.umich.edu advanceInst(fault); 6112623SN/A } 6123222Sktlim@umich.edu 6139179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 6149179Sandreas.hansson@arm.com previousCycle = curCycle(); 6152623SN/A} 6162623SN/A 6172623SN/A 6182623SN/Avoid 6192644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 6202623SN/A{ 6218276SAli.Saidi@ARM.com 6228276SAli.Saidi@ARM.com if (_status == Faulting) 6238276SAli.Saidi@ARM.com return; 6248276SAli.Saidi@ARM.com 6258276SAli.Saidi@ARM.com if (fault != NoFault) { 6268276SAli.Saidi@ARM.com advancePC(fault); 6278276SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 6288276SAli.Saidi@ARM.com reschedule(fetchEvent, nextCycle(), true); 6298276SAli.Saidi@ARM.com _status = Faulting; 6308276SAli.Saidi@ARM.com return; 6318276SAli.Saidi@ARM.com } 6328276SAli.Saidi@ARM.com 6338276SAli.Saidi@ARM.com 6348276SAli.Saidi@ARM.com if (!stayAtPC) 6355726Sgblack@eecs.umich.edu advancePC(fault); 6362623SN/A 6379342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6382631SN/A // kick off fetch of next instruction... callback from icache 6392631SN/A // response will cause that instruction to be executed, 6402631SN/A // keeping the CPU running. 6412631SN/A fetch(); 6422631SN/A } 6432623SN/A} 6442623SN/A 6452623SN/A 6462623SN/Avoid 6473349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 6482623SN/A{ 6498277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 6508277SAli.Saidi@ARM.com pkt->getAddr() : 0); 6518277SAli.Saidi@ARM.com 6522623SN/A // received a response from the icache: execute the received 6532623SN/A // instruction 6545669Sgblack@eecs.umich.edu 6555669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 6562623SN/A assert(_status == IcacheWaitResponse); 6572798Sktlim@umich.edu 6589342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6592644Sstever@eecs.umich.edu 6609179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 6619179Sandreas.hansson@arm.com previousCycle = curCycle(); 6623222Sktlim@umich.edu 6639342SAndreas.Sandberg@arm.com if (getDrainState() == Drainable::Draining) { 6645669Sgblack@eecs.umich.edu if (pkt) { 6655669Sgblack@eecs.umich.edu delete pkt->req; 6665669Sgblack@eecs.umich.edu delete pkt; 6675669Sgblack@eecs.umich.edu } 6683658Sktlim@umich.edu 6692839Sktlim@umich.edu completeDrain(); 6702798Sktlim@umich.edu return; 6712798Sktlim@umich.edu } 6722798Sktlim@umich.edu 6732623SN/A preExecute(); 6747725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 6752623SN/A // load or store: just send to dcache 6762623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 6777945SAli.Saidi@ARM.com 6787945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 6797945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 6807945SAli.Saidi@ARM.com // ifetch 6819342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6825894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 6835001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6845001Sgblack@eecs.umich.edu delete traceData; 6855001Sgblack@eecs.umich.edu traceData = NULL; 6863170Sstever@eecs.umich.edu } 6874998Sgblack@eecs.umich.edu 6882644Sstever@eecs.umich.edu postExecute(); 6895103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6905103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6915103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6925103Ssaidi@eecs.umich.edu instCnt++; 6932644Sstever@eecs.umich.edu advanceInst(fault); 6942644Sstever@eecs.umich.edu } 6955726Sgblack@eecs.umich.edu } else if (curStaticInst) { 6962623SN/A // non-memory instruction: execute completely now 6972623SN/A Fault fault = curStaticInst->execute(this, traceData); 6984998Sgblack@eecs.umich.edu 6994998Sgblack@eecs.umich.edu // keep an instruction count 7004998Sgblack@eecs.umich.edu if (fault == NoFault) 7014998Sgblack@eecs.umich.edu countInst(); 7027655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 7035001Sgblack@eecs.umich.edu delete traceData; 7045001Sgblack@eecs.umich.edu traceData = NULL; 7055001Sgblack@eecs.umich.edu } 7064998Sgblack@eecs.umich.edu 7072644Sstever@eecs.umich.edu postExecute(); 7085103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7095103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7105103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7115103Ssaidi@eecs.umich.edu instCnt++; 7122644Sstever@eecs.umich.edu advanceInst(fault); 7135726Sgblack@eecs.umich.edu } else { 7145726Sgblack@eecs.umich.edu advanceInst(NoFault); 7152623SN/A } 7163658Sktlim@umich.edu 7175669Sgblack@eecs.umich.edu if (pkt) { 7185669Sgblack@eecs.umich.edu delete pkt->req; 7195669Sgblack@eecs.umich.edu delete pkt; 7205669Sgblack@eecs.umich.edu } 7212623SN/A} 7222623SN/A 7232948Ssaidi@eecs.umich.eduvoid 7242948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7252948Ssaidi@eecs.umich.edu{ 7262948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7272948Ssaidi@eecs.umich.edu} 7282623SN/A 7292623SN/Abool 7308975Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 7312623SN/A{ 7329165Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); 7339165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 7349165Sandreas.hansson@arm.com Tick next_tick = cpu->nextCycle(); 7352948Ssaidi@eecs.umich.edu 7369165Sandreas.hansson@arm.com if (next_tick == curTick()) 7379165Sandreas.hansson@arm.com cpu->completeIfetch(pkt); 7389165Sandreas.hansson@arm.com else 7399165Sandreas.hansson@arm.com tickEvent.schedule(pkt, next_tick); 7408948Sandreas.hansson@arm.com 7414433Ssaidi@eecs.umich.edu return true; 7422623SN/A} 7432623SN/A 7442657Ssaidi@eecs.umich.eduvoid 7452623SN/ATimingSimpleCPU::IcachePort::recvRetry() 7462623SN/A{ 7472623SN/A // we shouldn't get a retry unless we have a packet that we're 7482623SN/A // waiting to transmit 7492623SN/A assert(cpu->ifetch_pkt != NULL); 7502623SN/A assert(cpu->_status == IcacheRetry); 7513349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7528975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 7532657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7542657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7552657Ssaidi@eecs.umich.edu } 7562623SN/A} 7572623SN/A 7582623SN/Avoid 7593349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 7602623SN/A{ 7612623SN/A // received a response from the dcache: complete the load or store 7622623SN/A // instruction 7634870Sstever@eecs.umich.edu assert(!pkt->isError()); 7647516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 7657516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 7662623SN/A 7679179Sandreas.hansson@arm.com numCycles += curCycle() - previousCycle; 7689179Sandreas.hansson@arm.com previousCycle = curCycle(); 7693184Srdreslin@umich.edu 7705728Sgblack@eecs.umich.edu if (pkt->senderState) { 7715728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 7725728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 7735728Sgblack@eecs.umich.edu assert(send_state); 7745728Sgblack@eecs.umich.edu delete pkt->req; 7755728Sgblack@eecs.umich.edu delete pkt; 7765728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 7775728Sgblack@eecs.umich.edu delete send_state; 7785728Sgblack@eecs.umich.edu 7795728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 7805728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 7815728Sgblack@eecs.umich.edu assert(main_send_state); 7825728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 7835728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 7845728Sgblack@eecs.umich.edu main_send_state->outstanding--; 7855728Sgblack@eecs.umich.edu 7865728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 7875728Sgblack@eecs.umich.edu return; 7885728Sgblack@eecs.umich.edu } else { 7895728Sgblack@eecs.umich.edu delete main_send_state; 7905728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 7915728Sgblack@eecs.umich.edu pkt = big_pkt; 7925728Sgblack@eecs.umich.edu } 7935728Sgblack@eecs.umich.edu } 7945728Sgblack@eecs.umich.edu 7959342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 7965728Sgblack@eecs.umich.edu 7972623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 7982623SN/A 7994998Sgblack@eecs.umich.edu // keep an instruction count 8004998Sgblack@eecs.umich.edu if (fault == NoFault) 8014998Sgblack@eecs.umich.edu countInst(); 8025001Sgblack@eecs.umich.edu else if (traceData) { 8035001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 8045001Sgblack@eecs.umich.edu delete traceData; 8055001Sgblack@eecs.umich.edu traceData = NULL; 8065001Sgblack@eecs.umich.edu } 8074998Sgblack@eecs.umich.edu 8085507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 8095507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 8106102Sgblack@eecs.umich.edu if (pkt->isRead() && pkt->req->isLLSC()) { 8113170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 8123170Sstever@eecs.umich.edu } 8133170Sstever@eecs.umich.edu 8142644Sstever@eecs.umich.edu delete pkt->req; 8152644Sstever@eecs.umich.edu delete pkt; 8162644Sstever@eecs.umich.edu 8173184Srdreslin@umich.edu postExecute(); 8183227Sktlim@umich.edu 8199342SAndreas.Sandberg@arm.com if (getDrainState() == Drainable::Draining) { 8203201Shsul@eecs.umich.edu advancePC(fault); 8213201Shsul@eecs.umich.edu completeDrain(); 8223201Shsul@eecs.umich.edu 8233201Shsul@eecs.umich.edu return; 8243201Shsul@eecs.umich.edu } 8253201Shsul@eecs.umich.edu 8262644Sstever@eecs.umich.edu advanceInst(fault); 8272623SN/A} 8282623SN/A 8292623SN/A 8302798Sktlim@umich.eduvoid 8312839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 8322798Sktlim@umich.edu{ 8339152Satgutier@umich.edu DPRINTF(Drain, "CPU done draining, processing drain event\n"); 8349342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 8359342SAndreas.Sandberg@arm.com drainManager->signalDrainDone(); 8362798Sktlim@umich.edu} 8372623SN/A 8382623SN/Abool 8398975Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 8402623SN/A{ 8419165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 8429165Sandreas.hansson@arm.com Tick next_tick = cpu->nextCycle(); 8432948Ssaidi@eecs.umich.edu 8449165Sandreas.hansson@arm.com if (next_tick == curTick()) { 8459165Sandreas.hansson@arm.com cpu->completeDataAccess(pkt); 8469165Sandreas.hansson@arm.com } else { 8479165Sandreas.hansson@arm.com if (!tickEvent.scheduled()) { 8489165Sandreas.hansson@arm.com tickEvent.schedule(pkt, next_tick); 8495728Sgblack@eecs.umich.edu } else { 8509165Sandreas.hansson@arm.com // In the case of a split transaction and a cache that is 8519165Sandreas.hansson@arm.com // faster than a CPU we could get two responses before 8529165Sandreas.hansson@arm.com // next_tick expires 8539165Sandreas.hansson@arm.com if (!retryEvent.scheduled()) 8549165Sandreas.hansson@arm.com cpu->schedule(retryEvent, next_tick); 8559165Sandreas.hansson@arm.com return false; 8564433Ssaidi@eecs.umich.edu } 8573310Srdreslin@umich.edu } 8588948Sandreas.hansson@arm.com 8594433Ssaidi@eecs.umich.edu return true; 8602948Ssaidi@eecs.umich.edu} 8612948Ssaidi@eecs.umich.edu 8622948Ssaidi@eecs.umich.eduvoid 8632948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 8642948Ssaidi@eecs.umich.edu{ 8652630SN/A cpu->completeDataAccess(pkt); 8662623SN/A} 8672623SN/A 8682657Ssaidi@eecs.umich.eduvoid 8692623SN/ATimingSimpleCPU::DcachePort::recvRetry() 8702623SN/A{ 8712623SN/A // we shouldn't get a retry unless we have a packet that we're 8722623SN/A // waiting to transmit 8732623SN/A assert(cpu->dcache_pkt != NULL); 8742623SN/A assert(cpu->_status == DcacheRetry); 8753349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 8765728Sgblack@eecs.umich.edu if (tmp->senderState) { 8775728Sgblack@eecs.umich.edu // This is a packet from a split access. 8785728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8795728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 8805728Sgblack@eecs.umich.edu assert(send_state); 8815728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8825728Sgblack@eecs.umich.edu 8835728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8845728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8855728Sgblack@eecs.umich.edu assert(main_send_state); 8865728Sgblack@eecs.umich.edu 8878975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 8885728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 8895728Sgblack@eecs.umich.edu // and try sending the other fragment. 8905728Sgblack@eecs.umich.edu send_state->clearFromParent(); 8915728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 8925728Sgblack@eecs.umich.edu if (other_index > 0) { 8935728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 8945728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 8955728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 8965728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 8975728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 8985728Sgblack@eecs.umich.edu } 8995728Sgblack@eecs.umich.edu } else { 9005728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9015728Sgblack@eecs.umich.edu // memory system takes ownership of packet 9025728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 9035728Sgblack@eecs.umich.edu } 9045728Sgblack@eecs.umich.edu } 9058975Sandreas.hansson@arm.com } else if (sendTimingReq(tmp)) { 9062657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9073170Sstever@eecs.umich.edu // memory system takes ownership of packet 9082657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 9092657Ssaidi@eecs.umich.edu } 9102623SN/A} 9112623SN/A 9125606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 9135606Snate@binkert.org Tick t) 9145606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 9155103Ssaidi@eecs.umich.edu{ 9165606Snate@binkert.org cpu->schedule(this, t); 9175103Ssaidi@eecs.umich.edu} 9185103Ssaidi@eecs.umich.edu 9195103Ssaidi@eecs.umich.eduvoid 9205103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 9215103Ssaidi@eecs.umich.edu{ 9225103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 9235103Ssaidi@eecs.umich.edu} 9245103Ssaidi@eecs.umich.edu 9255103Ssaidi@eecs.umich.educonst char * 9265336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 9275103Ssaidi@eecs.umich.edu{ 9285103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 9295103Ssaidi@eecs.umich.edu} 9305103Ssaidi@eecs.umich.edu 9312623SN/A 9325315Sstever@gmail.comvoid 9335315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 9345315Sstever@gmail.com{ 9355315Sstever@gmail.com dcachePort.printAddr(a); 9365315Sstever@gmail.com} 9375315Sstever@gmail.com 9385315Sstever@gmail.com 9392623SN/A//////////////////////////////////////////////////////////////////////// 9402623SN/A// 9412623SN/A// TimingSimpleCPU Simulation Object 9422623SN/A// 9434762Snate@binkert.orgTimingSimpleCPU * 9444762Snate@binkert.orgTimingSimpleCPUParams::create() 9452623SN/A{ 9465529Snate@binkert.org numThreads = 1; 9478779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 9484762Snate@binkert.org panic("only one workload allowed"); 9495529Snate@binkert.org return new TimingSimpleCPU(this); 9502623SN/A} 951