timing.cc revision 8707
12623SN/A/* 27725SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37725SAli.Saidi@ARM.com * All rights reserved 47725SAli.Saidi@ARM.com * 57725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137725SAli.Saidi@ARM.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 433170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 448105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 452623SN/A#include "arch/utility.hh" 464040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/simple/timing.hh" 492623SN/A#include "cpu/exetrace.hh" 508232Snate@binkert.org#include "debug/Config.hh" 518232Snate@binkert.org#include "debug/ExecFaulting.hh" 528232Snate@binkert.org#include "debug/SimpleCPU.hh" 533348Sbinkertn@umich.edu#include "mem/packet.hh" 543348Sbinkertn@umich.edu#include "mem/packet_access.hh" 554762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 567678Sgblack@eecs.umich.edu#include "sim/faults.hh" 572901Ssaidi@eecs.umich.edu#include "sim/system.hh" 582623SN/A 592623SN/Ausing namespace std; 602623SN/Ausing namespace TheISA; 612623SN/A 622856Srdreslin@umich.eduPort * 632856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 642856Srdreslin@umich.edu{ 652856Srdreslin@umich.edu if (if_name == "dcache_port") 662856Srdreslin@umich.edu return &dcachePort; 672856Srdreslin@umich.edu else if (if_name == "icache_port") 682856Srdreslin@umich.edu return &icachePort; 692856Srdreslin@umich.edu else 702856Srdreslin@umich.edu panic("No Such Port\n"); 712856Srdreslin@umich.edu} 722623SN/A 732623SN/Avoid 742623SN/ATimingSimpleCPU::init() 752623SN/A{ 762623SN/A BaseCPU::init(); 772623SN/A#if FULL_SYSTEM 782680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 792680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 802623SN/A 812623SN/A // initialize CPU, including PC 825712Shsul@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 832623SN/A } 848706Sandreas.hansson@arm.com 858706Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 868706Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 872623SN/A#endif 882623SN/A} 892623SN/A 902623SN/Avoid 918707Sandreas.hansson@arm.comTimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 922948Ssaidi@eecs.umich.edu{ 932948Ssaidi@eecs.umich.edu pkt = _pkt; 945606Snate@binkert.org cpu->schedule(this, t); 952948Ssaidi@eecs.umich.edu} 962948Ssaidi@eecs.umich.edu 975529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 988707Sandreas.hansson@arm.com : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 998707Sandreas.hansson@arm.com dcachePort(this), fetchEvent(this) 1002623SN/A{ 1012623SN/A _status = Idle; 1023647Srdreslin@umich.edu 1032623SN/A ifetch_pkt = dcache_pkt = NULL; 1042839Sktlim@umich.edu drainEvent = NULL; 1053222Sktlim@umich.edu previousTick = 0; 1062901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1077897Shestness@cs.utexas.edu system->totalNumInsts = 0; 1082623SN/A} 1092623SN/A 1102623SN/A 1112623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1122623SN/A{ 1132623SN/A} 1142623SN/A 1152623SN/Avoid 1162623SN/ATimingSimpleCPU::serialize(ostream &os) 1172623SN/A{ 1182915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1192915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1202623SN/A BaseSimpleCPU::serialize(os); 1212623SN/A} 1222623SN/A 1232623SN/Avoid 1242623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1252623SN/A{ 1262915Sktlim@umich.edu SimObject::State so_state; 1272915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1282623SN/A BaseSimpleCPU::unserialize(cp, section); 1292798Sktlim@umich.edu} 1302798Sktlim@umich.edu 1312901Ssaidi@eecs.umich.eduunsigned int 1322839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1332798Sktlim@umich.edu{ 1342839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1352798Sktlim@umich.edu // an access to complete. 1365496Ssaidi@eecs.umich.edu if (_status == Idle || _status == Running || _status == SwitchedOut) { 1372901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1382901Ssaidi@eecs.umich.edu return 0; 1392798Sktlim@umich.edu } else { 1402839Sktlim@umich.edu changeState(SimObject::Draining); 1412839Sktlim@umich.edu drainEvent = drain_event; 1422901Ssaidi@eecs.umich.edu return 1; 1432798Sktlim@umich.edu } 1442623SN/A} 1452623SN/A 1462623SN/Avoid 1472798Sktlim@umich.eduTimingSimpleCPU::resume() 1482623SN/A{ 1495221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1502798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1514762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1523201Shsul@eecs.umich.edu 1535710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1545710Scws3k@cs.virginia.edu deschedule(fetchEvent); 1552915Sktlim@umich.edu 1565710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1572623SN/A } 1582798Sktlim@umich.edu 1592901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1602798Sktlim@umich.edu} 1612798Sktlim@umich.edu 1622798Sktlim@umich.eduvoid 1632798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1642798Sktlim@umich.edu{ 1655496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 1662798Sktlim@umich.edu _status = SwitchedOut; 1677823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 1682867Sktlim@umich.edu 1692867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1702867Sktlim@umich.edu // we'll need to cancel it. 1715710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1725606Snate@binkert.org deschedule(fetchEvent); 1732623SN/A} 1742623SN/A 1752623SN/A 1762623SN/Avoid 1772623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1782623SN/A{ 1794192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 1802623SN/A 1812680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1822623SN/A // running and schedule its tick event. 1832680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1842680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1852680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 1862623SN/A _status = Running; 1872623SN/A break; 1882623SN/A } 1892623SN/A } 1903201Shsul@eecs.umich.edu 1913201Shsul@eecs.umich.edu if (_status != Running) { 1923201Shsul@eecs.umich.edu _status = Idle; 1933201Shsul@eecs.umich.edu } 1945169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 1957823Ssteve.reinhardt@amd.com previousTick = curTick(); 1962623SN/A} 1972623SN/A 1982623SN/A 1992623SN/Avoid 2002623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2012623SN/A{ 2025221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2035221Ssaidi@eecs.umich.edu 2042623SN/A assert(thread_num == 0); 2052683Sktlim@umich.edu assert(thread); 2062623SN/A 2072623SN/A assert(_status == Idle); 2082623SN/A 2092623SN/A notIdleFraction++; 2102623SN/A _status = Running; 2113686Sktlim@umich.edu 2122623SN/A // kick things off by initiating the fetch of the next instruction 2137823Ssteve.reinhardt@amd.com schedule(fetchEvent, nextCycle(curTick() + ticks(delay))); 2142623SN/A} 2152623SN/A 2162623SN/A 2172623SN/Avoid 2182623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2192623SN/A{ 2205221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2215221Ssaidi@eecs.umich.edu 2222623SN/A assert(thread_num == 0); 2232683Sktlim@umich.edu assert(thread); 2242623SN/A 2256043Sgblack@eecs.umich.edu if (_status == Idle) 2266043Sgblack@eecs.umich.edu return; 2276043Sgblack@eecs.umich.edu 2282644Sstever@eecs.umich.edu assert(_status == Running); 2292623SN/A 2302644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2312644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2322623SN/A 2332623SN/A notIdleFraction--; 2342623SN/A _status = Idle; 2352623SN/A} 2362623SN/A 2375728Sgblack@eecs.umich.edubool 2385728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2395728Sgblack@eecs.umich.edu{ 2405728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 2418105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2425728Sgblack@eecs.umich.edu Tick delay; 2435728Sgblack@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2447823Ssteve.reinhardt@amd.com new IprEvent(pkt, this, nextCycle(curTick() + delay)); 2455728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2465728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2475728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(pkt)) { 2485728Sgblack@eecs.umich.edu _status = DcacheRetry; 2495728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2505728Sgblack@eecs.umich.edu } else { 2515728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2525728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2535728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2545728Sgblack@eecs.umich.edu } 2555728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2565728Sgblack@eecs.umich.edu} 2572623SN/A 2585894Sgblack@eecs.umich.eduvoid 2596973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2606973Stjones1@inf.ed.ac.uk bool read) 2615744Sgblack@eecs.umich.edu{ 2625894Sgblack@eecs.umich.edu PacketPtr pkt; 2635894Sgblack@eecs.umich.edu buildPacket(pkt, req, read); 2647691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 2655894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2665894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2675894Sgblack@eecs.umich.edu pkt->makeResponse(); 2685894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2695894Sgblack@eecs.umich.edu } else if (read) { 2705894Sgblack@eecs.umich.edu handleReadPacket(pkt); 2715894Sgblack@eecs.umich.edu } else { 2725894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 2735894Sgblack@eecs.umich.edu 2746102Sgblack@eecs.umich.edu if (req->isLLSC()) { 2755894Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 2765894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 2775894Sgblack@eecs.umich.edu assert(res); 2785894Sgblack@eecs.umich.edu req->setExtraData(*res); 2795894Sgblack@eecs.umich.edu } 2805894Sgblack@eecs.umich.edu 2815894Sgblack@eecs.umich.edu if (do_access) { 2825894Sgblack@eecs.umich.edu dcache_pkt = pkt; 2835894Sgblack@eecs.umich.edu handleWritePacket(); 2845894Sgblack@eecs.umich.edu } else { 2855894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2865894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2875894Sgblack@eecs.umich.edu } 2885894Sgblack@eecs.umich.edu } 2895894Sgblack@eecs.umich.edu} 2905894Sgblack@eecs.umich.edu 2915894Sgblack@eecs.umich.eduvoid 2926973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 2936973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 2945894Sgblack@eecs.umich.edu{ 2955894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 2965894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 2975894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2985894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2995894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3005894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3015894Sgblack@eecs.umich.edu } else if (read) { 3027911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3037911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3045894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3055894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3067911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3077911Shestness@cs.utexas.edu pkt2->senderState); 3085894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3095894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3105894Sgblack@eecs.umich.edu } 3115894Sgblack@eecs.umich.edu } 3125894Sgblack@eecs.umich.edu } else { 3135894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3147911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3157911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3165894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3175894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3185894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3197911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3207911Shestness@cs.utexas.edu pkt2->senderState); 3215894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3225894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3235894Sgblack@eecs.umich.edu } 3245894Sgblack@eecs.umich.edu } 3255894Sgblack@eecs.umich.edu } 3265894Sgblack@eecs.umich.edu} 3275894Sgblack@eecs.umich.edu 3285894Sgblack@eecs.umich.eduvoid 3295894Sgblack@eecs.umich.eduTimingSimpleCPU::translationFault(Fault fault) 3305894Sgblack@eecs.umich.edu{ 3316739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3326739Sgblack@eecs.umich.edu // for instance prefetches. 3337823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 3347823Ssteve.reinhardt@amd.com previousTick = curTick(); 3355894Sgblack@eecs.umich.edu 3365894Sgblack@eecs.umich.edu if (traceData) { 3375894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3385894Sgblack@eecs.umich.edu delete traceData; 3395894Sgblack@eecs.umich.edu traceData = NULL; 3405744Sgblack@eecs.umich.edu } 3415744Sgblack@eecs.umich.edu 3425894Sgblack@eecs.umich.edu postExecute(); 3435894Sgblack@eecs.umich.edu 3445894Sgblack@eecs.umich.edu if (getState() == SimObject::Draining) { 3455894Sgblack@eecs.umich.edu advancePC(fault); 3465894Sgblack@eecs.umich.edu completeDrain(); 3475894Sgblack@eecs.umich.edu } else { 3485894Sgblack@eecs.umich.edu advanceInst(fault); 3495894Sgblack@eecs.umich.edu } 3505894Sgblack@eecs.umich.edu} 3515894Sgblack@eecs.umich.edu 3525894Sgblack@eecs.umich.eduvoid 3535894Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 3545894Sgblack@eecs.umich.edu{ 3555894Sgblack@eecs.umich.edu MemCmd cmd; 3565894Sgblack@eecs.umich.edu if (read) { 3575894Sgblack@eecs.umich.edu cmd = MemCmd::ReadReq; 3586102Sgblack@eecs.umich.edu if (req->isLLSC()) 3595894Sgblack@eecs.umich.edu cmd = MemCmd::LoadLockedReq; 3605894Sgblack@eecs.umich.edu } else { 3615894Sgblack@eecs.umich.edu cmd = MemCmd::WriteReq; 3626102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3635894Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3645894Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3655894Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3665894Sgblack@eecs.umich.edu } 3675894Sgblack@eecs.umich.edu } 3685894Sgblack@eecs.umich.edu pkt = new Packet(req, cmd, Packet::Broadcast); 3695894Sgblack@eecs.umich.edu} 3705894Sgblack@eecs.umich.edu 3715894Sgblack@eecs.umich.eduvoid 3725894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3735894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 3745894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3755894Sgblack@eecs.umich.edu{ 3765894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3775894Sgblack@eecs.umich.edu 3788105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 3795744Sgblack@eecs.umich.edu 3805894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3815894Sgblack@eecs.umich.edu buildPacket(pkt1, req, read); 3825894Sgblack@eecs.umich.edu return; 3835894Sgblack@eecs.umich.edu } 3845894Sgblack@eecs.umich.edu 3855894Sgblack@eecs.umich.edu buildPacket(pkt1, req1, read); 3865894Sgblack@eecs.umich.edu buildPacket(pkt2, req2, read); 3875894Sgblack@eecs.umich.edu 3885744Sgblack@eecs.umich.edu req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags()); 3895744Sgblack@eecs.umich.edu PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(), 3905744Sgblack@eecs.umich.edu Packet::Broadcast); 3915744Sgblack@eecs.umich.edu 3927691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 3935744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 3945744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 3955744Sgblack@eecs.umich.edu 3965744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 3975744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 3985744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 3995744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 4005744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 4015744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 4025744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 4035744Sgblack@eecs.umich.edu} 4045744Sgblack@eecs.umich.edu 4052623SN/AFault 4068444Sgblack@eecs.umich.eduTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 4078444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 4082623SN/A{ 4095728Sgblack@eecs.umich.edu Fault fault; 4105728Sgblack@eecs.umich.edu const int asid = 0; 4116221Snate@binkert.org const ThreadID tid = 0; 4127720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4136227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 4146973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4152623SN/A 4167045Ssteve.reinhardt@amd.com if (traceData) { 4177045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4187045Ssteve.reinhardt@amd.com } 4197045Ssteve.reinhardt@amd.com 4207520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4216221Snate@binkert.org flags, pc, _cpuId, tid); 4225728Sgblack@eecs.umich.edu 4237520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4245744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4255728Sgblack@eecs.umich.edu 4265894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4275744Sgblack@eecs.umich.edu if (split_addr > addr) { 4285894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4296102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4305894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4315894Sgblack@eecs.umich.edu 4326973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4337520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4346973Stjones1@inf.ed.ac.uk NULL, mode); 4358486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4368486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4378486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4388486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4396973Stjones1@inf.ed.ac.uk 4406973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 4416973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 4425744Sgblack@eecs.umich.edu } else { 4436973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4447520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4458486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4468486Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 4476973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 4482623SN/A } 4492623SN/A 4505728Sgblack@eecs.umich.edu return NoFault; 4512623SN/A} 4522623SN/A 4535728Sgblack@eecs.umich.edubool 4545728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4555728Sgblack@eecs.umich.edu{ 4565728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4578105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4585728Sgblack@eecs.umich.edu Tick delay; 4595728Sgblack@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4607823Ssteve.reinhardt@amd.com new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay)); 4615728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4625728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4635728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(dcache_pkt)) { 4645728Sgblack@eecs.umich.edu _status = DcacheRetry; 4655728Sgblack@eecs.umich.edu } else { 4665728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4675728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4685728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4695728Sgblack@eecs.umich.edu } 4705728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4715728Sgblack@eecs.umich.edu} 4722623SN/A 4732623SN/AFault 4748444Sgblack@eecs.umich.eduTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 4758444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 4762623SN/A{ 4778443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 4788443Sgblack@eecs.umich.edu memcpy(newData, data, size); 4798443Sgblack@eecs.umich.edu 4805728Sgblack@eecs.umich.edu const int asid = 0; 4816221Snate@binkert.org const ThreadID tid = 0; 4827720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4836227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 4846973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 4853169Sstever@eecs.umich.edu 4867045Ssteve.reinhardt@amd.com if (traceData) { 4877045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4887045Ssteve.reinhardt@amd.com } 4897045Ssteve.reinhardt@amd.com 4907520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4916221Snate@binkert.org flags, pc, _cpuId, tid); 4925728Sgblack@eecs.umich.edu 4937520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4945744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4955728Sgblack@eecs.umich.edu 4965894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4975744Sgblack@eecs.umich.edu if (split_addr > addr) { 4985894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4996102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 5005894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5015894Sgblack@eecs.umich.edu 5026973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5038443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 5048486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 5058486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 5068486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 5078486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 5086973Stjones1@inf.ed.ac.uk 5096973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 5106973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 5115744Sgblack@eecs.umich.edu } else { 5126973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5138443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5148486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation = 5158486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state); 5166973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 5172623SN/A } 5182623SN/A 5197045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5205728Sgblack@eecs.umich.edu return NoFault; 5212623SN/A} 5222623SN/A 5232623SN/A 5242623SN/Avoid 5256973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5266973Stjones1@inf.ed.ac.uk{ 5276973Stjones1@inf.ed.ac.uk _status = Running; 5286973Stjones1@inf.ed.ac.uk 5296973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 5306973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 5316973Stjones1@inf.ed.ac.uk state->setNoFault(); 5326973Stjones1@inf.ed.ac.uk } 5337691SAli.Saidi@ARM.com delete [] state->data; 5346973Stjones1@inf.ed.ac.uk state->deleteReqs(); 5356973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 5366973Stjones1@inf.ed.ac.uk } else { 5376973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 5386973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 5396973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 5406973Stjones1@inf.ed.ac.uk } else { 5416973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5426973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 5436973Stjones1@inf.ed.ac.uk } 5446973Stjones1@inf.ed.ac.uk } 5456973Stjones1@inf.ed.ac.uk 5466973Stjones1@inf.ed.ac.uk delete state; 5476973Stjones1@inf.ed.ac.uk} 5486973Stjones1@inf.ed.ac.uk 5496973Stjones1@inf.ed.ac.uk 5506973Stjones1@inf.ed.ac.ukvoid 5512623SN/ATimingSimpleCPU::fetch() 5522623SN/A{ 5535221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5545221Ssaidi@eecs.umich.edu 5553387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5563387Sgblack@eecs.umich.edu checkForInterrupts(); 5572631SN/A 5585348Ssaidi@eecs.umich.edu checkPcEventQueue(); 5595348Ssaidi@eecs.umich.edu 5608143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5618143SAli.Saidi@ARM.com if (_status == Idle) 5628143SAli.Saidi@ARM.com return; 5638143SAli.Saidi@ARM.com 5647720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5657720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 5662623SN/A 5677720Sgblack@eecs.umich.edu if (needToFetch) { 5688276SAli.Saidi@ARM.com _status = Running; 5695669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 5705712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 5715894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 5728277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 5736023Snate@binkert.org thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 5746023Snate@binkert.org BaseTLB::Execute); 5752623SN/A } else { 5765669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5775669Sgblack@eecs.umich.edu completeIfetch(NULL); 5785894Sgblack@eecs.umich.edu 5797823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 5807823Ssteve.reinhardt@amd.com previousTick = curTick(); 5815894Sgblack@eecs.umich.edu } 5825894Sgblack@eecs.umich.edu} 5835894Sgblack@eecs.umich.edu 5845894Sgblack@eecs.umich.edu 5855894Sgblack@eecs.umich.eduvoid 5865894Sgblack@eecs.umich.eduTimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc) 5875894Sgblack@eecs.umich.edu{ 5885894Sgblack@eecs.umich.edu if (fault == NoFault) { 5898277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 5908277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 5915894Sgblack@eecs.umich.edu ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 5925894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 5938277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 5945894Sgblack@eecs.umich.edu 5955894Sgblack@eecs.umich.edu if (!icachePort.sendTiming(ifetch_pkt)) { 5965894Sgblack@eecs.umich.edu // Need to wait for retry 5975894Sgblack@eecs.umich.edu _status = IcacheRetry; 5985894Sgblack@eecs.umich.edu } else { 5995894Sgblack@eecs.umich.edu // Need to wait for cache to respond 6005894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6015894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 6025894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 6035894Sgblack@eecs.umich.edu } 6045894Sgblack@eecs.umich.edu } else { 6058277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 6065894Sgblack@eecs.umich.edu delete req; 6075894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 6087945SAli.Saidi@ARM.com _status = Running; 6095894Sgblack@eecs.umich.edu advanceInst(fault); 6102623SN/A } 6113222Sktlim@umich.edu 6127823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 6137823Ssteve.reinhardt@amd.com previousTick = curTick(); 6142623SN/A} 6152623SN/A 6162623SN/A 6172623SN/Avoid 6182644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 6192623SN/A{ 6208276SAli.Saidi@ARM.com 6218276SAli.Saidi@ARM.com if (_status == Faulting) 6228276SAli.Saidi@ARM.com return; 6238276SAli.Saidi@ARM.com 6248276SAli.Saidi@ARM.com if (fault != NoFault) { 6258276SAli.Saidi@ARM.com advancePC(fault); 6268276SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 6278276SAli.Saidi@ARM.com reschedule(fetchEvent, nextCycle(), true); 6288276SAli.Saidi@ARM.com _status = Faulting; 6298276SAli.Saidi@ARM.com return; 6308276SAli.Saidi@ARM.com } 6318276SAli.Saidi@ARM.com 6328276SAli.Saidi@ARM.com 6338276SAli.Saidi@ARM.com if (!stayAtPC) 6345726Sgblack@eecs.umich.edu advancePC(fault); 6352623SN/A 6362631SN/A if (_status == Running) { 6372631SN/A // kick off fetch of next instruction... callback from icache 6382631SN/A // response will cause that instruction to be executed, 6392631SN/A // keeping the CPU running. 6402631SN/A fetch(); 6412631SN/A } 6422623SN/A} 6432623SN/A 6442623SN/A 6452623SN/Avoid 6463349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 6472623SN/A{ 6488277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 6498277SAli.Saidi@ARM.com pkt->getAddr() : 0); 6508277SAli.Saidi@ARM.com 6512623SN/A // received a response from the icache: execute the received 6522623SN/A // instruction 6535669Sgblack@eecs.umich.edu 6545669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 6552623SN/A assert(_status == IcacheWaitResponse); 6562798Sktlim@umich.edu 6572623SN/A _status = Running; 6582644Sstever@eecs.umich.edu 6597823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 6607823Ssteve.reinhardt@amd.com previousTick = curTick(); 6613222Sktlim@umich.edu 6622839Sktlim@umich.edu if (getState() == SimObject::Draining) { 6635669Sgblack@eecs.umich.edu if (pkt) { 6645669Sgblack@eecs.umich.edu delete pkt->req; 6655669Sgblack@eecs.umich.edu delete pkt; 6665669Sgblack@eecs.umich.edu } 6673658Sktlim@umich.edu 6682839Sktlim@umich.edu completeDrain(); 6692798Sktlim@umich.edu return; 6702798Sktlim@umich.edu } 6712798Sktlim@umich.edu 6722623SN/A preExecute(); 6737725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 6742623SN/A // load or store: just send to dcache 6752623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 6767945SAli.Saidi@ARM.com 6777945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 6787945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 6797945SAli.Saidi@ARM.com // ifetch 6807945SAli.Saidi@ARM.com if (_status == Running) { 6815894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 6825001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6835001Sgblack@eecs.umich.edu delete traceData; 6845001Sgblack@eecs.umich.edu traceData = NULL; 6853170Sstever@eecs.umich.edu } 6864998Sgblack@eecs.umich.edu 6872644Sstever@eecs.umich.edu postExecute(); 6885103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6895103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6905103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6915103Ssaidi@eecs.umich.edu instCnt++; 6922644Sstever@eecs.umich.edu advanceInst(fault); 6932644Sstever@eecs.umich.edu } 6945726Sgblack@eecs.umich.edu } else if (curStaticInst) { 6952623SN/A // non-memory instruction: execute completely now 6962623SN/A Fault fault = curStaticInst->execute(this, traceData); 6974998Sgblack@eecs.umich.edu 6984998Sgblack@eecs.umich.edu // keep an instruction count 6994998Sgblack@eecs.umich.edu if (fault == NoFault) 7004998Sgblack@eecs.umich.edu countInst(); 7017655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 7025001Sgblack@eecs.umich.edu delete traceData; 7035001Sgblack@eecs.umich.edu traceData = NULL; 7045001Sgblack@eecs.umich.edu } 7054998Sgblack@eecs.umich.edu 7062644Sstever@eecs.umich.edu postExecute(); 7075103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7085103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7095103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7105103Ssaidi@eecs.umich.edu instCnt++; 7112644Sstever@eecs.umich.edu advanceInst(fault); 7125726Sgblack@eecs.umich.edu } else { 7135726Sgblack@eecs.umich.edu advanceInst(NoFault); 7142623SN/A } 7153658Sktlim@umich.edu 7165669Sgblack@eecs.umich.edu if (pkt) { 7175669Sgblack@eecs.umich.edu delete pkt->req; 7185669Sgblack@eecs.umich.edu delete pkt; 7195669Sgblack@eecs.umich.edu } 7202623SN/A} 7212623SN/A 7222948Ssaidi@eecs.umich.eduvoid 7232948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7242948Ssaidi@eecs.umich.edu{ 7252948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7262948Ssaidi@eecs.umich.edu} 7272623SN/A 7282623SN/Abool 7293349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 7302623SN/A{ 7314986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 7328277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); 7333310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 7347823Ssteve.reinhardt@amd.com Tick next_tick = cpu->nextCycle(curTick()); 7352948Ssaidi@eecs.umich.edu 7367823Ssteve.reinhardt@amd.com if (next_tick == curTick()) 7373310Srdreslin@umich.edu cpu->completeIfetch(pkt); 7383310Srdreslin@umich.edu else 7393495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 7402948Ssaidi@eecs.umich.edu 7413310Srdreslin@umich.edu return true; 7428276SAli.Saidi@ARM.com } else if (pkt->wasNacked()) { 7434433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 7444433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 7454433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 7464433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 7474433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 7484433Ssaidi@eecs.umich.edu } 7493310Srdreslin@umich.edu } 7504433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 7514433Ssaidi@eecs.umich.edu return true; 7522623SN/A} 7532623SN/A 7542657Ssaidi@eecs.umich.eduvoid 7552623SN/ATimingSimpleCPU::IcachePort::recvRetry() 7562623SN/A{ 7572623SN/A // we shouldn't get a retry unless we have a packet that we're 7582623SN/A // waiting to transmit 7592623SN/A assert(cpu->ifetch_pkt != NULL); 7602623SN/A assert(cpu->_status == IcacheRetry); 7613349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7622657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 7632657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7642657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7652657Ssaidi@eecs.umich.edu } 7662623SN/A} 7672623SN/A 7682623SN/Avoid 7693349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 7702623SN/A{ 7712623SN/A // received a response from the dcache: complete the load or store 7722623SN/A // instruction 7734870Sstever@eecs.umich.edu assert(!pkt->isError()); 7747516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 7757516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 7762623SN/A 7777823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 7787823Ssteve.reinhardt@amd.com previousTick = curTick(); 7793184Srdreslin@umich.edu 7805728Sgblack@eecs.umich.edu if (pkt->senderState) { 7815728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 7825728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 7835728Sgblack@eecs.umich.edu assert(send_state); 7845728Sgblack@eecs.umich.edu delete pkt->req; 7855728Sgblack@eecs.umich.edu delete pkt; 7865728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 7875728Sgblack@eecs.umich.edu delete send_state; 7885728Sgblack@eecs.umich.edu 7895728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 7905728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 7915728Sgblack@eecs.umich.edu assert(main_send_state); 7925728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 7935728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 7945728Sgblack@eecs.umich.edu main_send_state->outstanding--; 7955728Sgblack@eecs.umich.edu 7965728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 7975728Sgblack@eecs.umich.edu return; 7985728Sgblack@eecs.umich.edu } else { 7995728Sgblack@eecs.umich.edu delete main_send_state; 8005728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 8015728Sgblack@eecs.umich.edu pkt = big_pkt; 8025728Sgblack@eecs.umich.edu } 8035728Sgblack@eecs.umich.edu } 8045728Sgblack@eecs.umich.edu 8055728Sgblack@eecs.umich.edu _status = Running; 8065728Sgblack@eecs.umich.edu 8072623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 8082623SN/A 8094998Sgblack@eecs.umich.edu // keep an instruction count 8104998Sgblack@eecs.umich.edu if (fault == NoFault) 8114998Sgblack@eecs.umich.edu countInst(); 8125001Sgblack@eecs.umich.edu else if (traceData) { 8135001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 8145001Sgblack@eecs.umich.edu delete traceData; 8155001Sgblack@eecs.umich.edu traceData = NULL; 8165001Sgblack@eecs.umich.edu } 8174998Sgblack@eecs.umich.edu 8185507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 8195507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 8206102Sgblack@eecs.umich.edu if (pkt->isRead() && pkt->req->isLLSC()) { 8213170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 8223170Sstever@eecs.umich.edu } 8233170Sstever@eecs.umich.edu 8242644Sstever@eecs.umich.edu delete pkt->req; 8252644Sstever@eecs.umich.edu delete pkt; 8262644Sstever@eecs.umich.edu 8273184Srdreslin@umich.edu postExecute(); 8283227Sktlim@umich.edu 8293201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 8303201Shsul@eecs.umich.edu advancePC(fault); 8313201Shsul@eecs.umich.edu completeDrain(); 8323201Shsul@eecs.umich.edu 8333201Shsul@eecs.umich.edu return; 8343201Shsul@eecs.umich.edu } 8353201Shsul@eecs.umich.edu 8362644Sstever@eecs.umich.edu advanceInst(fault); 8372623SN/A} 8382623SN/A 8392623SN/A 8402798Sktlim@umich.eduvoid 8412839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 8422798Sktlim@umich.edu{ 8432839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 8442901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 8452839Sktlim@umich.edu drainEvent->process(); 8462798Sktlim@umich.edu} 8472623SN/A 8482623SN/Abool 8493349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 8502623SN/A{ 8514986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 8523310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 8537823Ssteve.reinhardt@amd.com Tick next_tick = cpu->nextCycle(curTick()); 8542948Ssaidi@eecs.umich.edu 8557823Ssteve.reinhardt@amd.com if (next_tick == curTick()) { 8563310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 8575728Sgblack@eecs.umich.edu } else { 8587745SAli.Saidi@ARM.com if (!tickEvent.scheduled()) { 8597745SAli.Saidi@ARM.com tickEvent.schedule(pkt, next_tick); 8607745SAli.Saidi@ARM.com } else { 8617745SAli.Saidi@ARM.com // In the case of a split transaction and a cache that is 8627745SAli.Saidi@ARM.com // faster than a CPU we could get two responses before 8637745SAli.Saidi@ARM.com // next_tick expires 8647745SAli.Saidi@ARM.com if (!retryEvent.scheduled()) 8657745SAli.Saidi@ARM.com schedule(retryEvent, next_tick); 8667745SAli.Saidi@ARM.com return false; 8677745SAli.Saidi@ARM.com } 8685728Sgblack@eecs.umich.edu } 8692948Ssaidi@eecs.umich.edu 8703310Srdreslin@umich.edu return true; 8713310Srdreslin@umich.edu } 8724870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 8734433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 8744433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 8754433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 8764433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 8774433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 8784433Ssaidi@eecs.umich.edu } 8793310Srdreslin@umich.edu } 8804433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 8814433Ssaidi@eecs.umich.edu return true; 8822948Ssaidi@eecs.umich.edu} 8832948Ssaidi@eecs.umich.edu 8842948Ssaidi@eecs.umich.eduvoid 8852948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 8862948Ssaidi@eecs.umich.edu{ 8872630SN/A cpu->completeDataAccess(pkt); 8882623SN/A} 8892623SN/A 8902657Ssaidi@eecs.umich.eduvoid 8912623SN/ATimingSimpleCPU::DcachePort::recvRetry() 8922623SN/A{ 8932623SN/A // we shouldn't get a retry unless we have a packet that we're 8942623SN/A // waiting to transmit 8952623SN/A assert(cpu->dcache_pkt != NULL); 8962623SN/A assert(cpu->_status == DcacheRetry); 8973349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 8985728Sgblack@eecs.umich.edu if (tmp->senderState) { 8995728Sgblack@eecs.umich.edu // This is a packet from a split access. 9005728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 9015728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 9025728Sgblack@eecs.umich.edu assert(send_state); 9035728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 9045728Sgblack@eecs.umich.edu 9055728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 9065728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 9075728Sgblack@eecs.umich.edu assert(main_send_state); 9085728Sgblack@eecs.umich.edu 9095728Sgblack@eecs.umich.edu if (sendTiming(tmp)) { 9105728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 9115728Sgblack@eecs.umich.edu // and try sending the other fragment. 9125728Sgblack@eecs.umich.edu send_state->clearFromParent(); 9135728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 9145728Sgblack@eecs.umich.edu if (other_index > 0) { 9155728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 9165728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 9175728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 9185728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 9195728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 9205728Sgblack@eecs.umich.edu } 9215728Sgblack@eecs.umich.edu } else { 9225728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9235728Sgblack@eecs.umich.edu // memory system takes ownership of packet 9245728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 9255728Sgblack@eecs.umich.edu } 9265728Sgblack@eecs.umich.edu } 9275728Sgblack@eecs.umich.edu } else if (sendTiming(tmp)) { 9282657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9293170Sstever@eecs.umich.edu // memory system takes ownership of packet 9302657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 9312657Ssaidi@eecs.umich.edu } 9322623SN/A} 9332623SN/A 9345606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 9355606Snate@binkert.org Tick t) 9365606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 9375103Ssaidi@eecs.umich.edu{ 9385606Snate@binkert.org cpu->schedule(this, t); 9395103Ssaidi@eecs.umich.edu} 9405103Ssaidi@eecs.umich.edu 9415103Ssaidi@eecs.umich.eduvoid 9425103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 9435103Ssaidi@eecs.umich.edu{ 9445103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 9455103Ssaidi@eecs.umich.edu} 9465103Ssaidi@eecs.umich.edu 9475103Ssaidi@eecs.umich.educonst char * 9485336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 9495103Ssaidi@eecs.umich.edu{ 9505103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 9515103Ssaidi@eecs.umich.edu} 9525103Ssaidi@eecs.umich.edu 9532623SN/A 9545315Sstever@gmail.comvoid 9555315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 9565315Sstever@gmail.com{ 9575315Sstever@gmail.com dcachePort.printAddr(a); 9585315Sstever@gmail.com} 9595315Sstever@gmail.com 9605315Sstever@gmail.com 9612623SN/A//////////////////////////////////////////////////////////////////////// 9622623SN/A// 9632623SN/A// TimingSimpleCPU Simulation Object 9642623SN/A// 9654762Snate@binkert.orgTimingSimpleCPU * 9664762Snate@binkert.orgTimingSimpleCPUParams::create() 9672623SN/A{ 9685529Snate@binkert.org numThreads = 1; 9695529Snate@binkert.org#if !FULL_SYSTEM 9704762Snate@binkert.org if (workload.size() != 1) 9714762Snate@binkert.org panic("only one workload allowed"); 9722623SN/A#endif 9735529Snate@binkert.org return new TimingSimpleCPU(this); 9742623SN/A} 975