timing.cc revision 8706
12623SN/A/* 27725SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37725SAli.Saidi@ARM.com * All rights reserved 47725SAli.Saidi@ARM.com * 57725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137725SAli.Saidi@ARM.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 433170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 448105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 452623SN/A#include "arch/utility.hh" 464040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/simple/timing.hh" 492623SN/A#include "cpu/exetrace.hh" 508232Snate@binkert.org#include "debug/Config.hh" 518232Snate@binkert.org#include "debug/ExecFaulting.hh" 528232Snate@binkert.org#include "debug/SimpleCPU.hh" 533348Sbinkertn@umich.edu#include "mem/packet.hh" 543348Sbinkertn@umich.edu#include "mem/packet_access.hh" 554762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 567678Sgblack@eecs.umich.edu#include "sim/faults.hh" 572901Ssaidi@eecs.umich.edu#include "sim/system.hh" 582623SN/A 592623SN/Ausing namespace std; 602623SN/Ausing namespace TheISA; 612623SN/A 622856Srdreslin@umich.eduPort * 632856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 642856Srdreslin@umich.edu{ 652856Srdreslin@umich.edu if (if_name == "dcache_port") 662856Srdreslin@umich.edu return &dcachePort; 672856Srdreslin@umich.edu else if (if_name == "icache_port") 682856Srdreslin@umich.edu return &icachePort; 692856Srdreslin@umich.edu else 702856Srdreslin@umich.edu panic("No Such Port\n"); 712856Srdreslin@umich.edu} 722623SN/A 732623SN/Avoid 742623SN/ATimingSimpleCPU::init() 752623SN/A{ 762623SN/A BaseCPU::init(); 772623SN/A#if FULL_SYSTEM 782680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 792680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 802623SN/A 812623SN/A // initialize CPU, including PC 825712Shsul@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 832623SN/A } 848706Sandreas.hansson@arm.com 858706Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 868706Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 872623SN/A#endif 882623SN/A} 892623SN/A 902623SN/ATick 913349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 922623SN/A{ 932623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 947823Ssteve.reinhardt@amd.com return curTick(); 952623SN/A} 962623SN/A 972623SN/Avoid 983349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 992623SN/A{ 1003184Srdreslin@umich.edu //No internal storage to update, jusst return 1013184Srdreslin@umich.edu return; 1022623SN/A} 1032623SN/A 1042623SN/Avoid 1052623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 1062623SN/A{ 1073647Srdreslin@umich.edu if (status == RangeChange) { 1083647Srdreslin@umich.edu if (!snoopRangeSent) { 1093647Srdreslin@umich.edu snoopRangeSent = true; 1103647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 1113647Srdreslin@umich.edu } 1122631SN/A return; 1133647Srdreslin@umich.edu } 1142631SN/A 1152623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 1162623SN/A} 1172623SN/A 1182948Ssaidi@eecs.umich.edu 1192948Ssaidi@eecs.umich.eduvoid 1203349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1212948Ssaidi@eecs.umich.edu{ 1222948Ssaidi@eecs.umich.edu pkt = _pkt; 1235606Snate@binkert.org cpu->schedule(this, t); 1242948Ssaidi@eecs.umich.edu} 1252948Ssaidi@eecs.umich.edu 1265529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 1275894Sgblack@eecs.umich.edu : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this, p->clock), 1285894Sgblack@eecs.umich.edu dcachePort(this, p->clock), fetchEvent(this) 1292623SN/A{ 1302623SN/A _status = Idle; 1313647Srdreslin@umich.edu 1323647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1333647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1343647Srdreslin@umich.edu 1352623SN/A ifetch_pkt = dcache_pkt = NULL; 1362839Sktlim@umich.edu drainEvent = NULL; 1373222Sktlim@umich.edu previousTick = 0; 1382901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1397897Shestness@cs.utexas.edu system->totalNumInsts = 0; 1402623SN/A} 1412623SN/A 1422623SN/A 1432623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1442623SN/A{ 1452623SN/A} 1462623SN/A 1472623SN/Avoid 1482623SN/ATimingSimpleCPU::serialize(ostream &os) 1492623SN/A{ 1502915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1512915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1522623SN/A BaseSimpleCPU::serialize(os); 1532623SN/A} 1542623SN/A 1552623SN/Avoid 1562623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1572623SN/A{ 1582915Sktlim@umich.edu SimObject::State so_state; 1592915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1602623SN/A BaseSimpleCPU::unserialize(cp, section); 1612798Sktlim@umich.edu} 1622798Sktlim@umich.edu 1632901Ssaidi@eecs.umich.eduunsigned int 1642839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1652798Sktlim@umich.edu{ 1662839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1672798Sktlim@umich.edu // an access to complete. 1685496Ssaidi@eecs.umich.edu if (_status == Idle || _status == Running || _status == SwitchedOut) { 1692901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1702901Ssaidi@eecs.umich.edu return 0; 1712798Sktlim@umich.edu } else { 1722839Sktlim@umich.edu changeState(SimObject::Draining); 1732839Sktlim@umich.edu drainEvent = drain_event; 1742901Ssaidi@eecs.umich.edu return 1; 1752798Sktlim@umich.edu } 1762623SN/A} 1772623SN/A 1782623SN/Avoid 1792798Sktlim@umich.eduTimingSimpleCPU::resume() 1802623SN/A{ 1815221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1822798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1834762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1843201Shsul@eecs.umich.edu 1855710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1865710Scws3k@cs.virginia.edu deschedule(fetchEvent); 1872915Sktlim@umich.edu 1885710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1892623SN/A } 1902798Sktlim@umich.edu 1912901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1922798Sktlim@umich.edu} 1932798Sktlim@umich.edu 1942798Sktlim@umich.eduvoid 1952798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1962798Sktlim@umich.edu{ 1975496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 1982798Sktlim@umich.edu _status = SwitchedOut; 1997823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 2002867Sktlim@umich.edu 2012867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 2022867Sktlim@umich.edu // we'll need to cancel it. 2035710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 2045606Snate@binkert.org deschedule(fetchEvent); 2052623SN/A} 2062623SN/A 2072623SN/A 2082623SN/Avoid 2092623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2102623SN/A{ 2114192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 2122623SN/A 2132680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 2142623SN/A // running and schedule its tick event. 2152680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2162680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2172680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2182623SN/A _status = Running; 2192623SN/A break; 2202623SN/A } 2212623SN/A } 2223201Shsul@eecs.umich.edu 2233201Shsul@eecs.umich.edu if (_status != Running) { 2243201Shsul@eecs.umich.edu _status = Idle; 2253201Shsul@eecs.umich.edu } 2265169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2277823Ssteve.reinhardt@amd.com previousTick = curTick(); 2282623SN/A} 2292623SN/A 2302623SN/A 2312623SN/Avoid 2322623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2332623SN/A{ 2345221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2355221Ssaidi@eecs.umich.edu 2362623SN/A assert(thread_num == 0); 2372683Sktlim@umich.edu assert(thread); 2382623SN/A 2392623SN/A assert(_status == Idle); 2402623SN/A 2412623SN/A notIdleFraction++; 2422623SN/A _status = Running; 2433686Sktlim@umich.edu 2442623SN/A // kick things off by initiating the fetch of the next instruction 2457823Ssteve.reinhardt@amd.com schedule(fetchEvent, nextCycle(curTick() + ticks(delay))); 2462623SN/A} 2472623SN/A 2482623SN/A 2492623SN/Avoid 2502623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2512623SN/A{ 2525221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2535221Ssaidi@eecs.umich.edu 2542623SN/A assert(thread_num == 0); 2552683Sktlim@umich.edu assert(thread); 2562623SN/A 2576043Sgblack@eecs.umich.edu if (_status == Idle) 2586043Sgblack@eecs.umich.edu return; 2596043Sgblack@eecs.umich.edu 2602644Sstever@eecs.umich.edu assert(_status == Running); 2612623SN/A 2622644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2632644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2642623SN/A 2652623SN/A notIdleFraction--; 2662623SN/A _status = Idle; 2672623SN/A} 2682623SN/A 2695728Sgblack@eecs.umich.edubool 2705728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2715728Sgblack@eecs.umich.edu{ 2725728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 2738105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2745728Sgblack@eecs.umich.edu Tick delay; 2755728Sgblack@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2767823Ssteve.reinhardt@amd.com new IprEvent(pkt, this, nextCycle(curTick() + delay)); 2775728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2785728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2795728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(pkt)) { 2805728Sgblack@eecs.umich.edu _status = DcacheRetry; 2815728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2825728Sgblack@eecs.umich.edu } else { 2835728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2845728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2855728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2865728Sgblack@eecs.umich.edu } 2875728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2885728Sgblack@eecs.umich.edu} 2892623SN/A 2905894Sgblack@eecs.umich.eduvoid 2916973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2926973Stjones1@inf.ed.ac.uk bool read) 2935744Sgblack@eecs.umich.edu{ 2945894Sgblack@eecs.umich.edu PacketPtr pkt; 2955894Sgblack@eecs.umich.edu buildPacket(pkt, req, read); 2967691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 2975894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2985894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2995894Sgblack@eecs.umich.edu pkt->makeResponse(); 3005894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3015894Sgblack@eecs.umich.edu } else if (read) { 3025894Sgblack@eecs.umich.edu handleReadPacket(pkt); 3035894Sgblack@eecs.umich.edu } else { 3045894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3055894Sgblack@eecs.umich.edu 3066102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3075894Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3085894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 3095894Sgblack@eecs.umich.edu assert(res); 3105894Sgblack@eecs.umich.edu req->setExtraData(*res); 3115894Sgblack@eecs.umich.edu } 3125894Sgblack@eecs.umich.edu 3135894Sgblack@eecs.umich.edu if (do_access) { 3145894Sgblack@eecs.umich.edu dcache_pkt = pkt; 3155894Sgblack@eecs.umich.edu handleWritePacket(); 3165894Sgblack@eecs.umich.edu } else { 3175894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 3185894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3195894Sgblack@eecs.umich.edu } 3205894Sgblack@eecs.umich.edu } 3215894Sgblack@eecs.umich.edu} 3225894Sgblack@eecs.umich.edu 3235894Sgblack@eecs.umich.eduvoid 3246973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 3256973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 3265894Sgblack@eecs.umich.edu{ 3275894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3285894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3295894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3305894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3315894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3325894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3335894Sgblack@eecs.umich.edu } else if (read) { 3347911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3357911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3365894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3375894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3387911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3397911Shestness@cs.utexas.edu pkt2->senderState); 3405894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3415894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3425894Sgblack@eecs.umich.edu } 3435894Sgblack@eecs.umich.edu } 3445894Sgblack@eecs.umich.edu } else { 3455894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3467911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3477911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3485894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3495894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3505894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3517911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3527911Shestness@cs.utexas.edu pkt2->senderState); 3535894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3545894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3555894Sgblack@eecs.umich.edu } 3565894Sgblack@eecs.umich.edu } 3575894Sgblack@eecs.umich.edu } 3585894Sgblack@eecs.umich.edu} 3595894Sgblack@eecs.umich.edu 3605894Sgblack@eecs.umich.eduvoid 3615894Sgblack@eecs.umich.eduTimingSimpleCPU::translationFault(Fault fault) 3625894Sgblack@eecs.umich.edu{ 3636739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3646739Sgblack@eecs.umich.edu // for instance prefetches. 3657823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 3667823Ssteve.reinhardt@amd.com previousTick = curTick(); 3675894Sgblack@eecs.umich.edu 3685894Sgblack@eecs.umich.edu if (traceData) { 3695894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3705894Sgblack@eecs.umich.edu delete traceData; 3715894Sgblack@eecs.umich.edu traceData = NULL; 3725744Sgblack@eecs.umich.edu } 3735744Sgblack@eecs.umich.edu 3745894Sgblack@eecs.umich.edu postExecute(); 3755894Sgblack@eecs.umich.edu 3765894Sgblack@eecs.umich.edu if (getState() == SimObject::Draining) { 3775894Sgblack@eecs.umich.edu advancePC(fault); 3785894Sgblack@eecs.umich.edu completeDrain(); 3795894Sgblack@eecs.umich.edu } else { 3805894Sgblack@eecs.umich.edu advanceInst(fault); 3815894Sgblack@eecs.umich.edu } 3825894Sgblack@eecs.umich.edu} 3835894Sgblack@eecs.umich.edu 3845894Sgblack@eecs.umich.eduvoid 3855894Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 3865894Sgblack@eecs.umich.edu{ 3875894Sgblack@eecs.umich.edu MemCmd cmd; 3885894Sgblack@eecs.umich.edu if (read) { 3895894Sgblack@eecs.umich.edu cmd = MemCmd::ReadReq; 3906102Sgblack@eecs.umich.edu if (req->isLLSC()) 3915894Sgblack@eecs.umich.edu cmd = MemCmd::LoadLockedReq; 3925894Sgblack@eecs.umich.edu } else { 3935894Sgblack@eecs.umich.edu cmd = MemCmd::WriteReq; 3946102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3955894Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3965894Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3975894Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3985894Sgblack@eecs.umich.edu } 3995894Sgblack@eecs.umich.edu } 4005894Sgblack@eecs.umich.edu pkt = new Packet(req, cmd, Packet::Broadcast); 4015894Sgblack@eecs.umich.edu} 4025894Sgblack@eecs.umich.edu 4035894Sgblack@eecs.umich.eduvoid 4045894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 4055894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 4065894Sgblack@eecs.umich.edu uint8_t *data, bool read) 4075894Sgblack@eecs.umich.edu{ 4085894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 4095894Sgblack@eecs.umich.edu 4108105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 4115744Sgblack@eecs.umich.edu 4125894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 4135894Sgblack@eecs.umich.edu buildPacket(pkt1, req, read); 4145894Sgblack@eecs.umich.edu return; 4155894Sgblack@eecs.umich.edu } 4165894Sgblack@eecs.umich.edu 4175894Sgblack@eecs.umich.edu buildPacket(pkt1, req1, read); 4185894Sgblack@eecs.umich.edu buildPacket(pkt2, req2, read); 4195894Sgblack@eecs.umich.edu 4205744Sgblack@eecs.umich.edu req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags()); 4215744Sgblack@eecs.umich.edu PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(), 4225744Sgblack@eecs.umich.edu Packet::Broadcast); 4235744Sgblack@eecs.umich.edu 4247691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 4255744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 4265744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 4275744Sgblack@eecs.umich.edu 4285744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 4295744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 4305744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 4315744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 4325744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 4335744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 4345744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 4355744Sgblack@eecs.umich.edu} 4365744Sgblack@eecs.umich.edu 4372623SN/AFault 4388444Sgblack@eecs.umich.eduTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 4398444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 4402623SN/A{ 4415728Sgblack@eecs.umich.edu Fault fault; 4425728Sgblack@eecs.umich.edu const int asid = 0; 4436221Snate@binkert.org const ThreadID tid = 0; 4447720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4456227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 4466973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4472623SN/A 4487045Ssteve.reinhardt@amd.com if (traceData) { 4497045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4507045Ssteve.reinhardt@amd.com } 4517045Ssteve.reinhardt@amd.com 4527520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4536221Snate@binkert.org flags, pc, _cpuId, tid); 4545728Sgblack@eecs.umich.edu 4557520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4565744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4575728Sgblack@eecs.umich.edu 4585894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4595744Sgblack@eecs.umich.edu if (split_addr > addr) { 4605894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4616102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4625894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4635894Sgblack@eecs.umich.edu 4646973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4657520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4666973Stjones1@inf.ed.ac.uk NULL, mode); 4678486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4688486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4698486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4708486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4716973Stjones1@inf.ed.ac.uk 4726973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 4736973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 4745744Sgblack@eecs.umich.edu } else { 4756973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4767520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4778486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4788486Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 4796973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 4802623SN/A } 4812623SN/A 4825728Sgblack@eecs.umich.edu return NoFault; 4832623SN/A} 4842623SN/A 4855728Sgblack@eecs.umich.edubool 4865728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4875728Sgblack@eecs.umich.edu{ 4885728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4898105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4905728Sgblack@eecs.umich.edu Tick delay; 4915728Sgblack@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4927823Ssteve.reinhardt@amd.com new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay)); 4935728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4945728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4955728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(dcache_pkt)) { 4965728Sgblack@eecs.umich.edu _status = DcacheRetry; 4975728Sgblack@eecs.umich.edu } else { 4985728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4995728Sgblack@eecs.umich.edu // memory system takes ownership of packet 5005728Sgblack@eecs.umich.edu dcache_pkt = NULL; 5015728Sgblack@eecs.umich.edu } 5025728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 5035728Sgblack@eecs.umich.edu} 5042623SN/A 5052623SN/AFault 5068444Sgblack@eecs.umich.eduTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 5078444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 5082623SN/A{ 5098443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 5108443Sgblack@eecs.umich.edu memcpy(newData, data, size); 5118443Sgblack@eecs.umich.edu 5125728Sgblack@eecs.umich.edu const int asid = 0; 5136221Snate@binkert.org const ThreadID tid = 0; 5147720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 5156227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 5166973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 5173169Sstever@eecs.umich.edu 5187045Ssteve.reinhardt@amd.com if (traceData) { 5197045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 5207045Ssteve.reinhardt@amd.com } 5217045Ssteve.reinhardt@amd.com 5227520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 5236221Snate@binkert.org flags, pc, _cpuId, tid); 5245728Sgblack@eecs.umich.edu 5257520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 5265744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 5275728Sgblack@eecs.umich.edu 5285894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 5295744Sgblack@eecs.umich.edu if (split_addr > addr) { 5305894Sgblack@eecs.umich.edu RequestPtr req1, req2; 5316102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 5325894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5335894Sgblack@eecs.umich.edu 5346973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5358443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 5368486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 5378486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 5388486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 5398486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 5406973Stjones1@inf.ed.ac.uk 5416973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 5426973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 5435744Sgblack@eecs.umich.edu } else { 5446973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5458443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5468486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation = 5478486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state); 5486973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 5492623SN/A } 5502623SN/A 5517045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5525728Sgblack@eecs.umich.edu return NoFault; 5532623SN/A} 5542623SN/A 5552623SN/A 5562623SN/Avoid 5576973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5586973Stjones1@inf.ed.ac.uk{ 5596973Stjones1@inf.ed.ac.uk _status = Running; 5606973Stjones1@inf.ed.ac.uk 5616973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 5626973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 5636973Stjones1@inf.ed.ac.uk state->setNoFault(); 5646973Stjones1@inf.ed.ac.uk } 5657691SAli.Saidi@ARM.com delete [] state->data; 5666973Stjones1@inf.ed.ac.uk state->deleteReqs(); 5676973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 5686973Stjones1@inf.ed.ac.uk } else { 5696973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 5706973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 5716973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 5726973Stjones1@inf.ed.ac.uk } else { 5736973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5746973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 5756973Stjones1@inf.ed.ac.uk } 5766973Stjones1@inf.ed.ac.uk } 5776973Stjones1@inf.ed.ac.uk 5786973Stjones1@inf.ed.ac.uk delete state; 5796973Stjones1@inf.ed.ac.uk} 5806973Stjones1@inf.ed.ac.uk 5816973Stjones1@inf.ed.ac.uk 5826973Stjones1@inf.ed.ac.ukvoid 5832623SN/ATimingSimpleCPU::fetch() 5842623SN/A{ 5855221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5865221Ssaidi@eecs.umich.edu 5873387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5883387Sgblack@eecs.umich.edu checkForInterrupts(); 5892631SN/A 5905348Ssaidi@eecs.umich.edu checkPcEventQueue(); 5915348Ssaidi@eecs.umich.edu 5928143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5938143SAli.Saidi@ARM.com if (_status == Idle) 5948143SAli.Saidi@ARM.com return; 5958143SAli.Saidi@ARM.com 5967720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5977720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 5982623SN/A 5997720Sgblack@eecs.umich.edu if (needToFetch) { 6008276SAli.Saidi@ARM.com _status = Running; 6015669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 6025712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 6035894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 6048277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 6056023Snate@binkert.org thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 6066023Snate@binkert.org BaseTLB::Execute); 6072623SN/A } else { 6085669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6095669Sgblack@eecs.umich.edu completeIfetch(NULL); 6105894Sgblack@eecs.umich.edu 6117823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 6127823Ssteve.reinhardt@amd.com previousTick = curTick(); 6135894Sgblack@eecs.umich.edu } 6145894Sgblack@eecs.umich.edu} 6155894Sgblack@eecs.umich.edu 6165894Sgblack@eecs.umich.edu 6175894Sgblack@eecs.umich.eduvoid 6185894Sgblack@eecs.umich.eduTimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc) 6195894Sgblack@eecs.umich.edu{ 6205894Sgblack@eecs.umich.edu if (fault == NoFault) { 6218277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 6228277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 6235894Sgblack@eecs.umich.edu ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 6245894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 6258277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 6265894Sgblack@eecs.umich.edu 6275894Sgblack@eecs.umich.edu if (!icachePort.sendTiming(ifetch_pkt)) { 6285894Sgblack@eecs.umich.edu // Need to wait for retry 6295894Sgblack@eecs.umich.edu _status = IcacheRetry; 6305894Sgblack@eecs.umich.edu } else { 6315894Sgblack@eecs.umich.edu // Need to wait for cache to respond 6325894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6335894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 6345894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 6355894Sgblack@eecs.umich.edu } 6365894Sgblack@eecs.umich.edu } else { 6378277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 6385894Sgblack@eecs.umich.edu delete req; 6395894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 6407945SAli.Saidi@ARM.com _status = Running; 6415894Sgblack@eecs.umich.edu advanceInst(fault); 6422623SN/A } 6433222Sktlim@umich.edu 6447823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 6457823Ssteve.reinhardt@amd.com previousTick = curTick(); 6462623SN/A} 6472623SN/A 6482623SN/A 6492623SN/Avoid 6502644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 6512623SN/A{ 6528276SAli.Saidi@ARM.com 6538276SAli.Saidi@ARM.com if (_status == Faulting) 6548276SAli.Saidi@ARM.com return; 6558276SAli.Saidi@ARM.com 6568276SAli.Saidi@ARM.com if (fault != NoFault) { 6578276SAli.Saidi@ARM.com advancePC(fault); 6588276SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 6598276SAli.Saidi@ARM.com reschedule(fetchEvent, nextCycle(), true); 6608276SAli.Saidi@ARM.com _status = Faulting; 6618276SAli.Saidi@ARM.com return; 6628276SAli.Saidi@ARM.com } 6638276SAli.Saidi@ARM.com 6648276SAli.Saidi@ARM.com 6658276SAli.Saidi@ARM.com if (!stayAtPC) 6665726Sgblack@eecs.umich.edu advancePC(fault); 6672623SN/A 6682631SN/A if (_status == Running) { 6692631SN/A // kick off fetch of next instruction... callback from icache 6702631SN/A // response will cause that instruction to be executed, 6712631SN/A // keeping the CPU running. 6722631SN/A fetch(); 6732631SN/A } 6742623SN/A} 6752623SN/A 6762623SN/A 6772623SN/Avoid 6783349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 6792623SN/A{ 6808277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 6818277SAli.Saidi@ARM.com pkt->getAddr() : 0); 6828277SAli.Saidi@ARM.com 6832623SN/A // received a response from the icache: execute the received 6842623SN/A // instruction 6855669Sgblack@eecs.umich.edu 6865669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 6872623SN/A assert(_status == IcacheWaitResponse); 6882798Sktlim@umich.edu 6892623SN/A _status = Running; 6902644Sstever@eecs.umich.edu 6917823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 6927823Ssteve.reinhardt@amd.com previousTick = curTick(); 6933222Sktlim@umich.edu 6942839Sktlim@umich.edu if (getState() == SimObject::Draining) { 6955669Sgblack@eecs.umich.edu if (pkt) { 6965669Sgblack@eecs.umich.edu delete pkt->req; 6975669Sgblack@eecs.umich.edu delete pkt; 6985669Sgblack@eecs.umich.edu } 6993658Sktlim@umich.edu 7002839Sktlim@umich.edu completeDrain(); 7012798Sktlim@umich.edu return; 7022798Sktlim@umich.edu } 7032798Sktlim@umich.edu 7042623SN/A preExecute(); 7057725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 7062623SN/A // load or store: just send to dcache 7072623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 7087945SAli.Saidi@ARM.com 7097945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 7107945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 7117945SAli.Saidi@ARM.com // ifetch 7127945SAli.Saidi@ARM.com if (_status == Running) { 7135894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 7145001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7155001Sgblack@eecs.umich.edu delete traceData; 7165001Sgblack@eecs.umich.edu traceData = NULL; 7173170Sstever@eecs.umich.edu } 7184998Sgblack@eecs.umich.edu 7192644Sstever@eecs.umich.edu postExecute(); 7205103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7215103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7225103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7235103Ssaidi@eecs.umich.edu instCnt++; 7242644Sstever@eecs.umich.edu advanceInst(fault); 7252644Sstever@eecs.umich.edu } 7265726Sgblack@eecs.umich.edu } else if (curStaticInst) { 7272623SN/A // non-memory instruction: execute completely now 7282623SN/A Fault fault = curStaticInst->execute(this, traceData); 7294998Sgblack@eecs.umich.edu 7304998Sgblack@eecs.umich.edu // keep an instruction count 7314998Sgblack@eecs.umich.edu if (fault == NoFault) 7324998Sgblack@eecs.umich.edu countInst(); 7337655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 7345001Sgblack@eecs.umich.edu delete traceData; 7355001Sgblack@eecs.umich.edu traceData = NULL; 7365001Sgblack@eecs.umich.edu } 7374998Sgblack@eecs.umich.edu 7382644Sstever@eecs.umich.edu postExecute(); 7395103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7405103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7415103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7425103Ssaidi@eecs.umich.edu instCnt++; 7432644Sstever@eecs.umich.edu advanceInst(fault); 7445726Sgblack@eecs.umich.edu } else { 7455726Sgblack@eecs.umich.edu advanceInst(NoFault); 7462623SN/A } 7473658Sktlim@umich.edu 7485669Sgblack@eecs.umich.edu if (pkt) { 7495669Sgblack@eecs.umich.edu delete pkt->req; 7505669Sgblack@eecs.umich.edu delete pkt; 7515669Sgblack@eecs.umich.edu } 7522623SN/A} 7532623SN/A 7542948Ssaidi@eecs.umich.eduvoid 7552948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7562948Ssaidi@eecs.umich.edu{ 7572948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7582948Ssaidi@eecs.umich.edu} 7592623SN/A 7602623SN/Abool 7613349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 7622623SN/A{ 7634986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 7648277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); 7653310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 7667823Ssteve.reinhardt@amd.com Tick next_tick = cpu->nextCycle(curTick()); 7672948Ssaidi@eecs.umich.edu 7687823Ssteve.reinhardt@amd.com if (next_tick == curTick()) 7693310Srdreslin@umich.edu cpu->completeIfetch(pkt); 7703310Srdreslin@umich.edu else 7713495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 7722948Ssaidi@eecs.umich.edu 7733310Srdreslin@umich.edu return true; 7748276SAli.Saidi@ARM.com } else if (pkt->wasNacked()) { 7754433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 7764433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 7774433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 7784433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 7794433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 7804433Ssaidi@eecs.umich.edu } 7813310Srdreslin@umich.edu } 7824433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 7834433Ssaidi@eecs.umich.edu return true; 7842623SN/A} 7852623SN/A 7862657Ssaidi@eecs.umich.eduvoid 7872623SN/ATimingSimpleCPU::IcachePort::recvRetry() 7882623SN/A{ 7892623SN/A // we shouldn't get a retry unless we have a packet that we're 7902623SN/A // waiting to transmit 7912623SN/A assert(cpu->ifetch_pkt != NULL); 7922623SN/A assert(cpu->_status == IcacheRetry); 7933349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7942657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 7952657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7962657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7972657Ssaidi@eecs.umich.edu } 7982623SN/A} 7992623SN/A 8002623SN/Avoid 8013349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 8022623SN/A{ 8032623SN/A // received a response from the dcache: complete the load or store 8042623SN/A // instruction 8054870Sstever@eecs.umich.edu assert(!pkt->isError()); 8067516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 8077516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 8082623SN/A 8097823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 8107823Ssteve.reinhardt@amd.com previousTick = curTick(); 8113184Srdreslin@umich.edu 8125728Sgblack@eecs.umich.edu if (pkt->senderState) { 8135728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8145728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 8155728Sgblack@eecs.umich.edu assert(send_state); 8165728Sgblack@eecs.umich.edu delete pkt->req; 8175728Sgblack@eecs.umich.edu delete pkt; 8185728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8195728Sgblack@eecs.umich.edu delete send_state; 8205728Sgblack@eecs.umich.edu 8215728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8225728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8235728Sgblack@eecs.umich.edu assert(main_send_state); 8245728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 8255728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 8265728Sgblack@eecs.umich.edu main_send_state->outstanding--; 8275728Sgblack@eecs.umich.edu 8285728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 8295728Sgblack@eecs.umich.edu return; 8305728Sgblack@eecs.umich.edu } else { 8315728Sgblack@eecs.umich.edu delete main_send_state; 8325728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 8335728Sgblack@eecs.umich.edu pkt = big_pkt; 8345728Sgblack@eecs.umich.edu } 8355728Sgblack@eecs.umich.edu } 8365728Sgblack@eecs.umich.edu 8375728Sgblack@eecs.umich.edu _status = Running; 8385728Sgblack@eecs.umich.edu 8392623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 8402623SN/A 8414998Sgblack@eecs.umich.edu // keep an instruction count 8424998Sgblack@eecs.umich.edu if (fault == NoFault) 8434998Sgblack@eecs.umich.edu countInst(); 8445001Sgblack@eecs.umich.edu else if (traceData) { 8455001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 8465001Sgblack@eecs.umich.edu delete traceData; 8475001Sgblack@eecs.umich.edu traceData = NULL; 8485001Sgblack@eecs.umich.edu } 8494998Sgblack@eecs.umich.edu 8505507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 8515507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 8526102Sgblack@eecs.umich.edu if (pkt->isRead() && pkt->req->isLLSC()) { 8533170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 8543170Sstever@eecs.umich.edu } 8553170Sstever@eecs.umich.edu 8562644Sstever@eecs.umich.edu delete pkt->req; 8572644Sstever@eecs.umich.edu delete pkt; 8582644Sstever@eecs.umich.edu 8593184Srdreslin@umich.edu postExecute(); 8603227Sktlim@umich.edu 8613201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 8623201Shsul@eecs.umich.edu advancePC(fault); 8633201Shsul@eecs.umich.edu completeDrain(); 8643201Shsul@eecs.umich.edu 8653201Shsul@eecs.umich.edu return; 8663201Shsul@eecs.umich.edu } 8673201Shsul@eecs.umich.edu 8682644Sstever@eecs.umich.edu advanceInst(fault); 8692623SN/A} 8702623SN/A 8712623SN/A 8722798Sktlim@umich.eduvoid 8732839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 8742798Sktlim@umich.edu{ 8752839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 8762901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 8772839Sktlim@umich.edu drainEvent->process(); 8782798Sktlim@umich.edu} 8792623SN/A 8802623SN/Abool 8813349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 8822623SN/A{ 8834986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 8843310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 8857823Ssteve.reinhardt@amd.com Tick next_tick = cpu->nextCycle(curTick()); 8862948Ssaidi@eecs.umich.edu 8877823Ssteve.reinhardt@amd.com if (next_tick == curTick()) { 8883310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 8895728Sgblack@eecs.umich.edu } else { 8907745SAli.Saidi@ARM.com if (!tickEvent.scheduled()) { 8917745SAli.Saidi@ARM.com tickEvent.schedule(pkt, next_tick); 8927745SAli.Saidi@ARM.com } else { 8937745SAli.Saidi@ARM.com // In the case of a split transaction and a cache that is 8947745SAli.Saidi@ARM.com // faster than a CPU we could get two responses before 8957745SAli.Saidi@ARM.com // next_tick expires 8967745SAli.Saidi@ARM.com if (!retryEvent.scheduled()) 8977745SAli.Saidi@ARM.com schedule(retryEvent, next_tick); 8987745SAli.Saidi@ARM.com return false; 8997745SAli.Saidi@ARM.com } 9005728Sgblack@eecs.umich.edu } 9012948Ssaidi@eecs.umich.edu 9023310Srdreslin@umich.edu return true; 9033310Srdreslin@umich.edu } 9044870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 9054433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 9064433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 9074433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 9084433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 9094433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 9104433Ssaidi@eecs.umich.edu } 9113310Srdreslin@umich.edu } 9124433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 9134433Ssaidi@eecs.umich.edu return true; 9142948Ssaidi@eecs.umich.edu} 9152948Ssaidi@eecs.umich.edu 9162948Ssaidi@eecs.umich.eduvoid 9172948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 9182948Ssaidi@eecs.umich.edu{ 9192630SN/A cpu->completeDataAccess(pkt); 9202623SN/A} 9212623SN/A 9222657Ssaidi@eecs.umich.eduvoid 9232623SN/ATimingSimpleCPU::DcachePort::recvRetry() 9242623SN/A{ 9252623SN/A // we shouldn't get a retry unless we have a packet that we're 9262623SN/A // waiting to transmit 9272623SN/A assert(cpu->dcache_pkt != NULL); 9282623SN/A assert(cpu->_status == DcacheRetry); 9293349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 9305728Sgblack@eecs.umich.edu if (tmp->senderState) { 9315728Sgblack@eecs.umich.edu // This is a packet from a split access. 9325728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 9335728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 9345728Sgblack@eecs.umich.edu assert(send_state); 9355728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 9365728Sgblack@eecs.umich.edu 9375728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 9385728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 9395728Sgblack@eecs.umich.edu assert(main_send_state); 9405728Sgblack@eecs.umich.edu 9415728Sgblack@eecs.umich.edu if (sendTiming(tmp)) { 9425728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 9435728Sgblack@eecs.umich.edu // and try sending the other fragment. 9445728Sgblack@eecs.umich.edu send_state->clearFromParent(); 9455728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 9465728Sgblack@eecs.umich.edu if (other_index > 0) { 9475728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 9485728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 9495728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 9505728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 9515728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 9525728Sgblack@eecs.umich.edu } 9535728Sgblack@eecs.umich.edu } else { 9545728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9555728Sgblack@eecs.umich.edu // memory system takes ownership of packet 9565728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 9575728Sgblack@eecs.umich.edu } 9585728Sgblack@eecs.umich.edu } 9595728Sgblack@eecs.umich.edu } else if (sendTiming(tmp)) { 9602657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9613170Sstever@eecs.umich.edu // memory system takes ownership of packet 9622657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 9632657Ssaidi@eecs.umich.edu } 9642623SN/A} 9652623SN/A 9665606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 9675606Snate@binkert.org Tick t) 9685606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 9695103Ssaidi@eecs.umich.edu{ 9705606Snate@binkert.org cpu->schedule(this, t); 9715103Ssaidi@eecs.umich.edu} 9725103Ssaidi@eecs.umich.edu 9735103Ssaidi@eecs.umich.eduvoid 9745103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 9755103Ssaidi@eecs.umich.edu{ 9765103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 9775103Ssaidi@eecs.umich.edu} 9785103Ssaidi@eecs.umich.edu 9795103Ssaidi@eecs.umich.educonst char * 9805336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 9815103Ssaidi@eecs.umich.edu{ 9825103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 9835103Ssaidi@eecs.umich.edu} 9845103Ssaidi@eecs.umich.edu 9852623SN/A 9865315Sstever@gmail.comvoid 9875315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 9885315Sstever@gmail.com{ 9895315Sstever@gmail.com dcachePort.printAddr(a); 9905315Sstever@gmail.com} 9915315Sstever@gmail.com 9925315Sstever@gmail.com 9932623SN/A//////////////////////////////////////////////////////////////////////// 9942623SN/A// 9952623SN/A// TimingSimpleCPU Simulation Object 9962623SN/A// 9974762Snate@binkert.orgTimingSimpleCPU * 9984762Snate@binkert.orgTimingSimpleCPUParams::create() 9992623SN/A{ 10005529Snate@binkert.org numThreads = 1; 10015529Snate@binkert.org#if !FULL_SYSTEM 10024762Snate@binkert.org if (workload.size() != 1) 10034762Snate@binkert.org panic("only one workload allowed"); 10042623SN/A#endif 10055529Snate@binkert.org return new TimingSimpleCPU(this); 10062623SN/A} 1007