timing.cc revision 8443
12623SN/A/* 27725SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37725SAli.Saidi@ARM.com * All rights reserved 47725SAli.Saidi@ARM.com * 57725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137725SAli.Saidi@ARM.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 433170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 448105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 452623SN/A#include "arch/utility.hh" 464040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/simple/timing.hh" 492623SN/A#include "cpu/exetrace.hh" 508232Snate@binkert.org#include "debug/Config.hh" 518232Snate@binkert.org#include "debug/ExecFaulting.hh" 528232Snate@binkert.org#include "debug/SimpleCPU.hh" 533348Sbinkertn@umich.edu#include "mem/packet.hh" 543348Sbinkertn@umich.edu#include "mem/packet_access.hh" 554762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 567678Sgblack@eecs.umich.edu#include "sim/faults.hh" 572901Ssaidi@eecs.umich.edu#include "sim/system.hh" 582623SN/A 592623SN/Ausing namespace std; 602623SN/Ausing namespace TheISA; 612623SN/A 622856Srdreslin@umich.eduPort * 632856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 642856Srdreslin@umich.edu{ 652856Srdreslin@umich.edu if (if_name == "dcache_port") 662856Srdreslin@umich.edu return &dcachePort; 672856Srdreslin@umich.edu else if (if_name == "icache_port") 682856Srdreslin@umich.edu return &icachePort; 692856Srdreslin@umich.edu else 702856Srdreslin@umich.edu panic("No Such Port\n"); 712856Srdreslin@umich.edu} 722623SN/A 732623SN/Avoid 742623SN/ATimingSimpleCPU::init() 752623SN/A{ 762623SN/A BaseCPU::init(); 772623SN/A#if FULL_SYSTEM 782680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 792680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 802623SN/A 812623SN/A // initialize CPU, including PC 825712Shsul@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 832623SN/A } 842623SN/A#endif 852623SN/A} 862623SN/A 872623SN/ATick 883349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 892623SN/A{ 902623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 917823Ssteve.reinhardt@amd.com return curTick(); 922623SN/A} 932623SN/A 942623SN/Avoid 953349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 962623SN/A{ 973184Srdreslin@umich.edu //No internal storage to update, jusst return 983184Srdreslin@umich.edu return; 992623SN/A} 1002623SN/A 1012623SN/Avoid 1022623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 1032623SN/A{ 1043647Srdreslin@umich.edu if (status == RangeChange) { 1053647Srdreslin@umich.edu if (!snoopRangeSent) { 1063647Srdreslin@umich.edu snoopRangeSent = true; 1073647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 1083647Srdreslin@umich.edu } 1092631SN/A return; 1103647Srdreslin@umich.edu } 1112631SN/A 1122623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 1132623SN/A} 1142623SN/A 1152948Ssaidi@eecs.umich.edu 1162948Ssaidi@eecs.umich.eduvoid 1173349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1182948Ssaidi@eecs.umich.edu{ 1192948Ssaidi@eecs.umich.edu pkt = _pkt; 1205606Snate@binkert.org cpu->schedule(this, t); 1212948Ssaidi@eecs.umich.edu} 1222948Ssaidi@eecs.umich.edu 1235529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 1245894Sgblack@eecs.umich.edu : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this, p->clock), 1255894Sgblack@eecs.umich.edu dcachePort(this, p->clock), fetchEvent(this) 1262623SN/A{ 1272623SN/A _status = Idle; 1283647Srdreslin@umich.edu 1293647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1303647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1313647Srdreslin@umich.edu 1322623SN/A ifetch_pkt = dcache_pkt = NULL; 1332839Sktlim@umich.edu drainEvent = NULL; 1343222Sktlim@umich.edu previousTick = 0; 1352901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1367897Shestness@cs.utexas.edu system->totalNumInsts = 0; 1372623SN/A} 1382623SN/A 1392623SN/A 1402623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1412623SN/A{ 1422623SN/A} 1432623SN/A 1442623SN/Avoid 1452623SN/ATimingSimpleCPU::serialize(ostream &os) 1462623SN/A{ 1472915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1482915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1492623SN/A BaseSimpleCPU::serialize(os); 1502623SN/A} 1512623SN/A 1522623SN/Avoid 1532623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1542623SN/A{ 1552915Sktlim@umich.edu SimObject::State so_state; 1562915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1572623SN/A BaseSimpleCPU::unserialize(cp, section); 1582798Sktlim@umich.edu} 1592798Sktlim@umich.edu 1602901Ssaidi@eecs.umich.eduunsigned int 1612839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1622798Sktlim@umich.edu{ 1632839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1642798Sktlim@umich.edu // an access to complete. 1655496Ssaidi@eecs.umich.edu if (_status == Idle || _status == Running || _status == SwitchedOut) { 1662901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1672901Ssaidi@eecs.umich.edu return 0; 1682798Sktlim@umich.edu } else { 1692839Sktlim@umich.edu changeState(SimObject::Draining); 1702839Sktlim@umich.edu drainEvent = drain_event; 1712901Ssaidi@eecs.umich.edu return 1; 1722798Sktlim@umich.edu } 1732623SN/A} 1742623SN/A 1752623SN/Avoid 1762798Sktlim@umich.eduTimingSimpleCPU::resume() 1772623SN/A{ 1785221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1792798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1804762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1813201Shsul@eecs.umich.edu 1825710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1835710Scws3k@cs.virginia.edu deschedule(fetchEvent); 1842915Sktlim@umich.edu 1855710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1862623SN/A } 1872798Sktlim@umich.edu 1882901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1892798Sktlim@umich.edu} 1902798Sktlim@umich.edu 1912798Sktlim@umich.eduvoid 1922798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1932798Sktlim@umich.edu{ 1945496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 1952798Sktlim@umich.edu _status = SwitchedOut; 1967823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 1972867Sktlim@umich.edu 1982867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1992867Sktlim@umich.edu // we'll need to cancel it. 2005710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 2015606Snate@binkert.org deschedule(fetchEvent); 2022623SN/A} 2032623SN/A 2042623SN/A 2052623SN/Avoid 2062623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2072623SN/A{ 2084192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 2092623SN/A 2102680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 2112623SN/A // running and schedule its tick event. 2122680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2132680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2142680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2152623SN/A _status = Running; 2162623SN/A break; 2172623SN/A } 2182623SN/A } 2193201Shsul@eecs.umich.edu 2203201Shsul@eecs.umich.edu if (_status != Running) { 2213201Shsul@eecs.umich.edu _status = Idle; 2223201Shsul@eecs.umich.edu } 2235169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2247823Ssteve.reinhardt@amd.com previousTick = curTick(); 2252623SN/A} 2262623SN/A 2272623SN/A 2282623SN/Avoid 2292623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2302623SN/A{ 2315221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2325221Ssaidi@eecs.umich.edu 2332623SN/A assert(thread_num == 0); 2342683Sktlim@umich.edu assert(thread); 2352623SN/A 2362623SN/A assert(_status == Idle); 2372623SN/A 2382623SN/A notIdleFraction++; 2392623SN/A _status = Running; 2403686Sktlim@umich.edu 2412623SN/A // kick things off by initiating the fetch of the next instruction 2427823Ssteve.reinhardt@amd.com schedule(fetchEvent, nextCycle(curTick() + ticks(delay))); 2432623SN/A} 2442623SN/A 2452623SN/A 2462623SN/Avoid 2472623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2482623SN/A{ 2495221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2505221Ssaidi@eecs.umich.edu 2512623SN/A assert(thread_num == 0); 2522683Sktlim@umich.edu assert(thread); 2532623SN/A 2546043Sgblack@eecs.umich.edu if (_status == Idle) 2556043Sgblack@eecs.umich.edu return; 2566043Sgblack@eecs.umich.edu 2572644Sstever@eecs.umich.edu assert(_status == Running); 2582623SN/A 2592644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2602644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2612623SN/A 2622623SN/A notIdleFraction--; 2632623SN/A _status = Idle; 2642623SN/A} 2652623SN/A 2665728Sgblack@eecs.umich.edubool 2675728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2685728Sgblack@eecs.umich.edu{ 2695728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 2708105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2715728Sgblack@eecs.umich.edu Tick delay; 2725728Sgblack@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2737823Ssteve.reinhardt@amd.com new IprEvent(pkt, this, nextCycle(curTick() + delay)); 2745728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2755728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2765728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(pkt)) { 2775728Sgblack@eecs.umich.edu _status = DcacheRetry; 2785728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2795728Sgblack@eecs.umich.edu } else { 2805728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2815728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2825728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2835728Sgblack@eecs.umich.edu } 2845728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2855728Sgblack@eecs.umich.edu} 2862623SN/A 2875894Sgblack@eecs.umich.eduvoid 2886973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2896973Stjones1@inf.ed.ac.uk bool read) 2905744Sgblack@eecs.umich.edu{ 2915894Sgblack@eecs.umich.edu PacketPtr pkt; 2925894Sgblack@eecs.umich.edu buildPacket(pkt, req, read); 2937691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 2945894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2955894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2965894Sgblack@eecs.umich.edu pkt->makeResponse(); 2975894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2985894Sgblack@eecs.umich.edu } else if (read) { 2995894Sgblack@eecs.umich.edu handleReadPacket(pkt); 3005894Sgblack@eecs.umich.edu } else { 3015894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3025894Sgblack@eecs.umich.edu 3036102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3045894Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3055894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 3065894Sgblack@eecs.umich.edu assert(res); 3075894Sgblack@eecs.umich.edu req->setExtraData(*res); 3085894Sgblack@eecs.umich.edu } 3095894Sgblack@eecs.umich.edu 3105894Sgblack@eecs.umich.edu if (do_access) { 3115894Sgblack@eecs.umich.edu dcache_pkt = pkt; 3125894Sgblack@eecs.umich.edu handleWritePacket(); 3135894Sgblack@eecs.umich.edu } else { 3145894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 3155894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3165894Sgblack@eecs.umich.edu } 3175894Sgblack@eecs.umich.edu } 3185894Sgblack@eecs.umich.edu} 3195894Sgblack@eecs.umich.edu 3205894Sgblack@eecs.umich.eduvoid 3216973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 3226973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 3235894Sgblack@eecs.umich.edu{ 3245894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3255894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3265894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3275894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3285894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3295894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3305894Sgblack@eecs.umich.edu } else if (read) { 3317911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3327911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3335894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3345894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3357911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3367911Shestness@cs.utexas.edu pkt2->senderState); 3375894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3385894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3395894Sgblack@eecs.umich.edu } 3405894Sgblack@eecs.umich.edu } 3415894Sgblack@eecs.umich.edu } else { 3425894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3437911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3447911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3455894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3465894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3475894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3487911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3497911Shestness@cs.utexas.edu pkt2->senderState); 3505894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3515894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3525894Sgblack@eecs.umich.edu } 3535894Sgblack@eecs.umich.edu } 3545894Sgblack@eecs.umich.edu } 3555894Sgblack@eecs.umich.edu} 3565894Sgblack@eecs.umich.edu 3575894Sgblack@eecs.umich.eduvoid 3585894Sgblack@eecs.umich.eduTimingSimpleCPU::translationFault(Fault fault) 3595894Sgblack@eecs.umich.edu{ 3606739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3616739Sgblack@eecs.umich.edu // for instance prefetches. 3627823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 3637823Ssteve.reinhardt@amd.com previousTick = curTick(); 3645894Sgblack@eecs.umich.edu 3655894Sgblack@eecs.umich.edu if (traceData) { 3665894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3675894Sgblack@eecs.umich.edu delete traceData; 3685894Sgblack@eecs.umich.edu traceData = NULL; 3695744Sgblack@eecs.umich.edu } 3705744Sgblack@eecs.umich.edu 3715894Sgblack@eecs.umich.edu postExecute(); 3725894Sgblack@eecs.umich.edu 3735894Sgblack@eecs.umich.edu if (getState() == SimObject::Draining) { 3745894Sgblack@eecs.umich.edu advancePC(fault); 3755894Sgblack@eecs.umich.edu completeDrain(); 3765894Sgblack@eecs.umich.edu } else { 3775894Sgblack@eecs.umich.edu advanceInst(fault); 3785894Sgblack@eecs.umich.edu } 3795894Sgblack@eecs.umich.edu} 3805894Sgblack@eecs.umich.edu 3815894Sgblack@eecs.umich.eduvoid 3825894Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 3835894Sgblack@eecs.umich.edu{ 3845894Sgblack@eecs.umich.edu MemCmd cmd; 3855894Sgblack@eecs.umich.edu if (read) { 3865894Sgblack@eecs.umich.edu cmd = MemCmd::ReadReq; 3876102Sgblack@eecs.umich.edu if (req->isLLSC()) 3885894Sgblack@eecs.umich.edu cmd = MemCmd::LoadLockedReq; 3895894Sgblack@eecs.umich.edu } else { 3905894Sgblack@eecs.umich.edu cmd = MemCmd::WriteReq; 3916102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3925894Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3935894Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3945894Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3955894Sgblack@eecs.umich.edu } 3965894Sgblack@eecs.umich.edu } 3975894Sgblack@eecs.umich.edu pkt = new Packet(req, cmd, Packet::Broadcast); 3985894Sgblack@eecs.umich.edu} 3995894Sgblack@eecs.umich.edu 4005894Sgblack@eecs.umich.eduvoid 4015894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 4025894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 4035894Sgblack@eecs.umich.edu uint8_t *data, bool read) 4045894Sgblack@eecs.umich.edu{ 4055894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 4065894Sgblack@eecs.umich.edu 4078105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 4085744Sgblack@eecs.umich.edu 4095894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 4105894Sgblack@eecs.umich.edu buildPacket(pkt1, req, read); 4115894Sgblack@eecs.umich.edu return; 4125894Sgblack@eecs.umich.edu } 4135894Sgblack@eecs.umich.edu 4145894Sgblack@eecs.umich.edu buildPacket(pkt1, req1, read); 4155894Sgblack@eecs.umich.edu buildPacket(pkt2, req2, read); 4165894Sgblack@eecs.umich.edu 4175744Sgblack@eecs.umich.edu req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags()); 4185744Sgblack@eecs.umich.edu PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(), 4195744Sgblack@eecs.umich.edu Packet::Broadcast); 4205744Sgblack@eecs.umich.edu 4217691SAli.Saidi@ARM.com pkt->dataDynamicArray<uint8_t>(data); 4225744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 4235744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 4245744Sgblack@eecs.umich.edu 4255744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 4265744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 4275744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 4285744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 4295744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 4305744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 4315744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 4325744Sgblack@eecs.umich.edu} 4335744Sgblack@eecs.umich.edu 4342623SN/AFault 4357520Sgblack@eecs.umich.eduTimingSimpleCPU::readBytes(Addr addr, uint8_t *data, 4367520Sgblack@eecs.umich.edu unsigned size, unsigned flags) 4372623SN/A{ 4385728Sgblack@eecs.umich.edu Fault fault; 4395728Sgblack@eecs.umich.edu const int asid = 0; 4406221Snate@binkert.org const ThreadID tid = 0; 4417720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4426227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 4436973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4442623SN/A 4457045Ssteve.reinhardt@amd.com if (traceData) { 4467045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4477045Ssteve.reinhardt@amd.com } 4487045Ssteve.reinhardt@amd.com 4497520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4506221Snate@binkert.org flags, pc, _cpuId, tid); 4515728Sgblack@eecs.umich.edu 4527520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4535744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4545728Sgblack@eecs.umich.edu 4555894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4565744Sgblack@eecs.umich.edu if (split_addr > addr) { 4575894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4586102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4595894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4605894Sgblack@eecs.umich.edu 4616973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4627520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4636973Stjones1@inf.ed.ac.uk NULL, mode); 4646973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *trans1 = 4656973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state, 0); 4666973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *trans2 = 4676973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state, 1); 4686973Stjones1@inf.ed.ac.uk 4696973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 4706973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 4715744Sgblack@eecs.umich.edu } else { 4726973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4737520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4746973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *translation 4756973Stjones1@inf.ed.ac.uk = new DataTranslation<TimingSimpleCPU>(this, state); 4766973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 4772623SN/A } 4782623SN/A 4795728Sgblack@eecs.umich.edu return NoFault; 4802623SN/A} 4812623SN/A 4825728Sgblack@eecs.umich.edubool 4835728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4845728Sgblack@eecs.umich.edu{ 4855728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4868105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4875728Sgblack@eecs.umich.edu Tick delay; 4885728Sgblack@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4897823Ssteve.reinhardt@amd.com new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay)); 4905728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4915728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4925728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(dcache_pkt)) { 4935728Sgblack@eecs.umich.edu _status = DcacheRetry; 4945728Sgblack@eecs.umich.edu } else { 4955728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4965728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4975728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4985728Sgblack@eecs.umich.edu } 4995728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 5005728Sgblack@eecs.umich.edu} 5012623SN/A 5022623SN/AFault 5038443Sgblack@eecs.umich.eduTimingSimpleCPU::writeBytes(uint8_t *data, unsigned size, 5048443Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 5052623SN/A{ 5068443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 5078443Sgblack@eecs.umich.edu memcpy(newData, data, size); 5088443Sgblack@eecs.umich.edu 5095728Sgblack@eecs.umich.edu const int asid = 0; 5106221Snate@binkert.org const ThreadID tid = 0; 5117720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 5126227Snate@binkert.org unsigned block_size = dcachePort.peerBlockSize(); 5136973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 5143169Sstever@eecs.umich.edu 5157045Ssteve.reinhardt@amd.com if (traceData) { 5167045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 5177045Ssteve.reinhardt@amd.com } 5187045Ssteve.reinhardt@amd.com 5197520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 5206221Snate@binkert.org flags, pc, _cpuId, tid); 5215728Sgblack@eecs.umich.edu 5227520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 5235744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 5245728Sgblack@eecs.umich.edu 5255894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 5265744Sgblack@eecs.umich.edu if (split_addr > addr) { 5275894Sgblack@eecs.umich.edu RequestPtr req1, req2; 5286102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 5295894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5305894Sgblack@eecs.umich.edu 5316973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5328443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 5336973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *trans1 = 5346973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state, 0); 5356973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *trans2 = 5366973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state, 1); 5376973Stjones1@inf.ed.ac.uk 5386973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 5396973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 5405744Sgblack@eecs.umich.edu } else { 5416973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5428443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5436973Stjones1@inf.ed.ac.uk DataTranslation<TimingSimpleCPU> *translation = 5446973Stjones1@inf.ed.ac.uk new DataTranslation<TimingSimpleCPU>(this, state); 5456973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 5462623SN/A } 5472623SN/A 5487045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5495728Sgblack@eecs.umich.edu return NoFault; 5502623SN/A} 5512623SN/A 5522623SN/A 5532623SN/Avoid 5546973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5556973Stjones1@inf.ed.ac.uk{ 5566973Stjones1@inf.ed.ac.uk _status = Running; 5576973Stjones1@inf.ed.ac.uk 5586973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 5596973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 5606973Stjones1@inf.ed.ac.uk state->setNoFault(); 5616973Stjones1@inf.ed.ac.uk } 5627691SAli.Saidi@ARM.com delete [] state->data; 5636973Stjones1@inf.ed.ac.uk state->deleteReqs(); 5646973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 5656973Stjones1@inf.ed.ac.uk } else { 5666973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 5676973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 5686973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 5696973Stjones1@inf.ed.ac.uk } else { 5706973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5716973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 5726973Stjones1@inf.ed.ac.uk } 5736973Stjones1@inf.ed.ac.uk } 5746973Stjones1@inf.ed.ac.uk 5756973Stjones1@inf.ed.ac.uk delete state; 5766973Stjones1@inf.ed.ac.uk} 5776973Stjones1@inf.ed.ac.uk 5786973Stjones1@inf.ed.ac.uk 5796973Stjones1@inf.ed.ac.ukvoid 5802623SN/ATimingSimpleCPU::fetch() 5812623SN/A{ 5825221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5835221Ssaidi@eecs.umich.edu 5843387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5853387Sgblack@eecs.umich.edu checkForInterrupts(); 5862631SN/A 5875348Ssaidi@eecs.umich.edu checkPcEventQueue(); 5885348Ssaidi@eecs.umich.edu 5898143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5908143SAli.Saidi@ARM.com if (_status == Idle) 5918143SAli.Saidi@ARM.com return; 5928143SAli.Saidi@ARM.com 5937720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5947720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 5952623SN/A 5967720Sgblack@eecs.umich.edu if (needToFetch) { 5978276SAli.Saidi@ARM.com _status = Running; 5985669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 5995712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 6005894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 6018277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 6026023Snate@binkert.org thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 6036023Snate@binkert.org BaseTLB::Execute); 6042623SN/A } else { 6055669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6065669Sgblack@eecs.umich.edu completeIfetch(NULL); 6075894Sgblack@eecs.umich.edu 6087823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 6097823Ssteve.reinhardt@amd.com previousTick = curTick(); 6105894Sgblack@eecs.umich.edu } 6115894Sgblack@eecs.umich.edu} 6125894Sgblack@eecs.umich.edu 6135894Sgblack@eecs.umich.edu 6145894Sgblack@eecs.umich.eduvoid 6155894Sgblack@eecs.umich.eduTimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc) 6165894Sgblack@eecs.umich.edu{ 6175894Sgblack@eecs.umich.edu if (fault == NoFault) { 6188277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 6198277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 6205894Sgblack@eecs.umich.edu ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 6215894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 6228277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 6235894Sgblack@eecs.umich.edu 6245894Sgblack@eecs.umich.edu if (!icachePort.sendTiming(ifetch_pkt)) { 6255894Sgblack@eecs.umich.edu // Need to wait for retry 6265894Sgblack@eecs.umich.edu _status = IcacheRetry; 6275894Sgblack@eecs.umich.edu } else { 6285894Sgblack@eecs.umich.edu // Need to wait for cache to respond 6295894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6305894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 6315894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 6325894Sgblack@eecs.umich.edu } 6335894Sgblack@eecs.umich.edu } else { 6348277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 6355894Sgblack@eecs.umich.edu delete req; 6365894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 6377945SAli.Saidi@ARM.com _status = Running; 6385894Sgblack@eecs.umich.edu advanceInst(fault); 6392623SN/A } 6403222Sktlim@umich.edu 6417823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 6427823Ssteve.reinhardt@amd.com previousTick = curTick(); 6432623SN/A} 6442623SN/A 6452623SN/A 6462623SN/Avoid 6472644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 6482623SN/A{ 6498276SAli.Saidi@ARM.com 6508276SAli.Saidi@ARM.com if (_status == Faulting) 6518276SAli.Saidi@ARM.com return; 6528276SAli.Saidi@ARM.com 6538276SAli.Saidi@ARM.com if (fault != NoFault) { 6548276SAli.Saidi@ARM.com advancePC(fault); 6558276SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 6568276SAli.Saidi@ARM.com reschedule(fetchEvent, nextCycle(), true); 6578276SAli.Saidi@ARM.com _status = Faulting; 6588276SAli.Saidi@ARM.com return; 6598276SAli.Saidi@ARM.com } 6608276SAli.Saidi@ARM.com 6618276SAli.Saidi@ARM.com 6628276SAli.Saidi@ARM.com if (!stayAtPC) 6635726Sgblack@eecs.umich.edu advancePC(fault); 6642623SN/A 6652631SN/A if (_status == Running) { 6662631SN/A // kick off fetch of next instruction... callback from icache 6672631SN/A // response will cause that instruction to be executed, 6682631SN/A // keeping the CPU running. 6692631SN/A fetch(); 6702631SN/A } 6712623SN/A} 6722623SN/A 6732623SN/A 6742623SN/Avoid 6753349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 6762623SN/A{ 6778277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 6788277SAli.Saidi@ARM.com pkt->getAddr() : 0); 6798277SAli.Saidi@ARM.com 6802623SN/A // received a response from the icache: execute the received 6812623SN/A // instruction 6825669Sgblack@eecs.umich.edu 6835669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 6842623SN/A assert(_status == IcacheWaitResponse); 6852798Sktlim@umich.edu 6862623SN/A _status = Running; 6872644Sstever@eecs.umich.edu 6887823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 6897823Ssteve.reinhardt@amd.com previousTick = curTick(); 6903222Sktlim@umich.edu 6912839Sktlim@umich.edu if (getState() == SimObject::Draining) { 6925669Sgblack@eecs.umich.edu if (pkt) { 6935669Sgblack@eecs.umich.edu delete pkt->req; 6945669Sgblack@eecs.umich.edu delete pkt; 6955669Sgblack@eecs.umich.edu } 6963658Sktlim@umich.edu 6972839Sktlim@umich.edu completeDrain(); 6982798Sktlim@umich.edu return; 6992798Sktlim@umich.edu } 7002798Sktlim@umich.edu 7012623SN/A preExecute(); 7027725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 7032623SN/A // load or store: just send to dcache 7042623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 7057945SAli.Saidi@ARM.com 7067945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 7077945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 7087945SAli.Saidi@ARM.com // ifetch 7097945SAli.Saidi@ARM.com if (_status == Running) { 7105894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 7115001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7125001Sgblack@eecs.umich.edu delete traceData; 7135001Sgblack@eecs.umich.edu traceData = NULL; 7143170Sstever@eecs.umich.edu } 7154998Sgblack@eecs.umich.edu 7162644Sstever@eecs.umich.edu postExecute(); 7175103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7185103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7195103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7205103Ssaidi@eecs.umich.edu instCnt++; 7212644Sstever@eecs.umich.edu advanceInst(fault); 7222644Sstever@eecs.umich.edu } 7235726Sgblack@eecs.umich.edu } else if (curStaticInst) { 7242623SN/A // non-memory instruction: execute completely now 7252623SN/A Fault fault = curStaticInst->execute(this, traceData); 7264998Sgblack@eecs.umich.edu 7274998Sgblack@eecs.umich.edu // keep an instruction count 7284998Sgblack@eecs.umich.edu if (fault == NoFault) 7294998Sgblack@eecs.umich.edu countInst(); 7307655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 7315001Sgblack@eecs.umich.edu delete traceData; 7325001Sgblack@eecs.umich.edu traceData = NULL; 7335001Sgblack@eecs.umich.edu } 7344998Sgblack@eecs.umich.edu 7352644Sstever@eecs.umich.edu postExecute(); 7365103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7375103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7385103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7395103Ssaidi@eecs.umich.edu instCnt++; 7402644Sstever@eecs.umich.edu advanceInst(fault); 7415726Sgblack@eecs.umich.edu } else { 7425726Sgblack@eecs.umich.edu advanceInst(NoFault); 7432623SN/A } 7443658Sktlim@umich.edu 7455669Sgblack@eecs.umich.edu if (pkt) { 7465669Sgblack@eecs.umich.edu delete pkt->req; 7475669Sgblack@eecs.umich.edu delete pkt; 7485669Sgblack@eecs.umich.edu } 7492623SN/A} 7502623SN/A 7512948Ssaidi@eecs.umich.eduvoid 7522948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7532948Ssaidi@eecs.umich.edu{ 7542948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7552948Ssaidi@eecs.umich.edu} 7562623SN/A 7572623SN/Abool 7583349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 7592623SN/A{ 7604986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 7618277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); 7623310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 7637823Ssteve.reinhardt@amd.com Tick next_tick = cpu->nextCycle(curTick()); 7642948Ssaidi@eecs.umich.edu 7657823Ssteve.reinhardt@amd.com if (next_tick == curTick()) 7663310Srdreslin@umich.edu cpu->completeIfetch(pkt); 7673310Srdreslin@umich.edu else 7683495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 7692948Ssaidi@eecs.umich.edu 7703310Srdreslin@umich.edu return true; 7718276SAli.Saidi@ARM.com } else if (pkt->wasNacked()) { 7724433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 7734433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 7744433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 7754433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 7764433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 7774433Ssaidi@eecs.umich.edu } 7783310Srdreslin@umich.edu } 7794433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 7804433Ssaidi@eecs.umich.edu return true; 7812623SN/A} 7822623SN/A 7832657Ssaidi@eecs.umich.eduvoid 7842623SN/ATimingSimpleCPU::IcachePort::recvRetry() 7852623SN/A{ 7862623SN/A // we shouldn't get a retry unless we have a packet that we're 7872623SN/A // waiting to transmit 7882623SN/A assert(cpu->ifetch_pkt != NULL); 7892623SN/A assert(cpu->_status == IcacheRetry); 7903349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7912657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 7922657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7932657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7942657Ssaidi@eecs.umich.edu } 7952623SN/A} 7962623SN/A 7972623SN/Avoid 7983349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 7992623SN/A{ 8002623SN/A // received a response from the dcache: complete the load or store 8012623SN/A // instruction 8024870Sstever@eecs.umich.edu assert(!pkt->isError()); 8037516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 8047516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 8052623SN/A 8067823Ssteve.reinhardt@amd.com numCycles += tickToCycles(curTick() - previousTick); 8077823Ssteve.reinhardt@amd.com previousTick = curTick(); 8083184Srdreslin@umich.edu 8095728Sgblack@eecs.umich.edu if (pkt->senderState) { 8105728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8115728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 8125728Sgblack@eecs.umich.edu assert(send_state); 8135728Sgblack@eecs.umich.edu delete pkt->req; 8145728Sgblack@eecs.umich.edu delete pkt; 8155728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8165728Sgblack@eecs.umich.edu delete send_state; 8175728Sgblack@eecs.umich.edu 8185728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8195728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8205728Sgblack@eecs.umich.edu assert(main_send_state); 8215728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 8225728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 8235728Sgblack@eecs.umich.edu main_send_state->outstanding--; 8245728Sgblack@eecs.umich.edu 8255728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 8265728Sgblack@eecs.umich.edu return; 8275728Sgblack@eecs.umich.edu } else { 8285728Sgblack@eecs.umich.edu delete main_send_state; 8295728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 8305728Sgblack@eecs.umich.edu pkt = big_pkt; 8315728Sgblack@eecs.umich.edu } 8325728Sgblack@eecs.umich.edu } 8335728Sgblack@eecs.umich.edu 8345728Sgblack@eecs.umich.edu _status = Running; 8355728Sgblack@eecs.umich.edu 8362623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 8372623SN/A 8384998Sgblack@eecs.umich.edu // keep an instruction count 8394998Sgblack@eecs.umich.edu if (fault == NoFault) 8404998Sgblack@eecs.umich.edu countInst(); 8415001Sgblack@eecs.umich.edu else if (traceData) { 8425001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 8435001Sgblack@eecs.umich.edu delete traceData; 8445001Sgblack@eecs.umich.edu traceData = NULL; 8455001Sgblack@eecs.umich.edu } 8464998Sgblack@eecs.umich.edu 8475507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 8485507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 8496102Sgblack@eecs.umich.edu if (pkt->isRead() && pkt->req->isLLSC()) { 8503170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 8513170Sstever@eecs.umich.edu } 8523170Sstever@eecs.umich.edu 8532644Sstever@eecs.umich.edu delete pkt->req; 8542644Sstever@eecs.umich.edu delete pkt; 8552644Sstever@eecs.umich.edu 8563184Srdreslin@umich.edu postExecute(); 8573227Sktlim@umich.edu 8583201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 8593201Shsul@eecs.umich.edu advancePC(fault); 8603201Shsul@eecs.umich.edu completeDrain(); 8613201Shsul@eecs.umich.edu 8623201Shsul@eecs.umich.edu return; 8633201Shsul@eecs.umich.edu } 8643201Shsul@eecs.umich.edu 8652644Sstever@eecs.umich.edu advanceInst(fault); 8662623SN/A} 8672623SN/A 8682623SN/A 8692798Sktlim@umich.eduvoid 8702839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 8712798Sktlim@umich.edu{ 8722839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 8732901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 8742839Sktlim@umich.edu drainEvent->process(); 8752798Sktlim@umich.edu} 8762623SN/A 8774192Sktlim@umich.eduvoid 8784192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 8794192Sktlim@umich.edu{ 8804192Sktlim@umich.edu Port::setPeer(port); 8814192Sktlim@umich.edu 8824192Sktlim@umich.edu#if FULL_SYSTEM 8834192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 8844192Sktlim@umich.edu // Ports) 8855497Ssaidi@eecs.umich.edu cpu->tcBase()->connectMemPorts(cpu->tcBase()); 8864192Sktlim@umich.edu#endif 8874192Sktlim@umich.edu} 8884192Sktlim@umich.edu 8892623SN/Abool 8903349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 8912623SN/A{ 8924986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 8933310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 8947823Ssteve.reinhardt@amd.com Tick next_tick = cpu->nextCycle(curTick()); 8952948Ssaidi@eecs.umich.edu 8967823Ssteve.reinhardt@amd.com if (next_tick == curTick()) { 8973310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 8985728Sgblack@eecs.umich.edu } else { 8997745SAli.Saidi@ARM.com if (!tickEvent.scheduled()) { 9007745SAli.Saidi@ARM.com tickEvent.schedule(pkt, next_tick); 9017745SAli.Saidi@ARM.com } else { 9027745SAli.Saidi@ARM.com // In the case of a split transaction and a cache that is 9037745SAli.Saidi@ARM.com // faster than a CPU we could get two responses before 9047745SAli.Saidi@ARM.com // next_tick expires 9057745SAli.Saidi@ARM.com if (!retryEvent.scheduled()) 9067745SAli.Saidi@ARM.com schedule(retryEvent, next_tick); 9077745SAli.Saidi@ARM.com return false; 9087745SAli.Saidi@ARM.com } 9095728Sgblack@eecs.umich.edu } 9102948Ssaidi@eecs.umich.edu 9113310Srdreslin@umich.edu return true; 9123310Srdreslin@umich.edu } 9134870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 9144433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 9154433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 9164433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 9174433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 9184433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 9194433Ssaidi@eecs.umich.edu } 9203310Srdreslin@umich.edu } 9214433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 9224433Ssaidi@eecs.umich.edu return true; 9232948Ssaidi@eecs.umich.edu} 9242948Ssaidi@eecs.umich.edu 9252948Ssaidi@eecs.umich.eduvoid 9262948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 9272948Ssaidi@eecs.umich.edu{ 9282630SN/A cpu->completeDataAccess(pkt); 9292623SN/A} 9302623SN/A 9312657Ssaidi@eecs.umich.eduvoid 9322623SN/ATimingSimpleCPU::DcachePort::recvRetry() 9332623SN/A{ 9342623SN/A // we shouldn't get a retry unless we have a packet that we're 9352623SN/A // waiting to transmit 9362623SN/A assert(cpu->dcache_pkt != NULL); 9372623SN/A assert(cpu->_status == DcacheRetry); 9383349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 9395728Sgblack@eecs.umich.edu if (tmp->senderState) { 9405728Sgblack@eecs.umich.edu // This is a packet from a split access. 9415728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 9425728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 9435728Sgblack@eecs.umich.edu assert(send_state); 9445728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 9455728Sgblack@eecs.umich.edu 9465728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 9475728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 9485728Sgblack@eecs.umich.edu assert(main_send_state); 9495728Sgblack@eecs.umich.edu 9505728Sgblack@eecs.umich.edu if (sendTiming(tmp)) { 9515728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 9525728Sgblack@eecs.umich.edu // and try sending the other fragment. 9535728Sgblack@eecs.umich.edu send_state->clearFromParent(); 9545728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 9555728Sgblack@eecs.umich.edu if (other_index > 0) { 9565728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 9575728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 9585728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 9595728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 9605728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 9615728Sgblack@eecs.umich.edu } 9625728Sgblack@eecs.umich.edu } else { 9635728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9645728Sgblack@eecs.umich.edu // memory system takes ownership of packet 9655728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 9665728Sgblack@eecs.umich.edu } 9675728Sgblack@eecs.umich.edu } 9685728Sgblack@eecs.umich.edu } else if (sendTiming(tmp)) { 9692657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9703170Sstever@eecs.umich.edu // memory system takes ownership of packet 9712657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 9722657Ssaidi@eecs.umich.edu } 9732623SN/A} 9742623SN/A 9755606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 9765606Snate@binkert.org Tick t) 9775606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 9785103Ssaidi@eecs.umich.edu{ 9795606Snate@binkert.org cpu->schedule(this, t); 9805103Ssaidi@eecs.umich.edu} 9815103Ssaidi@eecs.umich.edu 9825103Ssaidi@eecs.umich.eduvoid 9835103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 9845103Ssaidi@eecs.umich.edu{ 9855103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 9865103Ssaidi@eecs.umich.edu} 9875103Ssaidi@eecs.umich.edu 9885103Ssaidi@eecs.umich.educonst char * 9895336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 9905103Ssaidi@eecs.umich.edu{ 9915103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 9925103Ssaidi@eecs.umich.edu} 9935103Ssaidi@eecs.umich.edu 9942623SN/A 9955315Sstever@gmail.comvoid 9965315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 9975315Sstever@gmail.com{ 9985315Sstever@gmail.com dcachePort.printAddr(a); 9995315Sstever@gmail.com} 10005315Sstever@gmail.com 10015315Sstever@gmail.com 10022623SN/A//////////////////////////////////////////////////////////////////////// 10032623SN/A// 10042623SN/A// TimingSimpleCPU Simulation Object 10052623SN/A// 10064762Snate@binkert.orgTimingSimpleCPU * 10074762Snate@binkert.orgTimingSimpleCPUParams::create() 10082623SN/A{ 10095529Snate@binkert.org numThreads = 1; 10105529Snate@binkert.org#if !FULL_SYSTEM 10114762Snate@binkert.org if (workload.size() != 1) 10124762Snate@binkert.org panic("only one workload allowed"); 10132623SN/A#endif 10145529Snate@binkert.org return new TimingSimpleCPU(this); 10152623SN/A} 1016