timing.cc revision 5890
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 325103Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh" 332623SN/A#include "arch/utility.hh" 344040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 352623SN/A#include "cpu/exetrace.hh" 362623SN/A#include "cpu/simple/timing.hh" 373348Sbinkertn@umich.edu#include "mem/packet.hh" 383348Sbinkertn@umich.edu#include "mem/packet_access.hh" 394762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 402901Ssaidi@eecs.umich.edu#include "sim/system.hh" 412623SN/A 422623SN/Ausing namespace std; 432623SN/Ausing namespace TheISA; 442623SN/A 452856Srdreslin@umich.eduPort * 462856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 472856Srdreslin@umich.edu{ 482856Srdreslin@umich.edu if (if_name == "dcache_port") 492856Srdreslin@umich.edu return &dcachePort; 502856Srdreslin@umich.edu else if (if_name == "icache_port") 512856Srdreslin@umich.edu return &icachePort; 522856Srdreslin@umich.edu else 532856Srdreslin@umich.edu panic("No Such Port\n"); 542856Srdreslin@umich.edu} 552623SN/A 562623SN/Avoid 572623SN/ATimingSimpleCPU::init() 582623SN/A{ 592623SN/A BaseCPU::init(); 602623SN/A#if FULL_SYSTEM 612680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 622680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 632623SN/A 642623SN/A // initialize CPU, including PC 655712Shsul@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 662623SN/A } 672623SN/A#endif 682623SN/A} 692623SN/A 702623SN/ATick 713349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 722623SN/A{ 732623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 742623SN/A return curTick; 752623SN/A} 762623SN/A 772623SN/Avoid 783349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 792623SN/A{ 803184Srdreslin@umich.edu //No internal storage to update, jusst return 813184Srdreslin@umich.edu return; 822623SN/A} 832623SN/A 842623SN/Avoid 852623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 862623SN/A{ 873647Srdreslin@umich.edu if (status == RangeChange) { 883647Srdreslin@umich.edu if (!snoopRangeSent) { 893647Srdreslin@umich.edu snoopRangeSent = true; 903647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 913647Srdreslin@umich.edu } 922631SN/A return; 933647Srdreslin@umich.edu } 942631SN/A 952623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 962623SN/A} 972623SN/A 982948Ssaidi@eecs.umich.edu 992948Ssaidi@eecs.umich.eduvoid 1003349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1012948Ssaidi@eecs.umich.edu{ 1022948Ssaidi@eecs.umich.edu pkt = _pkt; 1035606Snate@binkert.org cpu->schedule(this, t); 1042948Ssaidi@eecs.umich.edu} 1052948Ssaidi@eecs.umich.edu 1065529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 1075710Scws3k@cs.virginia.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), fetchEvent(this) 1082623SN/A{ 1092623SN/A _status = Idle; 1103647Srdreslin@umich.edu 1113647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1123647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1133647Srdreslin@umich.edu 1142623SN/A ifetch_pkt = dcache_pkt = NULL; 1152839Sktlim@umich.edu drainEvent = NULL; 1163222Sktlim@umich.edu previousTick = 0; 1172901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1182623SN/A} 1192623SN/A 1202623SN/A 1212623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1222623SN/A{ 1232623SN/A} 1242623SN/A 1252623SN/Avoid 1262623SN/ATimingSimpleCPU::serialize(ostream &os) 1272623SN/A{ 1282915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1292915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1302623SN/A BaseSimpleCPU::serialize(os); 1312623SN/A} 1322623SN/A 1332623SN/Avoid 1342623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1352623SN/A{ 1362915Sktlim@umich.edu SimObject::State so_state; 1372915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1382623SN/A BaseSimpleCPU::unserialize(cp, section); 1392798Sktlim@umich.edu} 1402798Sktlim@umich.edu 1412901Ssaidi@eecs.umich.eduunsigned int 1422839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1432798Sktlim@umich.edu{ 1442839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1452798Sktlim@umich.edu // an access to complete. 1465496Ssaidi@eecs.umich.edu if (_status == Idle || _status == Running || _status == SwitchedOut) { 1472901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1482901Ssaidi@eecs.umich.edu return 0; 1492798Sktlim@umich.edu } else { 1502839Sktlim@umich.edu changeState(SimObject::Draining); 1512839Sktlim@umich.edu drainEvent = drain_event; 1522901Ssaidi@eecs.umich.edu return 1; 1532798Sktlim@umich.edu } 1542623SN/A} 1552623SN/A 1562623SN/Avoid 1572798Sktlim@umich.eduTimingSimpleCPU::resume() 1582623SN/A{ 1595221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1602798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1614762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1623201Shsul@eecs.umich.edu 1635710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1645710Scws3k@cs.virginia.edu deschedule(fetchEvent); 1652915Sktlim@umich.edu 1665710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1672623SN/A } 1682798Sktlim@umich.edu 1692901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1702798Sktlim@umich.edu} 1712798Sktlim@umich.edu 1722798Sktlim@umich.eduvoid 1732798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1742798Sktlim@umich.edu{ 1755496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 1762798Sktlim@umich.edu _status = SwitchedOut; 1775099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 1782867Sktlim@umich.edu 1792867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1802867Sktlim@umich.edu // we'll need to cancel it. 1815710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1825606Snate@binkert.org deschedule(fetchEvent); 1832623SN/A} 1842623SN/A 1852623SN/A 1862623SN/Avoid 1872623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1882623SN/A{ 1894192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 1902623SN/A 1912680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1922623SN/A // running and schedule its tick event. 1932680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1942680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1952680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 1962623SN/A _status = Running; 1972623SN/A break; 1982623SN/A } 1992623SN/A } 2003201Shsul@eecs.umich.edu 2013201Shsul@eecs.umich.edu if (_status != Running) { 2023201Shsul@eecs.umich.edu _status = Idle; 2033201Shsul@eecs.umich.edu } 2045169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2055101Ssaidi@eecs.umich.edu previousTick = curTick; 2062623SN/A} 2072623SN/A 2082623SN/A 2092623SN/Avoid 2102623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2112623SN/A{ 2125221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2135221Ssaidi@eecs.umich.edu 2142623SN/A assert(thread_num == 0); 2152683Sktlim@umich.edu assert(thread); 2162623SN/A 2172623SN/A assert(_status == Idle); 2182623SN/A 2192623SN/A notIdleFraction++; 2202623SN/A _status = Running; 2213686Sktlim@umich.edu 2222623SN/A // kick things off by initiating the fetch of the next instruction 2235606Snate@binkert.org schedule(fetchEvent, nextCycle(curTick + ticks(delay))); 2242623SN/A} 2252623SN/A 2262623SN/A 2272623SN/Avoid 2282623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2292623SN/A{ 2305221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2315221Ssaidi@eecs.umich.edu 2322623SN/A assert(thread_num == 0); 2332683Sktlim@umich.edu assert(thread); 2342623SN/A 2352644Sstever@eecs.umich.edu assert(_status == Running); 2362623SN/A 2372644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2382644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2392623SN/A 2402623SN/A notIdleFraction--; 2412623SN/A _status = Idle; 2422623SN/A} 2432623SN/A 2445728Sgblack@eecs.umich.edubool 2455728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2465728Sgblack@eecs.umich.edu{ 2475728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 2485728Sgblack@eecs.umich.edu if (req->isMmapedIpr()) { 2495728Sgblack@eecs.umich.edu Tick delay; 2505728Sgblack@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2515728Sgblack@eecs.umich.edu new IprEvent(pkt, this, nextCycle(curTick + delay)); 2525728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2535728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2545728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(pkt)) { 2555728Sgblack@eecs.umich.edu _status = DcacheRetry; 2565728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2575728Sgblack@eecs.umich.edu } else { 2585728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2595728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2605728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2615728Sgblack@eecs.umich.edu } 2625728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2635728Sgblack@eecs.umich.edu} 2642623SN/A 2655744Sgblack@eecs.umich.eduFault 2665744Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 2675744Sgblack@eecs.umich.edu RequestPtr &req, Addr split_addr, uint8_t *data, bool read) 2685744Sgblack@eecs.umich.edu{ 2695744Sgblack@eecs.umich.edu Fault fault; 2705744Sgblack@eecs.umich.edu RequestPtr req1, req2; 2715744Sgblack@eecs.umich.edu assert(!req->isLocked() && !req->isSwap()); 2725744Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 2735744Sgblack@eecs.umich.edu 2745744Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 2755744Sgblack@eecs.umich.edu if ((fault = buildPacket(pkt1, req1, read)) != NoFault || 2765744Sgblack@eecs.umich.edu (fault = buildPacket(pkt2, req2, read)) != NoFault) { 2775744Sgblack@eecs.umich.edu delete req; 2785890Sgblack@eecs.umich.edu delete req1; 2795744Sgblack@eecs.umich.edu delete pkt1; 2805744Sgblack@eecs.umich.edu req = NULL; 2815744Sgblack@eecs.umich.edu pkt1 = NULL; 2825744Sgblack@eecs.umich.edu return fault; 2835744Sgblack@eecs.umich.edu } 2845744Sgblack@eecs.umich.edu 2855744Sgblack@eecs.umich.edu assert(!req1->isMmapedIpr() && !req2->isMmapedIpr()); 2865744Sgblack@eecs.umich.edu 2875744Sgblack@eecs.umich.edu req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags()); 2885744Sgblack@eecs.umich.edu PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(), 2895744Sgblack@eecs.umich.edu Packet::Broadcast); 2905890Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2915890Sgblack@eecs.umich.edu delete req1; 2925890Sgblack@eecs.umich.edu delete pkt1; 2935890Sgblack@eecs.umich.edu delete req2; 2945890Sgblack@eecs.umich.edu delete pkt2; 2955890Sgblack@eecs.umich.edu pkt1 = pkt; 2965890Sgblack@eecs.umich.edu pkt2 = NULL; 2975890Sgblack@eecs.umich.edu return NoFault; 2985890Sgblack@eecs.umich.edu } 2995744Sgblack@eecs.umich.edu 3005744Sgblack@eecs.umich.edu pkt->dataDynamic<uint8_t>(data); 3015744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 3025744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 3035744Sgblack@eecs.umich.edu 3045744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 3055744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 3065744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 3075744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 3085744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 3095744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 3105744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 3115744Sgblack@eecs.umich.edu return fault; 3125744Sgblack@eecs.umich.edu} 3135744Sgblack@eecs.umich.edu 3145744Sgblack@eecs.umich.eduFault 3155744Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr &req, bool read) 3165744Sgblack@eecs.umich.edu{ 3175890Sgblack@eecs.umich.edu Fault fault = thread->dtb->translate(req, tc, !read); 3185744Sgblack@eecs.umich.edu MemCmd cmd; 3195744Sgblack@eecs.umich.edu if (fault != NoFault) { 3205744Sgblack@eecs.umich.edu delete req; 3215744Sgblack@eecs.umich.edu req = NULL; 3225744Sgblack@eecs.umich.edu pkt = NULL; 3235744Sgblack@eecs.umich.edu return fault; 3245744Sgblack@eecs.umich.edu } else if (read) { 3255744Sgblack@eecs.umich.edu cmd = MemCmd::ReadReq; 3265744Sgblack@eecs.umich.edu if (req->isLocked()) 3275744Sgblack@eecs.umich.edu cmd = MemCmd::LoadLockedReq; 3285744Sgblack@eecs.umich.edu } else { 3295744Sgblack@eecs.umich.edu cmd = MemCmd::WriteReq; 3305744Sgblack@eecs.umich.edu if (req->isLocked()) { 3315744Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3325744Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3335744Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3345744Sgblack@eecs.umich.edu } 3355744Sgblack@eecs.umich.edu } 3365744Sgblack@eecs.umich.edu pkt = new Packet(req, cmd, Packet::Broadcast); 3375744Sgblack@eecs.umich.edu return NoFault; 3385744Sgblack@eecs.umich.edu} 3395744Sgblack@eecs.umich.edu 3402623SN/Atemplate <class T> 3412623SN/AFault 3422623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 3432623SN/A{ 3445728Sgblack@eecs.umich.edu Fault fault; 3455728Sgblack@eecs.umich.edu const int asid = 0; 3465728Sgblack@eecs.umich.edu const int thread_id = 0; 3475728Sgblack@eecs.umich.edu const Addr pc = thread->readPC(); 3485728Sgblack@eecs.umich.edu int block_size = dcachePort.peerBlockSize(); 3495728Sgblack@eecs.umich.edu int data_size = sizeof(T); 3502623SN/A 3515744Sgblack@eecs.umich.edu PacketPtr pkt; 3525744Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, data_size, 3535744Sgblack@eecs.umich.edu flags, pc, _cpuId, thread_id); 3545728Sgblack@eecs.umich.edu 3555744Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + data_size - 1, block_size); 3565744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 3575728Sgblack@eecs.umich.edu 3585744Sgblack@eecs.umich.edu if (split_addr > addr) { 3595744Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3605890Sgblack@eecs.umich.edu Fault fault = this->buildSplitPacket(pkt1, pkt2, req, 3615744Sgblack@eecs.umich.edu split_addr, (uint8_t *)(new T), true); 3625890Sgblack@eecs.umich.edu if (fault != NoFault) 3635890Sgblack@eecs.umich.edu return fault; 3645890Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3655890Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3665890Sgblack@eecs.umich.edu } else if (handleReadPacket(pkt1)) { 3675744Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 3685744Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3695744Sgblack@eecs.umich.edu send_state->clearFromParent(); 3705744Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3715744Sgblack@eecs.umich.edu send_state = 3725744Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3735744Sgblack@eecs.umich.edu send_state->clearFromParent(); 3745744Sgblack@eecs.umich.edu } 3755744Sgblack@eecs.umich.edu } 3765744Sgblack@eecs.umich.edu } else { 3775744Sgblack@eecs.umich.edu Fault fault = buildPacket(pkt, req, true); 3785728Sgblack@eecs.umich.edu if (fault != NoFault) { 3795728Sgblack@eecs.umich.edu return fault; 3805728Sgblack@eecs.umich.edu } 3815890Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3825890Sgblack@eecs.umich.edu dcache_pkt = pkt; 3835890Sgblack@eecs.umich.edu } else { 3845890Sgblack@eecs.umich.edu pkt->dataDynamic<T>(new T); 3855890Sgblack@eecs.umich.edu handleReadPacket(pkt); 3865890Sgblack@eecs.umich.edu } 3872623SN/A } 3882623SN/A 3895408Sgblack@eecs.umich.edu if (traceData) { 3905408Sgblack@eecs.umich.edu traceData->setData(data); 3915728Sgblack@eecs.umich.edu traceData->setAddr(addr); 3925408Sgblack@eecs.umich.edu } 3935728Sgblack@eecs.umich.edu 3945728Sgblack@eecs.umich.edu // This will need a new way to tell if it has a dcache attached. 3955728Sgblack@eecs.umich.edu if (req->isUncacheable()) 3965728Sgblack@eecs.umich.edu recordEvent("Uncached Read"); 3975728Sgblack@eecs.umich.edu 3985728Sgblack@eecs.umich.edu return NoFault; 3992623SN/A} 4002623SN/A 4012623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4022623SN/A 4032623SN/Atemplate 4042623SN/AFault 4054040Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 4064040Ssaidi@eecs.umich.edu 4074040Ssaidi@eecs.umich.edutemplate 4084040Ssaidi@eecs.umich.eduFault 4094115Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 4104115Ssaidi@eecs.umich.edu 4114115Ssaidi@eecs.umich.edutemplate 4124115Ssaidi@eecs.umich.eduFault 4132623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 4142623SN/A 4152623SN/Atemplate 4162623SN/AFault 4172623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 4182623SN/A 4192623SN/Atemplate 4202623SN/AFault 4212623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 4222623SN/A 4232623SN/Atemplate 4242623SN/AFault 4252623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 4262623SN/A 4272623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4282623SN/A 4292623SN/Atemplate<> 4302623SN/AFault 4312623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 4322623SN/A{ 4332623SN/A return read(addr, *(uint64_t*)&data, flags); 4342623SN/A} 4352623SN/A 4362623SN/Atemplate<> 4372623SN/AFault 4382623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 4392623SN/A{ 4402623SN/A return read(addr, *(uint32_t*)&data, flags); 4412623SN/A} 4422623SN/A 4432623SN/A 4442623SN/Atemplate<> 4452623SN/AFault 4462623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 4472623SN/A{ 4482623SN/A return read(addr, (uint32_t&)data, flags); 4492623SN/A} 4502623SN/A 4515728Sgblack@eecs.umich.edubool 4525728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4535728Sgblack@eecs.umich.edu{ 4545728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4555728Sgblack@eecs.umich.edu if (req->isMmapedIpr()) { 4565728Sgblack@eecs.umich.edu Tick delay; 4575728Sgblack@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4585728Sgblack@eecs.umich.edu new IprEvent(dcache_pkt, this, nextCycle(curTick + delay)); 4595728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4605728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4615728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(dcache_pkt)) { 4625728Sgblack@eecs.umich.edu _status = DcacheRetry; 4635728Sgblack@eecs.umich.edu } else { 4645728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4655728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4665728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4675728Sgblack@eecs.umich.edu } 4685728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4695728Sgblack@eecs.umich.edu} 4702623SN/A 4712623SN/Atemplate <class T> 4722623SN/AFault 4732623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 4742623SN/A{ 4755728Sgblack@eecs.umich.edu const int asid = 0; 4765728Sgblack@eecs.umich.edu const int thread_id = 0; 4775728Sgblack@eecs.umich.edu const Addr pc = thread->readPC(); 4785728Sgblack@eecs.umich.edu int block_size = dcachePort.peerBlockSize(); 4795728Sgblack@eecs.umich.edu int data_size = sizeof(T); 4803169Sstever@eecs.umich.edu 4815744Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, data_size, 4825744Sgblack@eecs.umich.edu flags, pc, _cpuId, thread_id); 4835728Sgblack@eecs.umich.edu 4845744Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + data_size - 1, block_size); 4855744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4865728Sgblack@eecs.umich.edu 4875744Sgblack@eecs.umich.edu if (split_addr > addr) { 4885744Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 4895744Sgblack@eecs.umich.edu T *dataP = new T; 4905744Sgblack@eecs.umich.edu *dataP = data; 4915744Sgblack@eecs.umich.edu Fault fault = this->buildSplitPacket(pkt1, pkt2, req, split_addr, 4925744Sgblack@eecs.umich.edu (uint8_t *)dataP, false); 4935744Sgblack@eecs.umich.edu if (fault != NoFault) 4945728Sgblack@eecs.umich.edu return fault; 4955744Sgblack@eecs.umich.edu dcache_pkt = pkt1; 4965890Sgblack@eecs.umich.edu if (!req->getFlags().isSet(Request::NO_ACCESS)) { 4975890Sgblack@eecs.umich.edu if (handleWritePacket()) { 4985890Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 4995890Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>( 5005890Sgblack@eecs.umich.edu pkt1->senderState); 5015744Sgblack@eecs.umich.edu send_state->clearFromParent(); 5025890Sgblack@eecs.umich.edu dcache_pkt = pkt2; 5035890Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 5045890Sgblack@eecs.umich.edu send_state = 5055890Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>( 5065890Sgblack@eecs.umich.edu pkt1->senderState); 5075890Sgblack@eecs.umich.edu send_state->clearFromParent(); 5085890Sgblack@eecs.umich.edu } 5095744Sgblack@eecs.umich.edu } 5105728Sgblack@eecs.umich.edu } 5115744Sgblack@eecs.umich.edu } else { 5125744Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 5135744Sgblack@eecs.umich.edu 5145744Sgblack@eecs.umich.edu Fault fault = buildPacket(dcache_pkt, req, false); 5155744Sgblack@eecs.umich.edu if (fault != NoFault) 5165728Sgblack@eecs.umich.edu return fault; 5175744Sgblack@eecs.umich.edu 5185890Sgblack@eecs.umich.edu if (!req->getFlags().isSet(Request::NO_ACCESS)) { 5195890Sgblack@eecs.umich.edu if (req->isLocked()) { 5205890Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 5215890Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 5225890Sgblack@eecs.umich.edu assert(res); 5235890Sgblack@eecs.umich.edu req->setExtraData(*res); 5245890Sgblack@eecs.umich.edu } 5255890Sgblack@eecs.umich.edu 5265890Sgblack@eecs.umich.edu dcache_pkt->allocate(); 5275890Sgblack@eecs.umich.edu if (req->isMmapedIpr()) 5285890Sgblack@eecs.umich.edu dcache_pkt->set(htog(data)); 5295890Sgblack@eecs.umich.edu else 5305890Sgblack@eecs.umich.edu dcache_pkt->set(data); 5315890Sgblack@eecs.umich.edu 5325890Sgblack@eecs.umich.edu if (do_access) 5335890Sgblack@eecs.umich.edu handleWritePacket(); 5345728Sgblack@eecs.umich.edu } 5352623SN/A } 5362623SN/A 5375408Sgblack@eecs.umich.edu if (traceData) { 5385728Sgblack@eecs.umich.edu traceData->setAddr(req->getVaddr()); 5395408Sgblack@eecs.umich.edu traceData->setData(data); 5405408Sgblack@eecs.umich.edu } 5412623SN/A 5425728Sgblack@eecs.umich.edu // This will need a new way to tell if it's hooked up to a cache or not. 5435728Sgblack@eecs.umich.edu if (req->isUncacheable()) 5445728Sgblack@eecs.umich.edu recordEvent("Uncached Write"); 5455728Sgblack@eecs.umich.edu 5462623SN/A // If the write needs to have a fault on the access, consider calling 5472623SN/A // changeStatus() and changing it to "bad addr write" or something. 5485728Sgblack@eecs.umich.edu return NoFault; 5492623SN/A} 5502623SN/A 5512623SN/A 5522623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 5532623SN/Atemplate 5542623SN/AFault 5554224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin32_t data, Addr addr, 5564224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 5574224Sgblack@eecs.umich.edu 5584224Sgblack@eecs.umich.edutemplate 5594224Sgblack@eecs.umich.eduFault 5604224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin64_t data, Addr addr, 5614224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 5624224Sgblack@eecs.umich.edu 5634224Sgblack@eecs.umich.edutemplate 5644224Sgblack@eecs.umich.eduFault 5652623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 5662623SN/A unsigned flags, uint64_t *res); 5672623SN/A 5682623SN/Atemplate 5692623SN/AFault 5702623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 5712623SN/A unsigned flags, uint64_t *res); 5722623SN/A 5732623SN/Atemplate 5742623SN/AFault 5752623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 5762623SN/A unsigned flags, uint64_t *res); 5772623SN/A 5782623SN/Atemplate 5792623SN/AFault 5802623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 5812623SN/A unsigned flags, uint64_t *res); 5822623SN/A 5832623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 5842623SN/A 5852623SN/Atemplate<> 5862623SN/AFault 5872623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 5882623SN/A{ 5892623SN/A return write(*(uint64_t*)&data, addr, flags, res); 5902623SN/A} 5912623SN/A 5922623SN/Atemplate<> 5932623SN/AFault 5942623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 5952623SN/A{ 5962623SN/A return write(*(uint32_t*)&data, addr, flags, res); 5972623SN/A} 5982623SN/A 5992623SN/A 6002623SN/Atemplate<> 6012623SN/AFault 6022623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 6032623SN/A{ 6042623SN/A return write((uint32_t)data, addr, flags, res); 6052623SN/A} 6062623SN/A 6072623SN/A 6082623SN/Avoid 6092623SN/ATimingSimpleCPU::fetch() 6102623SN/A{ 6115221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 6125221Ssaidi@eecs.umich.edu 6133387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 6143387Sgblack@eecs.umich.edu checkForInterrupts(); 6152631SN/A 6165348Ssaidi@eecs.umich.edu checkPcEventQueue(); 6175348Ssaidi@eecs.umich.edu 6185669Sgblack@eecs.umich.edu bool fromRom = isRomMicroPC(thread->readMicroPC()); 6192623SN/A 6205669Sgblack@eecs.umich.edu if (!fromRom) { 6215669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 6225712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 6235669Sgblack@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 6242623SN/A 6255669Sgblack@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast); 6265669Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 6275669Sgblack@eecs.umich.edu 6285669Sgblack@eecs.umich.edu if (fault == NoFault) { 6295669Sgblack@eecs.umich.edu if (!icachePort.sendTiming(ifetch_pkt)) { 6305669Sgblack@eecs.umich.edu // Need to wait for retry 6315669Sgblack@eecs.umich.edu _status = IcacheRetry; 6325669Sgblack@eecs.umich.edu } else { 6335669Sgblack@eecs.umich.edu // Need to wait for cache to respond 6345669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6355669Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 6365669Sgblack@eecs.umich.edu ifetch_pkt = NULL; 6375669Sgblack@eecs.umich.edu } 6382623SN/A } else { 6395669Sgblack@eecs.umich.edu delete ifetch_req; 6405669Sgblack@eecs.umich.edu delete ifetch_pkt; 6415669Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 6425669Sgblack@eecs.umich.edu advanceInst(fault); 6432623SN/A } 6442623SN/A } else { 6455669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6465669Sgblack@eecs.umich.edu completeIfetch(NULL); 6472623SN/A } 6483222Sktlim@umich.edu 6495099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 6503222Sktlim@umich.edu previousTick = curTick; 6512623SN/A} 6522623SN/A 6532623SN/A 6542623SN/Avoid 6552644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 6562623SN/A{ 6575726Sgblack@eecs.umich.edu if (fault != NoFault || !stayAtPC) 6585726Sgblack@eecs.umich.edu advancePC(fault); 6592623SN/A 6602631SN/A if (_status == Running) { 6612631SN/A // kick off fetch of next instruction... callback from icache 6622631SN/A // response will cause that instruction to be executed, 6632631SN/A // keeping the CPU running. 6642631SN/A fetch(); 6652631SN/A } 6662623SN/A} 6672623SN/A 6682623SN/A 6692623SN/Avoid 6703349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 6712623SN/A{ 6725221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Complete ICache Fetch\n"); 6735221Ssaidi@eecs.umich.edu 6742623SN/A // received a response from the icache: execute the received 6752623SN/A // instruction 6765669Sgblack@eecs.umich.edu 6775669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 6782623SN/A assert(_status == IcacheWaitResponse); 6792798Sktlim@umich.edu 6802623SN/A _status = Running; 6812644Sstever@eecs.umich.edu 6825099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 6833222Sktlim@umich.edu previousTick = curTick; 6843222Sktlim@umich.edu 6852839Sktlim@umich.edu if (getState() == SimObject::Draining) { 6865669Sgblack@eecs.umich.edu if (pkt) { 6875669Sgblack@eecs.umich.edu delete pkt->req; 6885669Sgblack@eecs.umich.edu delete pkt; 6895669Sgblack@eecs.umich.edu } 6903658Sktlim@umich.edu 6912839Sktlim@umich.edu completeDrain(); 6922798Sktlim@umich.edu return; 6932798Sktlim@umich.edu } 6942798Sktlim@umich.edu 6952623SN/A preExecute(); 6965726Sgblack@eecs.umich.edu if (curStaticInst && 6975726Sgblack@eecs.umich.edu curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 6982623SN/A // load or store: just send to dcache 6992623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 7003170Sstever@eecs.umich.edu if (_status != Running) { 7013170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 7023170Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DcacheRetry); 7033170Sstever@eecs.umich.edu assert(fault == NoFault); 7042644Sstever@eecs.umich.edu } else { 7053170Sstever@eecs.umich.edu if (fault == NoFault) { 7065335Shines@cs.fsu.edu // Note that ARM can have NULL packets if the instruction gets 7075335Shines@cs.fsu.edu // squashed due to predication 7083170Sstever@eecs.umich.edu // early fail on store conditional: complete now 7095335Shines@cs.fsu.edu assert(dcache_pkt != NULL || THE_ISA == ARM_ISA); 7105335Shines@cs.fsu.edu 7113170Sstever@eecs.umich.edu fault = curStaticInst->completeAcc(dcache_pkt, this, 7123170Sstever@eecs.umich.edu traceData); 7135335Shines@cs.fsu.edu if (dcache_pkt != NULL) 7145335Shines@cs.fsu.edu { 7155335Shines@cs.fsu.edu delete dcache_pkt->req; 7165335Shines@cs.fsu.edu delete dcache_pkt; 7175335Shines@cs.fsu.edu dcache_pkt = NULL; 7185335Shines@cs.fsu.edu } 7194998Sgblack@eecs.umich.edu 7204998Sgblack@eecs.umich.edu // keep an instruction count 7214998Sgblack@eecs.umich.edu if (fault == NoFault) 7224998Sgblack@eecs.umich.edu countInst(); 7235001Sgblack@eecs.umich.edu } else if (traceData) { 7245001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7255001Sgblack@eecs.umich.edu delete traceData; 7265001Sgblack@eecs.umich.edu traceData = NULL; 7273170Sstever@eecs.umich.edu } 7284998Sgblack@eecs.umich.edu 7292644Sstever@eecs.umich.edu postExecute(); 7305103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7315103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7325103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7335103Ssaidi@eecs.umich.edu instCnt++; 7342644Sstever@eecs.umich.edu advanceInst(fault); 7352644Sstever@eecs.umich.edu } 7365726Sgblack@eecs.umich.edu } else if (curStaticInst) { 7372623SN/A // non-memory instruction: execute completely now 7382623SN/A Fault fault = curStaticInst->execute(this, traceData); 7394998Sgblack@eecs.umich.edu 7404998Sgblack@eecs.umich.edu // keep an instruction count 7414998Sgblack@eecs.umich.edu if (fault == NoFault) 7424998Sgblack@eecs.umich.edu countInst(); 7435001Sgblack@eecs.umich.edu else if (traceData) { 7445001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7455001Sgblack@eecs.umich.edu delete traceData; 7465001Sgblack@eecs.umich.edu traceData = NULL; 7475001Sgblack@eecs.umich.edu } 7484998Sgblack@eecs.umich.edu 7492644Sstever@eecs.umich.edu postExecute(); 7505103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7515103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7525103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7535103Ssaidi@eecs.umich.edu instCnt++; 7542644Sstever@eecs.umich.edu advanceInst(fault); 7555726Sgblack@eecs.umich.edu } else { 7565726Sgblack@eecs.umich.edu advanceInst(NoFault); 7572623SN/A } 7583658Sktlim@umich.edu 7595669Sgblack@eecs.umich.edu if (pkt) { 7605669Sgblack@eecs.umich.edu delete pkt->req; 7615669Sgblack@eecs.umich.edu delete pkt; 7625669Sgblack@eecs.umich.edu } 7632623SN/A} 7642623SN/A 7652948Ssaidi@eecs.umich.eduvoid 7662948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7672948Ssaidi@eecs.umich.edu{ 7682948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7692948Ssaidi@eecs.umich.edu} 7702623SN/A 7712623SN/Abool 7723349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 7732623SN/A{ 7744986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 7753310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 7764584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 7772948Ssaidi@eecs.umich.edu 7783495Sktlim@umich.edu if (next_tick == curTick) 7793310Srdreslin@umich.edu cpu->completeIfetch(pkt); 7803310Srdreslin@umich.edu else 7813495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 7822948Ssaidi@eecs.umich.edu 7833310Srdreslin@umich.edu return true; 7843310Srdreslin@umich.edu } 7854870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 7864433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 7874433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 7884433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 7894433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 7904433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 7914433Ssaidi@eecs.umich.edu } 7923310Srdreslin@umich.edu } 7934433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 7944433Ssaidi@eecs.umich.edu return true; 7952623SN/A} 7962623SN/A 7972657Ssaidi@eecs.umich.eduvoid 7982623SN/ATimingSimpleCPU::IcachePort::recvRetry() 7992623SN/A{ 8002623SN/A // we shouldn't get a retry unless we have a packet that we're 8012623SN/A // waiting to transmit 8022623SN/A assert(cpu->ifetch_pkt != NULL); 8032623SN/A assert(cpu->_status == IcacheRetry); 8043349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 8052657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 8062657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 8072657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 8082657Ssaidi@eecs.umich.edu } 8092623SN/A} 8102623SN/A 8112623SN/Avoid 8123349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 8132623SN/A{ 8142623SN/A // received a response from the dcache: complete the load or store 8152623SN/A // instruction 8164870Sstever@eecs.umich.edu assert(!pkt->isError()); 8172623SN/A 8185099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 8193222Sktlim@umich.edu previousTick = curTick; 8203184Srdreslin@umich.edu 8215728Sgblack@eecs.umich.edu if (pkt->senderState) { 8225728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8235728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 8245728Sgblack@eecs.umich.edu assert(send_state); 8255728Sgblack@eecs.umich.edu delete pkt->req; 8265728Sgblack@eecs.umich.edu delete pkt; 8275728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8285728Sgblack@eecs.umich.edu delete send_state; 8295728Sgblack@eecs.umich.edu 8305728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8315728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8325728Sgblack@eecs.umich.edu assert(main_send_state); 8335728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 8345728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 8355728Sgblack@eecs.umich.edu main_send_state->outstanding--; 8365728Sgblack@eecs.umich.edu 8375728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 8385728Sgblack@eecs.umich.edu return; 8395728Sgblack@eecs.umich.edu } else { 8405728Sgblack@eecs.umich.edu delete main_send_state; 8415728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 8425728Sgblack@eecs.umich.edu pkt = big_pkt; 8435728Sgblack@eecs.umich.edu } 8445728Sgblack@eecs.umich.edu } 8455728Sgblack@eecs.umich.edu 8465728Sgblack@eecs.umich.edu assert(_status == DcacheWaitResponse); 8475728Sgblack@eecs.umich.edu _status = Running; 8485728Sgblack@eecs.umich.edu 8492623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 8502623SN/A 8514998Sgblack@eecs.umich.edu // keep an instruction count 8524998Sgblack@eecs.umich.edu if (fault == NoFault) 8534998Sgblack@eecs.umich.edu countInst(); 8545001Sgblack@eecs.umich.edu else if (traceData) { 8555001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 8565001Sgblack@eecs.umich.edu delete traceData; 8575001Sgblack@eecs.umich.edu traceData = NULL; 8585001Sgblack@eecs.umich.edu } 8594998Sgblack@eecs.umich.edu 8605507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 8615507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 8625507Sstever@gmail.com if (pkt->isRead() && pkt->req->isLocked()) { 8633170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 8643170Sstever@eecs.umich.edu } 8653170Sstever@eecs.umich.edu 8662644Sstever@eecs.umich.edu delete pkt->req; 8672644Sstever@eecs.umich.edu delete pkt; 8682644Sstever@eecs.umich.edu 8693184Srdreslin@umich.edu postExecute(); 8703227Sktlim@umich.edu 8713201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 8723201Shsul@eecs.umich.edu advancePC(fault); 8733201Shsul@eecs.umich.edu completeDrain(); 8743201Shsul@eecs.umich.edu 8753201Shsul@eecs.umich.edu return; 8763201Shsul@eecs.umich.edu } 8773201Shsul@eecs.umich.edu 8782644Sstever@eecs.umich.edu advanceInst(fault); 8792623SN/A} 8802623SN/A 8812623SN/A 8822798Sktlim@umich.eduvoid 8832839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 8842798Sktlim@umich.edu{ 8852839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 8862901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 8872839Sktlim@umich.edu drainEvent->process(); 8882798Sktlim@umich.edu} 8892623SN/A 8904192Sktlim@umich.eduvoid 8914192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 8924192Sktlim@umich.edu{ 8934192Sktlim@umich.edu Port::setPeer(port); 8944192Sktlim@umich.edu 8954192Sktlim@umich.edu#if FULL_SYSTEM 8964192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 8974192Sktlim@umich.edu // Ports) 8985497Ssaidi@eecs.umich.edu cpu->tcBase()->connectMemPorts(cpu->tcBase()); 8994192Sktlim@umich.edu#endif 9004192Sktlim@umich.edu} 9014192Sktlim@umich.edu 9022623SN/Abool 9033349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 9042623SN/A{ 9054986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 9063310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 9074584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 9082948Ssaidi@eecs.umich.edu 9095728Sgblack@eecs.umich.edu if (next_tick == curTick) { 9103310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 9115728Sgblack@eecs.umich.edu } else { 9123495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 9135728Sgblack@eecs.umich.edu } 9142948Ssaidi@eecs.umich.edu 9153310Srdreslin@umich.edu return true; 9163310Srdreslin@umich.edu } 9174870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 9184433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 9194433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 9204433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 9214433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 9224433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 9234433Ssaidi@eecs.umich.edu } 9243310Srdreslin@umich.edu } 9254433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 9264433Ssaidi@eecs.umich.edu return true; 9272948Ssaidi@eecs.umich.edu} 9282948Ssaidi@eecs.umich.edu 9292948Ssaidi@eecs.umich.eduvoid 9302948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 9312948Ssaidi@eecs.umich.edu{ 9322630SN/A cpu->completeDataAccess(pkt); 9332623SN/A} 9342623SN/A 9352657Ssaidi@eecs.umich.eduvoid 9362623SN/ATimingSimpleCPU::DcachePort::recvRetry() 9372623SN/A{ 9382623SN/A // we shouldn't get a retry unless we have a packet that we're 9392623SN/A // waiting to transmit 9402623SN/A assert(cpu->dcache_pkt != NULL); 9412623SN/A assert(cpu->_status == DcacheRetry); 9423349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 9435728Sgblack@eecs.umich.edu if (tmp->senderState) { 9445728Sgblack@eecs.umich.edu // This is a packet from a split access. 9455728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 9465728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 9475728Sgblack@eecs.umich.edu assert(send_state); 9485728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 9495728Sgblack@eecs.umich.edu 9505728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 9515728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 9525728Sgblack@eecs.umich.edu assert(main_send_state); 9535728Sgblack@eecs.umich.edu 9545728Sgblack@eecs.umich.edu if (sendTiming(tmp)) { 9555728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 9565728Sgblack@eecs.umich.edu // and try sending the other fragment. 9575728Sgblack@eecs.umich.edu send_state->clearFromParent(); 9585728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 9595728Sgblack@eecs.umich.edu if (other_index > 0) { 9605728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 9615728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 9625728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 9635728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 9645728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 9655728Sgblack@eecs.umich.edu } 9665728Sgblack@eecs.umich.edu } else { 9675728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9685728Sgblack@eecs.umich.edu // memory system takes ownership of packet 9695728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 9705728Sgblack@eecs.umich.edu } 9715728Sgblack@eecs.umich.edu } 9725728Sgblack@eecs.umich.edu } else if (sendTiming(tmp)) { 9732657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9743170Sstever@eecs.umich.edu // memory system takes ownership of packet 9752657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 9762657Ssaidi@eecs.umich.edu } 9772623SN/A} 9782623SN/A 9795606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 9805606Snate@binkert.org Tick t) 9815606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 9825103Ssaidi@eecs.umich.edu{ 9835606Snate@binkert.org cpu->schedule(this, t); 9845103Ssaidi@eecs.umich.edu} 9855103Ssaidi@eecs.umich.edu 9865103Ssaidi@eecs.umich.eduvoid 9875103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 9885103Ssaidi@eecs.umich.edu{ 9895103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 9905103Ssaidi@eecs.umich.edu} 9915103Ssaidi@eecs.umich.edu 9925103Ssaidi@eecs.umich.educonst char * 9935336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 9945103Ssaidi@eecs.umich.edu{ 9955103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 9965103Ssaidi@eecs.umich.edu} 9975103Ssaidi@eecs.umich.edu 9982623SN/A 9995315Sstever@gmail.comvoid 10005315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 10015315Sstever@gmail.com{ 10025315Sstever@gmail.com dcachePort.printAddr(a); 10035315Sstever@gmail.com} 10045315Sstever@gmail.com 10055315Sstever@gmail.com 10062623SN/A//////////////////////////////////////////////////////////////////////// 10072623SN/A// 10082623SN/A// TimingSimpleCPU Simulation Object 10092623SN/A// 10104762Snate@binkert.orgTimingSimpleCPU * 10114762Snate@binkert.orgTimingSimpleCPUParams::create() 10122623SN/A{ 10135529Snate@binkert.org numThreads = 1; 10145529Snate@binkert.org#if !FULL_SYSTEM 10154762Snate@binkert.org if (workload.size() != 1) 10164762Snate@binkert.org panic("only one workload allowed"); 10172623SN/A#endif 10185529Snate@binkert.org return new TimingSimpleCPU(this); 10192623SN/A} 1020