timing.cc revision 5728
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 325103Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh" 332623SN/A#include "arch/utility.hh" 344040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 352623SN/A#include "cpu/exetrace.hh" 362623SN/A#include "cpu/simple/timing.hh" 373348Sbinkertn@umich.edu#include "mem/packet.hh" 383348Sbinkertn@umich.edu#include "mem/packet_access.hh" 394762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 402901Ssaidi@eecs.umich.edu#include "sim/system.hh" 412623SN/A 422623SN/Ausing namespace std; 432623SN/Ausing namespace TheISA; 442623SN/A 452856Srdreslin@umich.eduPort * 462856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 472856Srdreslin@umich.edu{ 482856Srdreslin@umich.edu if (if_name == "dcache_port") 492856Srdreslin@umich.edu return &dcachePort; 502856Srdreslin@umich.edu else if (if_name == "icache_port") 512856Srdreslin@umich.edu return &icachePort; 522856Srdreslin@umich.edu else 532856Srdreslin@umich.edu panic("No Such Port\n"); 542856Srdreslin@umich.edu} 552623SN/A 562623SN/Avoid 572623SN/ATimingSimpleCPU::init() 582623SN/A{ 592623SN/A BaseCPU::init(); 602623SN/A#if FULL_SYSTEM 612680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 622680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 632623SN/A 642623SN/A // initialize CPU, including PC 655712Shsul@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 662623SN/A } 672623SN/A#endif 682623SN/A} 692623SN/A 702623SN/ATick 713349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 722623SN/A{ 732623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 742623SN/A return curTick; 752623SN/A} 762623SN/A 772623SN/Avoid 783349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 792623SN/A{ 803184Srdreslin@umich.edu //No internal storage to update, jusst return 813184Srdreslin@umich.edu return; 822623SN/A} 832623SN/A 842623SN/Avoid 852623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 862623SN/A{ 873647Srdreslin@umich.edu if (status == RangeChange) { 883647Srdreslin@umich.edu if (!snoopRangeSent) { 893647Srdreslin@umich.edu snoopRangeSent = true; 903647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 913647Srdreslin@umich.edu } 922631SN/A return; 933647Srdreslin@umich.edu } 942631SN/A 952623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 962623SN/A} 972623SN/A 982948Ssaidi@eecs.umich.edu 992948Ssaidi@eecs.umich.eduvoid 1003349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1012948Ssaidi@eecs.umich.edu{ 1022948Ssaidi@eecs.umich.edu pkt = _pkt; 1035606Snate@binkert.org cpu->schedule(this, t); 1042948Ssaidi@eecs.umich.edu} 1052948Ssaidi@eecs.umich.edu 1065529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 1075710Scws3k@cs.virginia.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), fetchEvent(this) 1082623SN/A{ 1092623SN/A _status = Idle; 1103647Srdreslin@umich.edu 1113647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1123647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1133647Srdreslin@umich.edu 1142623SN/A ifetch_pkt = dcache_pkt = NULL; 1152839Sktlim@umich.edu drainEvent = NULL; 1163222Sktlim@umich.edu previousTick = 0; 1172901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1182623SN/A} 1192623SN/A 1202623SN/A 1212623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1222623SN/A{ 1232623SN/A} 1242623SN/A 1252623SN/Avoid 1262623SN/ATimingSimpleCPU::serialize(ostream &os) 1272623SN/A{ 1282915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1292915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1302623SN/A BaseSimpleCPU::serialize(os); 1312623SN/A} 1322623SN/A 1332623SN/Avoid 1342623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1352623SN/A{ 1362915Sktlim@umich.edu SimObject::State so_state; 1372915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1382623SN/A BaseSimpleCPU::unserialize(cp, section); 1392798Sktlim@umich.edu} 1402798Sktlim@umich.edu 1412901Ssaidi@eecs.umich.eduunsigned int 1422839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1432798Sktlim@umich.edu{ 1442839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1452798Sktlim@umich.edu // an access to complete. 1465496Ssaidi@eecs.umich.edu if (_status == Idle || _status == Running || _status == SwitchedOut) { 1472901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1482901Ssaidi@eecs.umich.edu return 0; 1492798Sktlim@umich.edu } else { 1502839Sktlim@umich.edu changeState(SimObject::Draining); 1512839Sktlim@umich.edu drainEvent = drain_event; 1522901Ssaidi@eecs.umich.edu return 1; 1532798Sktlim@umich.edu } 1542623SN/A} 1552623SN/A 1562623SN/Avoid 1572798Sktlim@umich.eduTimingSimpleCPU::resume() 1582623SN/A{ 1595221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1602798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1614762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1623201Shsul@eecs.umich.edu 1635710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1645710Scws3k@cs.virginia.edu deschedule(fetchEvent); 1652915Sktlim@umich.edu 1665710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1672623SN/A } 1682798Sktlim@umich.edu 1692901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1702798Sktlim@umich.edu} 1712798Sktlim@umich.edu 1722798Sktlim@umich.eduvoid 1732798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1742798Sktlim@umich.edu{ 1755496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 1762798Sktlim@umich.edu _status = SwitchedOut; 1775099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 1782867Sktlim@umich.edu 1792867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1802867Sktlim@umich.edu // we'll need to cancel it. 1815710Scws3k@cs.virginia.edu if (fetchEvent.scheduled()) 1825606Snate@binkert.org deschedule(fetchEvent); 1832623SN/A} 1842623SN/A 1852623SN/A 1862623SN/Avoid 1872623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1882623SN/A{ 1894192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 1902623SN/A 1912680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1922623SN/A // running and schedule its tick event. 1932680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1942680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1952680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 1962623SN/A _status = Running; 1972623SN/A break; 1982623SN/A } 1992623SN/A } 2003201Shsul@eecs.umich.edu 2013201Shsul@eecs.umich.edu if (_status != Running) { 2023201Shsul@eecs.umich.edu _status = Idle; 2033201Shsul@eecs.umich.edu } 2045169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2055101Ssaidi@eecs.umich.edu previousTick = curTick; 2062623SN/A} 2072623SN/A 2082623SN/A 2092623SN/Avoid 2102623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2112623SN/A{ 2125221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2135221Ssaidi@eecs.umich.edu 2142623SN/A assert(thread_num == 0); 2152683Sktlim@umich.edu assert(thread); 2162623SN/A 2172623SN/A assert(_status == Idle); 2182623SN/A 2192623SN/A notIdleFraction++; 2202623SN/A _status = Running; 2213686Sktlim@umich.edu 2222623SN/A // kick things off by initiating the fetch of the next instruction 2235606Snate@binkert.org schedule(fetchEvent, nextCycle(curTick + ticks(delay))); 2242623SN/A} 2252623SN/A 2262623SN/A 2272623SN/Avoid 2282623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2292623SN/A{ 2305221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2315221Ssaidi@eecs.umich.edu 2322623SN/A assert(thread_num == 0); 2332683Sktlim@umich.edu assert(thread); 2342623SN/A 2352644Sstever@eecs.umich.edu assert(_status == Running); 2362623SN/A 2372644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2382644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2392623SN/A 2402623SN/A notIdleFraction--; 2412623SN/A _status = Idle; 2422623SN/A} 2432623SN/A 2445728Sgblack@eecs.umich.edubool 2455728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2465728Sgblack@eecs.umich.edu{ 2475728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 2485728Sgblack@eecs.umich.edu if (req->isMmapedIpr()) { 2495728Sgblack@eecs.umich.edu Tick delay; 2505728Sgblack@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2515728Sgblack@eecs.umich.edu new IprEvent(pkt, this, nextCycle(curTick + delay)); 2525728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2535728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2545728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(pkt)) { 2555728Sgblack@eecs.umich.edu _status = DcacheRetry; 2565728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2575728Sgblack@eecs.umich.edu } else { 2585728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2595728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2605728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2615728Sgblack@eecs.umich.edu } 2625728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2635728Sgblack@eecs.umich.edu} 2642623SN/A 2652623SN/Atemplate <class T> 2662623SN/AFault 2672623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2682623SN/A{ 2695728Sgblack@eecs.umich.edu Fault fault; 2705728Sgblack@eecs.umich.edu const int asid = 0; 2715728Sgblack@eecs.umich.edu const int thread_id = 0; 2725728Sgblack@eecs.umich.edu const Addr pc = thread->readPC(); 2732623SN/A 2745728Sgblack@eecs.umich.edu PacketPtr pkt; 2755728Sgblack@eecs.umich.edu RequestPtr req; 2762623SN/A 2775728Sgblack@eecs.umich.edu int block_size = dcachePort.peerBlockSize(); 2785728Sgblack@eecs.umich.edu int data_size = sizeof(T); 2792623SN/A 2805728Sgblack@eecs.umich.edu Addr second_addr = roundDown(addr + data_size - 1, block_size); 2815728Sgblack@eecs.umich.edu 2825728Sgblack@eecs.umich.edu if (second_addr > addr) { 2835728Sgblack@eecs.umich.edu Addr first_size = second_addr - addr; 2845728Sgblack@eecs.umich.edu Addr second_size = data_size - first_size; 2855728Sgblack@eecs.umich.edu // Make sure we'll only need two accesses. 2865728Sgblack@eecs.umich.edu assert(roundDown(second_addr + second_size - 1, block_size) == 2875728Sgblack@eecs.umich.edu second_addr); 2885728Sgblack@eecs.umich.edu 2895728Sgblack@eecs.umich.edu /* 2905728Sgblack@eecs.umich.edu * Do the translations. If something isn't going to work, find out 2915728Sgblack@eecs.umich.edu * before we waste time setting up anything else. 2925728Sgblack@eecs.umich.edu */ 2935728Sgblack@eecs.umich.edu req = new Request(asid, addr, first_size, 2945728Sgblack@eecs.umich.edu flags, pc, _cpuId, thread_id); 2955728Sgblack@eecs.umich.edu fault = thread->translateDataReadReq(req); 2965728Sgblack@eecs.umich.edu if (fault != NoFault) { 2975728Sgblack@eecs.umich.edu delete req; 2985728Sgblack@eecs.umich.edu return fault; 2995728Sgblack@eecs.umich.edu } 3005728Sgblack@eecs.umich.edu Request *second_req = 3015728Sgblack@eecs.umich.edu new Request(asid, second_addr, second_size, 3025728Sgblack@eecs.umich.edu flags, pc, _cpuId, thread_id); 3035728Sgblack@eecs.umich.edu fault = thread->translateDataReadReq(second_req); 3045728Sgblack@eecs.umich.edu if (fault != NoFault) { 3055728Sgblack@eecs.umich.edu delete req; 3065728Sgblack@eecs.umich.edu delete second_req; 3075728Sgblack@eecs.umich.edu return fault; 3085728Sgblack@eecs.umich.edu } 3095728Sgblack@eecs.umich.edu 3105728Sgblack@eecs.umich.edu T * data_ptr = new T; 3115728Sgblack@eecs.umich.edu 3125728Sgblack@eecs.umich.edu /* 3135728Sgblack@eecs.umich.edu * This is the big packet that will hold the data we've gotten so far, 3145728Sgblack@eecs.umich.edu * if any, and also act as the response we actually give to the 3155728Sgblack@eecs.umich.edu * instruction. 3165728Sgblack@eecs.umich.edu */ 3175728Sgblack@eecs.umich.edu Request *orig_req = 3185728Sgblack@eecs.umich.edu new Request(asid, addr, data_size, flags, pc, _cpuId, thread_id); 3195728Sgblack@eecs.umich.edu orig_req->setPhys(req->getPaddr(), data_size, flags); 3205728Sgblack@eecs.umich.edu PacketPtr big_pkt = 3215728Sgblack@eecs.umich.edu new Packet(orig_req, MemCmd::ReadResp, Packet::Broadcast); 3225728Sgblack@eecs.umich.edu big_pkt->dataDynamic<T>(data_ptr); 3235728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 3245728Sgblack@eecs.umich.edu big_pkt->senderState = main_send_state; 3255728Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 3265728Sgblack@eecs.umich.edu 3275728Sgblack@eecs.umich.edu // This is the packet we'll process now. 3285728Sgblack@eecs.umich.edu pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 3295728Sgblack@eecs.umich.edu pkt->dataStatic<uint8_t>((uint8_t *)data_ptr); 3305728Sgblack@eecs.umich.edu pkt->senderState = new SplitFragmentSenderState(big_pkt, 0); 3315728Sgblack@eecs.umich.edu 3325728Sgblack@eecs.umich.edu // This is the second half of the access we'll deal with later. 3335728Sgblack@eecs.umich.edu PacketPtr second_pkt = 3345728Sgblack@eecs.umich.edu new Packet(second_req, MemCmd::ReadReq, Packet::Broadcast); 3355728Sgblack@eecs.umich.edu second_pkt->dataStatic<uint8_t>((uint8_t *)data_ptr + first_size); 3365728Sgblack@eecs.umich.edu second_pkt->senderState = new SplitFragmentSenderState(big_pkt, 1); 3375728Sgblack@eecs.umich.edu if (!handleReadPacket(pkt)) { 3385728Sgblack@eecs.umich.edu main_send_state->fragments[1] = second_pkt; 3395728Sgblack@eecs.umich.edu } else { 3405728Sgblack@eecs.umich.edu handleReadPacket(second_pkt); 3415728Sgblack@eecs.umich.edu } 3425728Sgblack@eecs.umich.edu } else { 3435728Sgblack@eecs.umich.edu req = new Request(asid, addr, data_size, 3445728Sgblack@eecs.umich.edu flags, pc, _cpuId, thread_id); 3455728Sgblack@eecs.umich.edu 3465728Sgblack@eecs.umich.edu // translate to physical address 3475728Sgblack@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 3485728Sgblack@eecs.umich.edu 3495728Sgblack@eecs.umich.edu if (fault != NoFault) { 3505728Sgblack@eecs.umich.edu delete req; 3515728Sgblack@eecs.umich.edu return fault; 3525728Sgblack@eecs.umich.edu } 3535728Sgblack@eecs.umich.edu 3545728Sgblack@eecs.umich.edu pkt = new Packet(req, 3555728Sgblack@eecs.umich.edu (req->isLocked() ? 3565728Sgblack@eecs.umich.edu MemCmd::LoadLockedReq : MemCmd::ReadReq), 3575728Sgblack@eecs.umich.edu Packet::Broadcast); 3583169Sstever@eecs.umich.edu pkt->dataDynamic<T>(new T); 3592623SN/A 3605728Sgblack@eecs.umich.edu handleReadPacket(pkt); 3612623SN/A } 3622623SN/A 3635408Sgblack@eecs.umich.edu if (traceData) { 3645408Sgblack@eecs.umich.edu traceData->setData(data); 3655728Sgblack@eecs.umich.edu traceData->setAddr(addr); 3665408Sgblack@eecs.umich.edu } 3675728Sgblack@eecs.umich.edu 3685728Sgblack@eecs.umich.edu // This will need a new way to tell if it has a dcache attached. 3695728Sgblack@eecs.umich.edu if (req->isUncacheable()) 3705728Sgblack@eecs.umich.edu recordEvent("Uncached Read"); 3715728Sgblack@eecs.umich.edu 3725728Sgblack@eecs.umich.edu return NoFault; 3732623SN/A} 3742623SN/A 3755177Sgblack@eecs.umich.eduFault 3765177Sgblack@eecs.umich.eduTimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr, 3775177Sgblack@eecs.umich.edu int size, unsigned flags) 3785177Sgblack@eecs.umich.edu{ 3795177Sgblack@eecs.umich.edu Request *req = 3805712Shsul@eecs.umich.edu new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0); 3815177Sgblack@eecs.umich.edu 3825177Sgblack@eecs.umich.edu if (traceData) { 3835177Sgblack@eecs.umich.edu traceData->setAddr(vaddr); 3845177Sgblack@eecs.umich.edu } 3855177Sgblack@eecs.umich.edu 3865177Sgblack@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3875177Sgblack@eecs.umich.edu 3885177Sgblack@eecs.umich.edu if (fault == NoFault) 3895177Sgblack@eecs.umich.edu paddr = req->getPaddr(); 3905177Sgblack@eecs.umich.edu 3915177Sgblack@eecs.umich.edu delete req; 3925177Sgblack@eecs.umich.edu return fault; 3935177Sgblack@eecs.umich.edu} 3945177Sgblack@eecs.umich.edu 3952623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3962623SN/A 3972623SN/Atemplate 3982623SN/AFault 3994040Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 4004040Ssaidi@eecs.umich.edu 4014040Ssaidi@eecs.umich.edutemplate 4024040Ssaidi@eecs.umich.eduFault 4034115Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 4044115Ssaidi@eecs.umich.edu 4054115Ssaidi@eecs.umich.edutemplate 4064115Ssaidi@eecs.umich.eduFault 4072623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 4082623SN/A 4092623SN/Atemplate 4102623SN/AFault 4112623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 4122623SN/A 4132623SN/Atemplate 4142623SN/AFault 4152623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 4162623SN/A 4172623SN/Atemplate 4182623SN/AFault 4192623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 4202623SN/A 4212623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4222623SN/A 4232623SN/Atemplate<> 4242623SN/AFault 4252623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 4262623SN/A{ 4272623SN/A return read(addr, *(uint64_t*)&data, flags); 4282623SN/A} 4292623SN/A 4302623SN/Atemplate<> 4312623SN/AFault 4322623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 4332623SN/A{ 4342623SN/A return read(addr, *(uint32_t*)&data, flags); 4352623SN/A} 4362623SN/A 4372623SN/A 4382623SN/Atemplate<> 4392623SN/AFault 4402623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 4412623SN/A{ 4422623SN/A return read(addr, (uint32_t&)data, flags); 4432623SN/A} 4442623SN/A 4455728Sgblack@eecs.umich.edubool 4465728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4475728Sgblack@eecs.umich.edu{ 4485728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4495728Sgblack@eecs.umich.edu if (req->isMmapedIpr()) { 4505728Sgblack@eecs.umich.edu Tick delay; 4515728Sgblack@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4525728Sgblack@eecs.umich.edu new IprEvent(dcache_pkt, this, nextCycle(curTick + delay)); 4535728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4545728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4555728Sgblack@eecs.umich.edu } else if (!dcachePort.sendTiming(dcache_pkt)) { 4565728Sgblack@eecs.umich.edu _status = DcacheRetry; 4575728Sgblack@eecs.umich.edu } else { 4585728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4595728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4605728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4615728Sgblack@eecs.umich.edu } 4625728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4635728Sgblack@eecs.umich.edu} 4642623SN/A 4652623SN/Atemplate <class T> 4662623SN/AFault 4672623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 4682623SN/A{ 4695728Sgblack@eecs.umich.edu const int asid = 0; 4705728Sgblack@eecs.umich.edu const int thread_id = 0; 4715728Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 4725728Sgblack@eecs.umich.edu const Addr pc = thread->readPC(); 4732623SN/A 4745728Sgblack@eecs.umich.edu RequestPtr req; 4754040Ssaidi@eecs.umich.edu 4765728Sgblack@eecs.umich.edu int block_size = dcachePort.peerBlockSize(); 4775728Sgblack@eecs.umich.edu int data_size = sizeof(T); 4783169Sstever@eecs.umich.edu 4795728Sgblack@eecs.umich.edu Addr second_addr = roundDown(addr + data_size - 1, block_size); 4805728Sgblack@eecs.umich.edu 4815728Sgblack@eecs.umich.edu if (second_addr > addr) { 4825728Sgblack@eecs.umich.edu Fault fault; 4835728Sgblack@eecs.umich.edu Addr first_size = second_addr - addr; 4845728Sgblack@eecs.umich.edu Addr second_size = data_size - first_size; 4855728Sgblack@eecs.umich.edu // Make sure we'll only need two accesses. 4865728Sgblack@eecs.umich.edu assert(roundDown(second_addr + second_size - 1, block_size) == 4875728Sgblack@eecs.umich.edu second_addr); 4885728Sgblack@eecs.umich.edu 4895728Sgblack@eecs.umich.edu req = new Request(asid, addr, first_size, 4905728Sgblack@eecs.umich.edu flags, pc, _cpuId, thread_id); 4915728Sgblack@eecs.umich.edu fault = thread->translateDataWriteReq(req); 4925728Sgblack@eecs.umich.edu if (fault != NoFault) { 4935728Sgblack@eecs.umich.edu delete req; 4945728Sgblack@eecs.umich.edu return fault; 4955728Sgblack@eecs.umich.edu } 4965728Sgblack@eecs.umich.edu RequestPtr second_req = new Request(asid, second_addr, second_size, 4975728Sgblack@eecs.umich.edu flags, pc, _cpuId, thread_id); 4985728Sgblack@eecs.umich.edu fault = thread->translateDataWriteReq(second_req); 4995728Sgblack@eecs.umich.edu if (fault != NoFault) { 5005728Sgblack@eecs.umich.edu delete req; 5015728Sgblack@eecs.umich.edu delete second_req; 5025728Sgblack@eecs.umich.edu return fault; 5035728Sgblack@eecs.umich.edu } 5045728Sgblack@eecs.umich.edu 5055728Sgblack@eecs.umich.edu if (req->isLocked() || req->isSwap() || 5065728Sgblack@eecs.umich.edu second_req->isLocked() || second_req->isSwap()) { 5075728Sgblack@eecs.umich.edu panic("LL/SCs and swaps can't be split."); 5085728Sgblack@eecs.umich.edu } 5095728Sgblack@eecs.umich.edu 5105728Sgblack@eecs.umich.edu T * data_ptr = new T; 5115728Sgblack@eecs.umich.edu 5125728Sgblack@eecs.umich.edu /* 5135728Sgblack@eecs.umich.edu * This is the big packet that will hold the data we've gotten so far, 5145728Sgblack@eecs.umich.edu * if any, and also act as the response we actually give to the 5155728Sgblack@eecs.umich.edu * instruction. 5165728Sgblack@eecs.umich.edu */ 5175728Sgblack@eecs.umich.edu RequestPtr orig_req = 5185728Sgblack@eecs.umich.edu new Request(asid, addr, data_size, flags, pc, _cpuId, thread_id); 5195728Sgblack@eecs.umich.edu orig_req->setPhys(req->getPaddr(), data_size, flags); 5205728Sgblack@eecs.umich.edu PacketPtr big_pkt = 5215728Sgblack@eecs.umich.edu new Packet(orig_req, MemCmd::WriteResp, Packet::Broadcast); 5225728Sgblack@eecs.umich.edu big_pkt->dataDynamic<T>(data_ptr); 5235728Sgblack@eecs.umich.edu big_pkt->set(data); 5245728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 5255728Sgblack@eecs.umich.edu big_pkt->senderState = main_send_state; 5265728Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 5275728Sgblack@eecs.umich.edu 5285728Sgblack@eecs.umich.edu assert(dcache_pkt == NULL); 5295728Sgblack@eecs.umich.edu // This is the packet we'll process now. 5305728Sgblack@eecs.umich.edu dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast); 5315728Sgblack@eecs.umich.edu dcache_pkt->dataStatic<uint8_t>((uint8_t *)data_ptr); 5325728Sgblack@eecs.umich.edu dcache_pkt->senderState = new SplitFragmentSenderState(big_pkt, 0); 5335728Sgblack@eecs.umich.edu 5345728Sgblack@eecs.umich.edu // This is the second half of the access we'll deal with later. 5355728Sgblack@eecs.umich.edu PacketPtr second_pkt = 5365728Sgblack@eecs.umich.edu new Packet(second_req, MemCmd::WriteReq, Packet::Broadcast); 5375728Sgblack@eecs.umich.edu second_pkt->dataStatic<uint8_t>((uint8_t *)data_ptr + first_size); 5385728Sgblack@eecs.umich.edu second_pkt->senderState = new SplitFragmentSenderState(big_pkt, 1); 5395728Sgblack@eecs.umich.edu if (!handleWritePacket()) { 5405728Sgblack@eecs.umich.edu main_send_state->fragments[1] = second_pkt; 5415728Sgblack@eecs.umich.edu } else { 5425728Sgblack@eecs.umich.edu dcache_pkt = second_pkt; 5435728Sgblack@eecs.umich.edu handleWritePacket(); 5445728Sgblack@eecs.umich.edu } 5455728Sgblack@eecs.umich.edu } else { 5465728Sgblack@eecs.umich.edu req = new Request(asid, addr, data_size, flags, pc, _cpuId, thread_id); 5475728Sgblack@eecs.umich.edu 5485728Sgblack@eecs.umich.edu // translate to physical address 5495728Sgblack@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 5505728Sgblack@eecs.umich.edu if (fault != NoFault) { 5515728Sgblack@eecs.umich.edu delete req; 5525728Sgblack@eecs.umich.edu return fault; 5535728Sgblack@eecs.umich.edu } 5545728Sgblack@eecs.umich.edu 5554878Sstever@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 5563170Sstever@eecs.umich.edu 5573170Sstever@eecs.umich.edu if (req->isLocked()) { 5584878Sstever@eecs.umich.edu cmd = MemCmd::StoreCondReq; 5593170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 5604878Sstever@eecs.umich.edu } else if (req->isSwap()) { 5614878Sstever@eecs.umich.edu cmd = MemCmd::SwapReq; 5624878Sstever@eecs.umich.edu if (req->isCondSwap()) { 5634878Sstever@eecs.umich.edu assert(res); 5644878Sstever@eecs.umich.edu req->setExtraData(*res); 5654878Sstever@eecs.umich.edu } 5663170Sstever@eecs.umich.edu } 5674584Ssaidi@eecs.umich.edu 5684881Sstever@eecs.umich.edu // Note: need to allocate dcache_pkt even if do_access is 5694881Sstever@eecs.umich.edu // false, as it's used unconditionally to call completeAcc(). 5704881Sstever@eecs.umich.edu assert(dcache_pkt == NULL); 5714881Sstever@eecs.umich.edu dcache_pkt = new Packet(req, cmd, Packet::Broadcast); 5724881Sstever@eecs.umich.edu dcache_pkt->allocate(); 5735728Sgblack@eecs.umich.edu if (req->isMmapedIpr()) 5745728Sgblack@eecs.umich.edu dcache_pkt->set(htog(data)); 5755728Sgblack@eecs.umich.edu else 5765728Sgblack@eecs.umich.edu dcache_pkt->set(data); 5773170Sstever@eecs.umich.edu 5785728Sgblack@eecs.umich.edu if (do_access) 5795728Sgblack@eecs.umich.edu handleWritePacket(); 5802623SN/A } 5812623SN/A 5825408Sgblack@eecs.umich.edu if (traceData) { 5835728Sgblack@eecs.umich.edu traceData->setAddr(req->getVaddr()); 5845408Sgblack@eecs.umich.edu traceData->setData(data); 5855408Sgblack@eecs.umich.edu } 5862623SN/A 5875728Sgblack@eecs.umich.edu // This will need a new way to tell if it's hooked up to a cache or not. 5885728Sgblack@eecs.umich.edu if (req->isUncacheable()) 5895728Sgblack@eecs.umich.edu recordEvent("Uncached Write"); 5905728Sgblack@eecs.umich.edu 5912623SN/A // If the write needs to have a fault on the access, consider calling 5922623SN/A // changeStatus() and changing it to "bad addr write" or something. 5935728Sgblack@eecs.umich.edu return NoFault; 5942623SN/A} 5952623SN/A 5965177Sgblack@eecs.umich.eduFault 5975177Sgblack@eecs.umich.eduTimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr, 5985177Sgblack@eecs.umich.edu int size, unsigned flags) 5995177Sgblack@eecs.umich.edu{ 6005177Sgblack@eecs.umich.edu Request *req = 6015712Shsul@eecs.umich.edu new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0); 6025177Sgblack@eecs.umich.edu 6035177Sgblack@eecs.umich.edu if (traceData) { 6045177Sgblack@eecs.umich.edu traceData->setAddr(vaddr); 6055177Sgblack@eecs.umich.edu } 6065177Sgblack@eecs.umich.edu 6075177Sgblack@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 6085177Sgblack@eecs.umich.edu 6095177Sgblack@eecs.umich.edu if (fault == NoFault) 6105177Sgblack@eecs.umich.edu paddr = req->getPaddr(); 6115177Sgblack@eecs.umich.edu 6125177Sgblack@eecs.umich.edu delete req; 6135177Sgblack@eecs.umich.edu return fault; 6145177Sgblack@eecs.umich.edu} 6155177Sgblack@eecs.umich.edu 6162623SN/A 6172623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 6182623SN/Atemplate 6192623SN/AFault 6204224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin32_t data, Addr addr, 6214224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 6224224Sgblack@eecs.umich.edu 6234224Sgblack@eecs.umich.edutemplate 6244224Sgblack@eecs.umich.eduFault 6254224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin64_t data, Addr addr, 6264224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 6274224Sgblack@eecs.umich.edu 6284224Sgblack@eecs.umich.edutemplate 6294224Sgblack@eecs.umich.eduFault 6302623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 6312623SN/A unsigned flags, uint64_t *res); 6322623SN/A 6332623SN/Atemplate 6342623SN/AFault 6352623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 6362623SN/A unsigned flags, uint64_t *res); 6372623SN/A 6382623SN/Atemplate 6392623SN/AFault 6402623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 6412623SN/A unsigned flags, uint64_t *res); 6422623SN/A 6432623SN/Atemplate 6442623SN/AFault 6452623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 6462623SN/A unsigned flags, uint64_t *res); 6472623SN/A 6482623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 6492623SN/A 6502623SN/Atemplate<> 6512623SN/AFault 6522623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 6532623SN/A{ 6542623SN/A return write(*(uint64_t*)&data, addr, flags, res); 6552623SN/A} 6562623SN/A 6572623SN/Atemplate<> 6582623SN/AFault 6592623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 6602623SN/A{ 6612623SN/A return write(*(uint32_t*)&data, addr, flags, res); 6622623SN/A} 6632623SN/A 6642623SN/A 6652623SN/Atemplate<> 6662623SN/AFault 6672623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 6682623SN/A{ 6692623SN/A return write((uint32_t)data, addr, flags, res); 6702623SN/A} 6712623SN/A 6722623SN/A 6732623SN/Avoid 6742623SN/ATimingSimpleCPU::fetch() 6752623SN/A{ 6765221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 6775221Ssaidi@eecs.umich.edu 6783387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 6793387Sgblack@eecs.umich.edu checkForInterrupts(); 6802631SN/A 6815348Ssaidi@eecs.umich.edu checkPcEventQueue(); 6825348Ssaidi@eecs.umich.edu 6835669Sgblack@eecs.umich.edu bool fromRom = isRomMicroPC(thread->readMicroPC()); 6842623SN/A 6855669Sgblack@eecs.umich.edu if (!fromRom) { 6865669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 6875712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 6885669Sgblack@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 6892623SN/A 6905669Sgblack@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast); 6915669Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 6925669Sgblack@eecs.umich.edu 6935669Sgblack@eecs.umich.edu if (fault == NoFault) { 6945669Sgblack@eecs.umich.edu if (!icachePort.sendTiming(ifetch_pkt)) { 6955669Sgblack@eecs.umich.edu // Need to wait for retry 6965669Sgblack@eecs.umich.edu _status = IcacheRetry; 6975669Sgblack@eecs.umich.edu } else { 6985669Sgblack@eecs.umich.edu // Need to wait for cache to respond 6995669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 7005669Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 7015669Sgblack@eecs.umich.edu ifetch_pkt = NULL; 7025669Sgblack@eecs.umich.edu } 7032623SN/A } else { 7045669Sgblack@eecs.umich.edu delete ifetch_req; 7055669Sgblack@eecs.umich.edu delete ifetch_pkt; 7065669Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 7075669Sgblack@eecs.umich.edu advanceInst(fault); 7082623SN/A } 7092623SN/A } else { 7105669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 7115669Sgblack@eecs.umich.edu completeIfetch(NULL); 7122623SN/A } 7133222Sktlim@umich.edu 7145099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 7153222Sktlim@umich.edu previousTick = curTick; 7162623SN/A} 7172623SN/A 7182623SN/A 7192623SN/Avoid 7202644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 7212623SN/A{ 7225726Sgblack@eecs.umich.edu if (fault != NoFault || !stayAtPC) 7235726Sgblack@eecs.umich.edu advancePC(fault); 7242623SN/A 7252631SN/A if (_status == Running) { 7262631SN/A // kick off fetch of next instruction... callback from icache 7272631SN/A // response will cause that instruction to be executed, 7282631SN/A // keeping the CPU running. 7292631SN/A fetch(); 7302631SN/A } 7312623SN/A} 7322623SN/A 7332623SN/A 7342623SN/Avoid 7353349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 7362623SN/A{ 7375221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Complete ICache Fetch\n"); 7385221Ssaidi@eecs.umich.edu 7392623SN/A // received a response from the icache: execute the received 7402623SN/A // instruction 7415669Sgblack@eecs.umich.edu 7425669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 7432623SN/A assert(_status == IcacheWaitResponse); 7442798Sktlim@umich.edu 7452623SN/A _status = Running; 7462644Sstever@eecs.umich.edu 7475099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 7483222Sktlim@umich.edu previousTick = curTick; 7493222Sktlim@umich.edu 7502839Sktlim@umich.edu if (getState() == SimObject::Draining) { 7515669Sgblack@eecs.umich.edu if (pkt) { 7525669Sgblack@eecs.umich.edu delete pkt->req; 7535669Sgblack@eecs.umich.edu delete pkt; 7545669Sgblack@eecs.umich.edu } 7553658Sktlim@umich.edu 7562839Sktlim@umich.edu completeDrain(); 7572798Sktlim@umich.edu return; 7582798Sktlim@umich.edu } 7592798Sktlim@umich.edu 7602623SN/A preExecute(); 7615726Sgblack@eecs.umich.edu if (curStaticInst && 7625726Sgblack@eecs.umich.edu curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 7632623SN/A // load or store: just send to dcache 7642623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 7653170Sstever@eecs.umich.edu if (_status != Running) { 7663170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 7673170Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DcacheRetry); 7683170Sstever@eecs.umich.edu assert(fault == NoFault); 7692644Sstever@eecs.umich.edu } else { 7703170Sstever@eecs.umich.edu if (fault == NoFault) { 7715335Shines@cs.fsu.edu // Note that ARM can have NULL packets if the instruction gets 7725335Shines@cs.fsu.edu // squashed due to predication 7733170Sstever@eecs.umich.edu // early fail on store conditional: complete now 7745335Shines@cs.fsu.edu assert(dcache_pkt != NULL || THE_ISA == ARM_ISA); 7755335Shines@cs.fsu.edu 7763170Sstever@eecs.umich.edu fault = curStaticInst->completeAcc(dcache_pkt, this, 7773170Sstever@eecs.umich.edu traceData); 7785335Shines@cs.fsu.edu if (dcache_pkt != NULL) 7795335Shines@cs.fsu.edu { 7805335Shines@cs.fsu.edu delete dcache_pkt->req; 7815335Shines@cs.fsu.edu delete dcache_pkt; 7825335Shines@cs.fsu.edu dcache_pkt = NULL; 7835335Shines@cs.fsu.edu } 7844998Sgblack@eecs.umich.edu 7854998Sgblack@eecs.umich.edu // keep an instruction count 7864998Sgblack@eecs.umich.edu if (fault == NoFault) 7874998Sgblack@eecs.umich.edu countInst(); 7885001Sgblack@eecs.umich.edu } else if (traceData) { 7895001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7905001Sgblack@eecs.umich.edu delete traceData; 7915001Sgblack@eecs.umich.edu traceData = NULL; 7923170Sstever@eecs.umich.edu } 7934998Sgblack@eecs.umich.edu 7942644Sstever@eecs.umich.edu postExecute(); 7955103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7965103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7975103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7985103Ssaidi@eecs.umich.edu instCnt++; 7992644Sstever@eecs.umich.edu advanceInst(fault); 8002644Sstever@eecs.umich.edu } 8015726Sgblack@eecs.umich.edu } else if (curStaticInst) { 8022623SN/A // non-memory instruction: execute completely now 8032623SN/A Fault fault = curStaticInst->execute(this, traceData); 8044998Sgblack@eecs.umich.edu 8054998Sgblack@eecs.umich.edu // keep an instruction count 8064998Sgblack@eecs.umich.edu if (fault == NoFault) 8074998Sgblack@eecs.umich.edu countInst(); 8085001Sgblack@eecs.umich.edu else if (traceData) { 8095001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 8105001Sgblack@eecs.umich.edu delete traceData; 8115001Sgblack@eecs.umich.edu traceData = NULL; 8125001Sgblack@eecs.umich.edu } 8134998Sgblack@eecs.umich.edu 8142644Sstever@eecs.umich.edu postExecute(); 8155103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 8165103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 8175103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 8185103Ssaidi@eecs.umich.edu instCnt++; 8192644Sstever@eecs.umich.edu advanceInst(fault); 8205726Sgblack@eecs.umich.edu } else { 8215726Sgblack@eecs.umich.edu advanceInst(NoFault); 8222623SN/A } 8233658Sktlim@umich.edu 8245669Sgblack@eecs.umich.edu if (pkt) { 8255669Sgblack@eecs.umich.edu delete pkt->req; 8265669Sgblack@eecs.umich.edu delete pkt; 8275669Sgblack@eecs.umich.edu } 8282623SN/A} 8292623SN/A 8302948Ssaidi@eecs.umich.eduvoid 8312948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 8322948Ssaidi@eecs.umich.edu{ 8332948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 8342948Ssaidi@eecs.umich.edu} 8352623SN/A 8362623SN/Abool 8373349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 8382623SN/A{ 8394986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 8403310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 8414584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 8422948Ssaidi@eecs.umich.edu 8433495Sktlim@umich.edu if (next_tick == curTick) 8443310Srdreslin@umich.edu cpu->completeIfetch(pkt); 8453310Srdreslin@umich.edu else 8463495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 8472948Ssaidi@eecs.umich.edu 8483310Srdreslin@umich.edu return true; 8493310Srdreslin@umich.edu } 8504870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 8514433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 8524433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 8534433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 8544433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 8554433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 8564433Ssaidi@eecs.umich.edu } 8573310Srdreslin@umich.edu } 8584433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 8594433Ssaidi@eecs.umich.edu return true; 8602623SN/A} 8612623SN/A 8622657Ssaidi@eecs.umich.eduvoid 8632623SN/ATimingSimpleCPU::IcachePort::recvRetry() 8642623SN/A{ 8652623SN/A // we shouldn't get a retry unless we have a packet that we're 8662623SN/A // waiting to transmit 8672623SN/A assert(cpu->ifetch_pkt != NULL); 8682623SN/A assert(cpu->_status == IcacheRetry); 8693349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 8702657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 8712657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 8722657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 8732657Ssaidi@eecs.umich.edu } 8742623SN/A} 8752623SN/A 8762623SN/Avoid 8773349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 8782623SN/A{ 8792623SN/A // received a response from the dcache: complete the load or store 8802623SN/A // instruction 8814870Sstever@eecs.umich.edu assert(!pkt->isError()); 8822623SN/A 8835099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 8843222Sktlim@umich.edu previousTick = curTick; 8853184Srdreslin@umich.edu 8865728Sgblack@eecs.umich.edu if (pkt->senderState) { 8875728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8885728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 8895728Sgblack@eecs.umich.edu assert(send_state); 8905728Sgblack@eecs.umich.edu delete pkt->req; 8915728Sgblack@eecs.umich.edu delete pkt; 8925728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8935728Sgblack@eecs.umich.edu delete send_state; 8945728Sgblack@eecs.umich.edu 8955728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8965728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8975728Sgblack@eecs.umich.edu assert(main_send_state); 8985728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 8995728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 9005728Sgblack@eecs.umich.edu main_send_state->outstanding--; 9015728Sgblack@eecs.umich.edu 9025728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 9035728Sgblack@eecs.umich.edu return; 9045728Sgblack@eecs.umich.edu } else { 9055728Sgblack@eecs.umich.edu delete main_send_state; 9065728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 9075728Sgblack@eecs.umich.edu pkt = big_pkt; 9085728Sgblack@eecs.umich.edu } 9095728Sgblack@eecs.umich.edu } 9105728Sgblack@eecs.umich.edu 9115728Sgblack@eecs.umich.edu assert(_status == DcacheWaitResponse); 9125728Sgblack@eecs.umich.edu _status = Running; 9135728Sgblack@eecs.umich.edu 9142623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 9152623SN/A 9164998Sgblack@eecs.umich.edu // keep an instruction count 9174998Sgblack@eecs.umich.edu if (fault == NoFault) 9184998Sgblack@eecs.umich.edu countInst(); 9195001Sgblack@eecs.umich.edu else if (traceData) { 9205001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 9215001Sgblack@eecs.umich.edu delete traceData; 9225001Sgblack@eecs.umich.edu traceData = NULL; 9235001Sgblack@eecs.umich.edu } 9244998Sgblack@eecs.umich.edu 9255507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 9265507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 9275507Sstever@gmail.com if (pkt->isRead() && pkt->req->isLocked()) { 9283170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 9293170Sstever@eecs.umich.edu } 9303170Sstever@eecs.umich.edu 9312644Sstever@eecs.umich.edu delete pkt->req; 9322644Sstever@eecs.umich.edu delete pkt; 9332644Sstever@eecs.umich.edu 9343184Srdreslin@umich.edu postExecute(); 9353227Sktlim@umich.edu 9363201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 9373201Shsul@eecs.umich.edu advancePC(fault); 9383201Shsul@eecs.umich.edu completeDrain(); 9393201Shsul@eecs.umich.edu 9403201Shsul@eecs.umich.edu return; 9413201Shsul@eecs.umich.edu } 9423201Shsul@eecs.umich.edu 9432644Sstever@eecs.umich.edu advanceInst(fault); 9442623SN/A} 9452623SN/A 9462623SN/A 9472798Sktlim@umich.eduvoid 9482839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 9492798Sktlim@umich.edu{ 9502839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 9512901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 9522839Sktlim@umich.edu drainEvent->process(); 9532798Sktlim@umich.edu} 9542623SN/A 9554192Sktlim@umich.eduvoid 9564192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 9574192Sktlim@umich.edu{ 9584192Sktlim@umich.edu Port::setPeer(port); 9594192Sktlim@umich.edu 9604192Sktlim@umich.edu#if FULL_SYSTEM 9614192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 9624192Sktlim@umich.edu // Ports) 9635497Ssaidi@eecs.umich.edu cpu->tcBase()->connectMemPorts(cpu->tcBase()); 9644192Sktlim@umich.edu#endif 9654192Sktlim@umich.edu} 9664192Sktlim@umich.edu 9672623SN/Abool 9683349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 9692623SN/A{ 9704986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 9713310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 9724584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 9732948Ssaidi@eecs.umich.edu 9745728Sgblack@eecs.umich.edu if (next_tick == curTick) { 9753310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 9765728Sgblack@eecs.umich.edu } else { 9773495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 9785728Sgblack@eecs.umich.edu } 9792948Ssaidi@eecs.umich.edu 9803310Srdreslin@umich.edu return true; 9813310Srdreslin@umich.edu } 9824870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 9834433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 9844433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 9854433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 9864433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 9874433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 9884433Ssaidi@eecs.umich.edu } 9893310Srdreslin@umich.edu } 9904433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 9914433Ssaidi@eecs.umich.edu return true; 9922948Ssaidi@eecs.umich.edu} 9932948Ssaidi@eecs.umich.edu 9942948Ssaidi@eecs.umich.eduvoid 9952948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 9962948Ssaidi@eecs.umich.edu{ 9972630SN/A cpu->completeDataAccess(pkt); 9982623SN/A} 9992623SN/A 10002657Ssaidi@eecs.umich.eduvoid 10012623SN/ATimingSimpleCPU::DcachePort::recvRetry() 10022623SN/A{ 10032623SN/A // we shouldn't get a retry unless we have a packet that we're 10042623SN/A // waiting to transmit 10052623SN/A assert(cpu->dcache_pkt != NULL); 10062623SN/A assert(cpu->_status == DcacheRetry); 10073349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 10085728Sgblack@eecs.umich.edu if (tmp->senderState) { 10095728Sgblack@eecs.umich.edu // This is a packet from a split access. 10105728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 10115728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 10125728Sgblack@eecs.umich.edu assert(send_state); 10135728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 10145728Sgblack@eecs.umich.edu 10155728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 10165728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 10175728Sgblack@eecs.umich.edu assert(main_send_state); 10185728Sgblack@eecs.umich.edu 10195728Sgblack@eecs.umich.edu if (sendTiming(tmp)) { 10205728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 10215728Sgblack@eecs.umich.edu // and try sending the other fragment. 10225728Sgblack@eecs.umich.edu send_state->clearFromParent(); 10235728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 10245728Sgblack@eecs.umich.edu if (other_index > 0) { 10255728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 10265728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 10275728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 10285728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 10295728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 10305728Sgblack@eecs.umich.edu } 10315728Sgblack@eecs.umich.edu } else { 10325728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 10335728Sgblack@eecs.umich.edu // memory system takes ownership of packet 10345728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 10355728Sgblack@eecs.umich.edu } 10365728Sgblack@eecs.umich.edu } 10375728Sgblack@eecs.umich.edu } else if (sendTiming(tmp)) { 10382657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 10393170Sstever@eecs.umich.edu // memory system takes ownership of packet 10402657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 10412657Ssaidi@eecs.umich.edu } 10422623SN/A} 10432623SN/A 10445606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 10455606Snate@binkert.org Tick t) 10465606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 10475103Ssaidi@eecs.umich.edu{ 10485606Snate@binkert.org cpu->schedule(this, t); 10495103Ssaidi@eecs.umich.edu} 10505103Ssaidi@eecs.umich.edu 10515103Ssaidi@eecs.umich.eduvoid 10525103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 10535103Ssaidi@eecs.umich.edu{ 10545103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 10555103Ssaidi@eecs.umich.edu} 10565103Ssaidi@eecs.umich.edu 10575103Ssaidi@eecs.umich.educonst char * 10585336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 10595103Ssaidi@eecs.umich.edu{ 10605103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 10615103Ssaidi@eecs.umich.edu} 10625103Ssaidi@eecs.umich.edu 10632623SN/A 10645315Sstever@gmail.comvoid 10655315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 10665315Sstever@gmail.com{ 10675315Sstever@gmail.com dcachePort.printAddr(a); 10685315Sstever@gmail.com} 10695315Sstever@gmail.com 10705315Sstever@gmail.com 10712623SN/A//////////////////////////////////////////////////////////////////////// 10722623SN/A// 10732623SN/A// TimingSimpleCPU Simulation Object 10742623SN/A// 10754762Snate@binkert.orgTimingSimpleCPU * 10764762Snate@binkert.orgTimingSimpleCPUParams::create() 10772623SN/A{ 10785529Snate@binkert.org numThreads = 1; 10795529Snate@binkert.org#if !FULL_SYSTEM 10804762Snate@binkert.org if (workload.size() != 1) 10814762Snate@binkert.org panic("only one workload allowed"); 10822623SN/A#endif 10835529Snate@binkert.org return new TimingSimpleCPU(this); 10842623SN/A} 1085