timing.cc revision 5669
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 325103Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh" 332623SN/A#include "arch/utility.hh" 344040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 352623SN/A#include "cpu/exetrace.hh" 362623SN/A#include "cpu/simple/timing.hh" 373348Sbinkertn@umich.edu#include "mem/packet.hh" 383348Sbinkertn@umich.edu#include "mem/packet_access.hh" 394762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 402901Ssaidi@eecs.umich.edu#include "sim/system.hh" 412623SN/A 422623SN/Ausing namespace std; 432623SN/Ausing namespace TheISA; 442623SN/A 452856Srdreslin@umich.eduPort * 462856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 472856Srdreslin@umich.edu{ 482856Srdreslin@umich.edu if (if_name == "dcache_port") 492856Srdreslin@umich.edu return &dcachePort; 502856Srdreslin@umich.edu else if (if_name == "icache_port") 512856Srdreslin@umich.edu return &icachePort; 522856Srdreslin@umich.edu else 532856Srdreslin@umich.edu panic("No Such Port\n"); 542856Srdreslin@umich.edu} 552623SN/A 562623SN/Avoid 572623SN/ATimingSimpleCPU::init() 582623SN/A{ 592623SN/A BaseCPU::init(); 605310Ssaidi@eecs.umich.edu cpuId = tc->readCpuId(); 612623SN/A#if FULL_SYSTEM 622680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 632680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 642623SN/A 652623SN/A // initialize CPU, including PC 665310Ssaidi@eecs.umich.edu TheISA::initCPU(tc, cpuId); 672623SN/A } 682623SN/A#endif 692623SN/A} 702623SN/A 712623SN/ATick 723349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 732623SN/A{ 742623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 752623SN/A return curTick; 762623SN/A} 772623SN/A 782623SN/Avoid 793349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 802623SN/A{ 813184Srdreslin@umich.edu //No internal storage to update, jusst return 823184Srdreslin@umich.edu return; 832623SN/A} 842623SN/A 852623SN/Avoid 862623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 872623SN/A{ 883647Srdreslin@umich.edu if (status == RangeChange) { 893647Srdreslin@umich.edu if (!snoopRangeSent) { 903647Srdreslin@umich.edu snoopRangeSent = true; 913647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 923647Srdreslin@umich.edu } 932631SN/A return; 943647Srdreslin@umich.edu } 952631SN/A 962623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 972623SN/A} 982623SN/A 992948Ssaidi@eecs.umich.edu 1002948Ssaidi@eecs.umich.eduvoid 1013349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1022948Ssaidi@eecs.umich.edu{ 1032948Ssaidi@eecs.umich.edu pkt = _pkt; 1045606Snate@binkert.org cpu->schedule(this, t); 1052948Ssaidi@eecs.umich.edu} 1062948Ssaidi@eecs.umich.edu 1075529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 1085169Ssaidi@eecs.umich.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock) 1092623SN/A{ 1102623SN/A _status = Idle; 1113647Srdreslin@umich.edu 1123647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1133647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1143647Srdreslin@umich.edu 1152623SN/A ifetch_pkt = dcache_pkt = NULL; 1162839Sktlim@umich.edu drainEvent = NULL; 1172867Sktlim@umich.edu fetchEvent = NULL; 1183222Sktlim@umich.edu previousTick = 0; 1192901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1202623SN/A} 1212623SN/A 1222623SN/A 1232623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1242623SN/A{ 1252623SN/A} 1262623SN/A 1272623SN/Avoid 1282623SN/ATimingSimpleCPU::serialize(ostream &os) 1292623SN/A{ 1302915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1312915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1322623SN/A BaseSimpleCPU::serialize(os); 1332623SN/A} 1342623SN/A 1352623SN/Avoid 1362623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1372623SN/A{ 1382915Sktlim@umich.edu SimObject::State so_state; 1392915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1402623SN/A BaseSimpleCPU::unserialize(cp, section); 1412798Sktlim@umich.edu} 1422798Sktlim@umich.edu 1432901Ssaidi@eecs.umich.eduunsigned int 1442839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1452798Sktlim@umich.edu{ 1462839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1472798Sktlim@umich.edu // an access to complete. 1485496Ssaidi@eecs.umich.edu if (_status == Idle || _status == Running || _status == SwitchedOut) { 1492901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1502901Ssaidi@eecs.umich.edu return 0; 1512798Sktlim@umich.edu } else { 1522839Sktlim@umich.edu changeState(SimObject::Draining); 1532839Sktlim@umich.edu drainEvent = drain_event; 1542901Ssaidi@eecs.umich.edu return 1; 1552798Sktlim@umich.edu } 1562623SN/A} 1572623SN/A 1582623SN/Avoid 1592798Sktlim@umich.eduTimingSimpleCPU::resume() 1602623SN/A{ 1615221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1622798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1634762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1643201Shsul@eecs.umich.edu 1652867Sktlim@umich.edu // Delete the old event if it existed. 1662867Sktlim@umich.edu if (fetchEvent) { 1672915Sktlim@umich.edu if (fetchEvent->scheduled()) 1685606Snate@binkert.org deschedule(fetchEvent); 1692915Sktlim@umich.edu 1702867Sktlim@umich.edu delete fetchEvent; 1712867Sktlim@umich.edu } 1722867Sktlim@umich.edu 1734471Sstever@eecs.umich.edu fetchEvent = new FetchEvent(this, nextCycle()); 1742623SN/A } 1752798Sktlim@umich.edu 1762901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1772798Sktlim@umich.edu} 1782798Sktlim@umich.edu 1792798Sktlim@umich.eduvoid 1802798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1812798Sktlim@umich.edu{ 1825496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 1832798Sktlim@umich.edu _status = SwitchedOut; 1845099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 1852867Sktlim@umich.edu 1862867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1872867Sktlim@umich.edu // we'll need to cancel it. 1882867Sktlim@umich.edu if (fetchEvent && fetchEvent->scheduled()) 1895606Snate@binkert.org deschedule(fetchEvent); 1902623SN/A} 1912623SN/A 1922623SN/A 1932623SN/Avoid 1942623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1952623SN/A{ 1964192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 1972623SN/A 1982680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1992623SN/A // running and schedule its tick event. 2002680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2012680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2022680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2032623SN/A _status = Running; 2042623SN/A break; 2052623SN/A } 2062623SN/A } 2073201Shsul@eecs.umich.edu 2083201Shsul@eecs.umich.edu if (_status != Running) { 2093201Shsul@eecs.umich.edu _status = Idle; 2103201Shsul@eecs.umich.edu } 2115169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2125169Ssaidi@eecs.umich.edu cpuId = tc->readCpuId(); 2135101Ssaidi@eecs.umich.edu previousTick = curTick; 2142623SN/A} 2152623SN/A 2162623SN/A 2172623SN/Avoid 2182623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2192623SN/A{ 2205221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2215221Ssaidi@eecs.umich.edu 2222623SN/A assert(thread_num == 0); 2232683Sktlim@umich.edu assert(thread); 2242623SN/A 2252623SN/A assert(_status == Idle); 2262623SN/A 2272623SN/A notIdleFraction++; 2282623SN/A _status = Running; 2293686Sktlim@umich.edu 2302623SN/A // kick things off by initiating the fetch of the next instruction 2315606Snate@binkert.org fetchEvent = new FetchEvent(this); 2325606Snate@binkert.org schedule(fetchEvent, nextCycle(curTick + ticks(delay))); 2332623SN/A} 2342623SN/A 2352623SN/A 2362623SN/Avoid 2372623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2382623SN/A{ 2395221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2405221Ssaidi@eecs.umich.edu 2412623SN/A assert(thread_num == 0); 2422683Sktlim@umich.edu assert(thread); 2432623SN/A 2442644Sstever@eecs.umich.edu assert(_status == Running); 2452623SN/A 2462644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2472644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2482623SN/A 2492623SN/A notIdleFraction--; 2502623SN/A _status = Idle; 2512623SN/A} 2522623SN/A 2532623SN/A 2542623SN/Atemplate <class T> 2552623SN/AFault 2562623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2572623SN/A{ 2583169Sstever@eecs.umich.edu Request *req = 2593169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 2605169Ssaidi@eecs.umich.edu cpuId, /* thread ID */ 0); 2612623SN/A 2622623SN/A if (traceData) { 2633169Sstever@eecs.umich.edu traceData->setAddr(req->getVaddr()); 2642623SN/A } 2652623SN/A 2662623SN/A // translate to physical address 2673169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2682623SN/A 2692623SN/A // Now do the access. 2702623SN/A if (fault == NoFault) { 2713349Sbinkertn@umich.edu PacketPtr pkt = 2724878Sstever@eecs.umich.edu new Packet(req, 2734878Sstever@eecs.umich.edu (req->isLocked() ? 2744878Sstever@eecs.umich.edu MemCmd::LoadLockedReq : MemCmd::ReadReq), 2754878Sstever@eecs.umich.edu Packet::Broadcast); 2763169Sstever@eecs.umich.edu pkt->dataDynamic<T>(new T); 2772623SN/A 2785103Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) { 2795103Ssaidi@eecs.umich.edu Tick delay; 2805103Ssaidi@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2815103Ssaidi@eecs.umich.edu new IprEvent(pkt, this, nextCycle(curTick + delay)); 2825103Ssaidi@eecs.umich.edu _status = DcacheWaitResponse; 2835103Ssaidi@eecs.umich.edu dcache_pkt = NULL; 2845103Ssaidi@eecs.umich.edu } else if (!dcachePort.sendTiming(pkt)) { 2852623SN/A _status = DcacheRetry; 2863169Sstever@eecs.umich.edu dcache_pkt = pkt; 2872623SN/A } else { 2882623SN/A _status = DcacheWaitResponse; 2893169Sstever@eecs.umich.edu // memory system takes ownership of packet 2902623SN/A dcache_pkt = NULL; 2912623SN/A } 2924200Ssaidi@eecs.umich.edu 2934200Ssaidi@eecs.umich.edu // This will need a new way to tell if it has a dcache attached. 2944200Ssaidi@eecs.umich.edu if (req->isUncacheable()) 2954200Ssaidi@eecs.umich.edu recordEvent("Uncached Read"); 2963658Sktlim@umich.edu } else { 2973658Sktlim@umich.edu delete req; 2982623SN/A } 2992623SN/A 3005408Sgblack@eecs.umich.edu if (traceData) { 3015408Sgblack@eecs.umich.edu traceData->setData(data); 3025408Sgblack@eecs.umich.edu } 3032623SN/A return fault; 3042623SN/A} 3052623SN/A 3065177Sgblack@eecs.umich.eduFault 3075177Sgblack@eecs.umich.eduTimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr, 3085177Sgblack@eecs.umich.edu int size, unsigned flags) 3095177Sgblack@eecs.umich.edu{ 3105177Sgblack@eecs.umich.edu Request *req = 3115177Sgblack@eecs.umich.edu new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0); 3125177Sgblack@eecs.umich.edu 3135177Sgblack@eecs.umich.edu if (traceData) { 3145177Sgblack@eecs.umich.edu traceData->setAddr(vaddr); 3155177Sgblack@eecs.umich.edu } 3165177Sgblack@eecs.umich.edu 3175177Sgblack@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3185177Sgblack@eecs.umich.edu 3195177Sgblack@eecs.umich.edu if (fault == NoFault) 3205177Sgblack@eecs.umich.edu paddr = req->getPaddr(); 3215177Sgblack@eecs.umich.edu 3225177Sgblack@eecs.umich.edu delete req; 3235177Sgblack@eecs.umich.edu return fault; 3245177Sgblack@eecs.umich.edu} 3255177Sgblack@eecs.umich.edu 3262623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3272623SN/A 3282623SN/Atemplate 3292623SN/AFault 3304040Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 3314040Ssaidi@eecs.umich.edu 3324040Ssaidi@eecs.umich.edutemplate 3334040Ssaidi@eecs.umich.eduFault 3344115Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 3354115Ssaidi@eecs.umich.edu 3364115Ssaidi@eecs.umich.edutemplate 3374115Ssaidi@eecs.umich.eduFault 3382623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 3392623SN/A 3402623SN/Atemplate 3412623SN/AFault 3422623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3432623SN/A 3442623SN/Atemplate 3452623SN/AFault 3462623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 3472623SN/A 3482623SN/Atemplate 3492623SN/AFault 3502623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3512623SN/A 3522623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3532623SN/A 3542623SN/Atemplate<> 3552623SN/AFault 3562623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 3572623SN/A{ 3582623SN/A return read(addr, *(uint64_t*)&data, flags); 3592623SN/A} 3602623SN/A 3612623SN/Atemplate<> 3622623SN/AFault 3632623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 3642623SN/A{ 3652623SN/A return read(addr, *(uint32_t*)&data, flags); 3662623SN/A} 3672623SN/A 3682623SN/A 3692623SN/Atemplate<> 3702623SN/AFault 3712623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3722623SN/A{ 3732623SN/A return read(addr, (uint32_t&)data, flags); 3742623SN/A} 3752623SN/A 3762623SN/A 3772623SN/Atemplate <class T> 3782623SN/AFault 3792623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3802623SN/A{ 3813169Sstever@eecs.umich.edu Request *req = 3823169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 3835169Ssaidi@eecs.umich.edu cpuId, /* thread ID */ 0); 3842623SN/A 3854040Ssaidi@eecs.umich.edu if (traceData) { 3864040Ssaidi@eecs.umich.edu traceData->setAddr(req->getVaddr()); 3874040Ssaidi@eecs.umich.edu } 3884040Ssaidi@eecs.umich.edu 3892623SN/A // translate to physical address 3903169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3913169Sstever@eecs.umich.edu 3922623SN/A // Now do the access. 3932623SN/A if (fault == NoFault) { 3944878Sstever@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 3953170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3963170Sstever@eecs.umich.edu 3973170Sstever@eecs.umich.edu if (req->isLocked()) { 3984878Sstever@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3993170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 4004878Sstever@eecs.umich.edu } else if (req->isSwap()) { 4014878Sstever@eecs.umich.edu cmd = MemCmd::SwapReq; 4024878Sstever@eecs.umich.edu if (req->isCondSwap()) { 4034878Sstever@eecs.umich.edu assert(res); 4044878Sstever@eecs.umich.edu req->setExtraData(*res); 4054878Sstever@eecs.umich.edu } 4063170Sstever@eecs.umich.edu } 4074584Ssaidi@eecs.umich.edu 4084881Sstever@eecs.umich.edu // Note: need to allocate dcache_pkt even if do_access is 4094881Sstever@eecs.umich.edu // false, as it's used unconditionally to call completeAcc(). 4104881Sstever@eecs.umich.edu assert(dcache_pkt == NULL); 4114881Sstever@eecs.umich.edu dcache_pkt = new Packet(req, cmd, Packet::Broadcast); 4124881Sstever@eecs.umich.edu dcache_pkt->allocate(); 4134881Sstever@eecs.umich.edu dcache_pkt->set(data); 4143170Sstever@eecs.umich.edu 4153170Sstever@eecs.umich.edu if (do_access) { 4165103Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) { 4175103Ssaidi@eecs.umich.edu Tick delay; 4185103Ssaidi@eecs.umich.edu dcache_pkt->set(htog(data)); 4195103Ssaidi@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4205103Ssaidi@eecs.umich.edu new IprEvent(dcache_pkt, this, nextCycle(curTick + delay)); 4215103Ssaidi@eecs.umich.edu _status = DcacheWaitResponse; 4225103Ssaidi@eecs.umich.edu dcache_pkt = NULL; 4235103Ssaidi@eecs.umich.edu } else if (!dcachePort.sendTiming(dcache_pkt)) { 4243170Sstever@eecs.umich.edu _status = DcacheRetry; 4253170Sstever@eecs.umich.edu } else { 4263170Sstever@eecs.umich.edu _status = DcacheWaitResponse; 4273170Sstever@eecs.umich.edu // memory system takes ownership of packet 4283170Sstever@eecs.umich.edu dcache_pkt = NULL; 4293170Sstever@eecs.umich.edu } 4302623SN/A } 4314200Ssaidi@eecs.umich.edu // This will need a new way to tell if it's hooked up to a cache or not. 4324200Ssaidi@eecs.umich.edu if (req->isUncacheable()) 4334200Ssaidi@eecs.umich.edu recordEvent("Uncached Write"); 4343658Sktlim@umich.edu } else { 4353658Sktlim@umich.edu delete req; 4362623SN/A } 4372623SN/A 4385408Sgblack@eecs.umich.edu if (traceData) { 4395408Sgblack@eecs.umich.edu traceData->setData(data); 4405408Sgblack@eecs.umich.edu } 4412623SN/A 4422623SN/A // If the write needs to have a fault on the access, consider calling 4432623SN/A // changeStatus() and changing it to "bad addr write" or something. 4442623SN/A return fault; 4452623SN/A} 4462623SN/A 4475177Sgblack@eecs.umich.eduFault 4485177Sgblack@eecs.umich.eduTimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr, 4495177Sgblack@eecs.umich.edu int size, unsigned flags) 4505177Sgblack@eecs.umich.edu{ 4515177Sgblack@eecs.umich.edu Request *req = 4525177Sgblack@eecs.umich.edu new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0); 4535177Sgblack@eecs.umich.edu 4545177Sgblack@eecs.umich.edu if (traceData) { 4555177Sgblack@eecs.umich.edu traceData->setAddr(vaddr); 4565177Sgblack@eecs.umich.edu } 4575177Sgblack@eecs.umich.edu 4585177Sgblack@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 4595177Sgblack@eecs.umich.edu 4605177Sgblack@eecs.umich.edu if (fault == NoFault) 4615177Sgblack@eecs.umich.edu paddr = req->getPaddr(); 4625177Sgblack@eecs.umich.edu 4635177Sgblack@eecs.umich.edu delete req; 4645177Sgblack@eecs.umich.edu return fault; 4655177Sgblack@eecs.umich.edu} 4665177Sgblack@eecs.umich.edu 4672623SN/A 4682623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4692623SN/Atemplate 4702623SN/AFault 4714224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin32_t data, Addr addr, 4724224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4734224Sgblack@eecs.umich.edu 4744224Sgblack@eecs.umich.edutemplate 4754224Sgblack@eecs.umich.eduFault 4764224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin64_t data, Addr addr, 4774224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4784224Sgblack@eecs.umich.edu 4794224Sgblack@eecs.umich.edutemplate 4804224Sgblack@eecs.umich.eduFault 4812623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 4822623SN/A unsigned flags, uint64_t *res); 4832623SN/A 4842623SN/Atemplate 4852623SN/AFault 4862623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 4872623SN/A unsigned flags, uint64_t *res); 4882623SN/A 4892623SN/Atemplate 4902623SN/AFault 4912623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 4922623SN/A unsigned flags, uint64_t *res); 4932623SN/A 4942623SN/Atemplate 4952623SN/AFault 4962623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 4972623SN/A unsigned flags, uint64_t *res); 4982623SN/A 4992623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 5002623SN/A 5012623SN/Atemplate<> 5022623SN/AFault 5032623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 5042623SN/A{ 5052623SN/A return write(*(uint64_t*)&data, addr, flags, res); 5062623SN/A} 5072623SN/A 5082623SN/Atemplate<> 5092623SN/AFault 5102623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 5112623SN/A{ 5122623SN/A return write(*(uint32_t*)&data, addr, flags, res); 5132623SN/A} 5142623SN/A 5152623SN/A 5162623SN/Atemplate<> 5172623SN/AFault 5182623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 5192623SN/A{ 5202623SN/A return write((uint32_t)data, addr, flags, res); 5212623SN/A} 5222623SN/A 5232623SN/A 5242623SN/Avoid 5252623SN/ATimingSimpleCPU::fetch() 5262623SN/A{ 5275221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5285221Ssaidi@eecs.umich.edu 5293387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5303387Sgblack@eecs.umich.edu checkForInterrupts(); 5312631SN/A 5325348Ssaidi@eecs.umich.edu checkPcEventQueue(); 5335348Ssaidi@eecs.umich.edu 5345669Sgblack@eecs.umich.edu bool fromRom = isRomMicroPC(thread->readMicroPC()); 5352623SN/A 5365669Sgblack@eecs.umich.edu if (!fromRom) { 5375669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 5385669Sgblack@eecs.umich.edu ifetch_req->setThreadContext(cpuId, /* thread ID */ 0); 5395669Sgblack@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 5402623SN/A 5415669Sgblack@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast); 5425669Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 5435669Sgblack@eecs.umich.edu 5445669Sgblack@eecs.umich.edu if (fault == NoFault) { 5455669Sgblack@eecs.umich.edu if (!icachePort.sendTiming(ifetch_pkt)) { 5465669Sgblack@eecs.umich.edu // Need to wait for retry 5475669Sgblack@eecs.umich.edu _status = IcacheRetry; 5485669Sgblack@eecs.umich.edu } else { 5495669Sgblack@eecs.umich.edu // Need to wait for cache to respond 5505669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5515669Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 5525669Sgblack@eecs.umich.edu ifetch_pkt = NULL; 5535669Sgblack@eecs.umich.edu } 5542623SN/A } else { 5555669Sgblack@eecs.umich.edu delete ifetch_req; 5565669Sgblack@eecs.umich.edu delete ifetch_pkt; 5575669Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 5585669Sgblack@eecs.umich.edu advanceInst(fault); 5592623SN/A } 5602623SN/A } else { 5615669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5625669Sgblack@eecs.umich.edu completeIfetch(NULL); 5632623SN/A } 5643222Sktlim@umich.edu 5655099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 5663222Sktlim@umich.edu previousTick = curTick; 5672623SN/A} 5682623SN/A 5692623SN/A 5702623SN/Avoid 5712644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 5722623SN/A{ 5732623SN/A advancePC(fault); 5742623SN/A 5752631SN/A if (_status == Running) { 5762631SN/A // kick off fetch of next instruction... callback from icache 5772631SN/A // response will cause that instruction to be executed, 5782631SN/A // keeping the CPU running. 5792631SN/A fetch(); 5802631SN/A } 5812623SN/A} 5822623SN/A 5832623SN/A 5842623SN/Avoid 5853349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 5862623SN/A{ 5875221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Complete ICache Fetch\n"); 5885221Ssaidi@eecs.umich.edu 5892623SN/A // received a response from the icache: execute the received 5902623SN/A // instruction 5915669Sgblack@eecs.umich.edu 5925669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 5932623SN/A assert(_status == IcacheWaitResponse); 5942798Sktlim@umich.edu 5952623SN/A _status = Running; 5962644Sstever@eecs.umich.edu 5975099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 5983222Sktlim@umich.edu previousTick = curTick; 5993222Sktlim@umich.edu 6002839Sktlim@umich.edu if (getState() == SimObject::Draining) { 6015669Sgblack@eecs.umich.edu if (pkt) { 6025669Sgblack@eecs.umich.edu delete pkt->req; 6035669Sgblack@eecs.umich.edu delete pkt; 6045669Sgblack@eecs.umich.edu } 6053658Sktlim@umich.edu 6062839Sktlim@umich.edu completeDrain(); 6072798Sktlim@umich.edu return; 6082798Sktlim@umich.edu } 6092798Sktlim@umich.edu 6102623SN/A preExecute(); 6112644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 6122623SN/A // load or store: just send to dcache 6132623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 6143170Sstever@eecs.umich.edu if (_status != Running) { 6153170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 6163170Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DcacheRetry); 6173170Sstever@eecs.umich.edu assert(fault == NoFault); 6182644Sstever@eecs.umich.edu } else { 6193170Sstever@eecs.umich.edu if (fault == NoFault) { 6205335Shines@cs.fsu.edu // Note that ARM can have NULL packets if the instruction gets 6215335Shines@cs.fsu.edu // squashed due to predication 6223170Sstever@eecs.umich.edu // early fail on store conditional: complete now 6235335Shines@cs.fsu.edu assert(dcache_pkt != NULL || THE_ISA == ARM_ISA); 6245335Shines@cs.fsu.edu 6253170Sstever@eecs.umich.edu fault = curStaticInst->completeAcc(dcache_pkt, this, 6263170Sstever@eecs.umich.edu traceData); 6275335Shines@cs.fsu.edu if (dcache_pkt != NULL) 6285335Shines@cs.fsu.edu { 6295335Shines@cs.fsu.edu delete dcache_pkt->req; 6305335Shines@cs.fsu.edu delete dcache_pkt; 6315335Shines@cs.fsu.edu dcache_pkt = NULL; 6325335Shines@cs.fsu.edu } 6334998Sgblack@eecs.umich.edu 6344998Sgblack@eecs.umich.edu // keep an instruction count 6354998Sgblack@eecs.umich.edu if (fault == NoFault) 6364998Sgblack@eecs.umich.edu countInst(); 6375001Sgblack@eecs.umich.edu } else if (traceData) { 6385001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6395001Sgblack@eecs.umich.edu delete traceData; 6405001Sgblack@eecs.umich.edu traceData = NULL; 6413170Sstever@eecs.umich.edu } 6424998Sgblack@eecs.umich.edu 6432644Sstever@eecs.umich.edu postExecute(); 6445103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6455103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6465103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6475103Ssaidi@eecs.umich.edu instCnt++; 6482644Sstever@eecs.umich.edu advanceInst(fault); 6492644Sstever@eecs.umich.edu } 6502623SN/A } else { 6512623SN/A // non-memory instruction: execute completely now 6522623SN/A Fault fault = curStaticInst->execute(this, traceData); 6534998Sgblack@eecs.umich.edu 6544998Sgblack@eecs.umich.edu // keep an instruction count 6554998Sgblack@eecs.umich.edu if (fault == NoFault) 6564998Sgblack@eecs.umich.edu countInst(); 6575001Sgblack@eecs.umich.edu else if (traceData) { 6585001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6595001Sgblack@eecs.umich.edu delete traceData; 6605001Sgblack@eecs.umich.edu traceData = NULL; 6615001Sgblack@eecs.umich.edu } 6624998Sgblack@eecs.umich.edu 6632644Sstever@eecs.umich.edu postExecute(); 6645103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6655103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6665103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6675103Ssaidi@eecs.umich.edu instCnt++; 6682644Sstever@eecs.umich.edu advanceInst(fault); 6692623SN/A } 6703658Sktlim@umich.edu 6715669Sgblack@eecs.umich.edu if (pkt) { 6725669Sgblack@eecs.umich.edu delete pkt->req; 6735669Sgblack@eecs.umich.edu delete pkt; 6745669Sgblack@eecs.umich.edu } 6752623SN/A} 6762623SN/A 6772948Ssaidi@eecs.umich.eduvoid 6782948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 6792948Ssaidi@eecs.umich.edu{ 6802948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 6812948Ssaidi@eecs.umich.edu} 6822623SN/A 6832623SN/Abool 6843349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 6852623SN/A{ 6864986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 6873310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 6884584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 6892948Ssaidi@eecs.umich.edu 6903495Sktlim@umich.edu if (next_tick == curTick) 6913310Srdreslin@umich.edu cpu->completeIfetch(pkt); 6923310Srdreslin@umich.edu else 6933495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 6942948Ssaidi@eecs.umich.edu 6953310Srdreslin@umich.edu return true; 6963310Srdreslin@umich.edu } 6974870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 6984433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 6994433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 7004433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 7014433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 7024433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 7034433Ssaidi@eecs.umich.edu } 7043310Srdreslin@umich.edu } 7054433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 7064433Ssaidi@eecs.umich.edu return true; 7072623SN/A} 7082623SN/A 7092657Ssaidi@eecs.umich.eduvoid 7102623SN/ATimingSimpleCPU::IcachePort::recvRetry() 7112623SN/A{ 7122623SN/A // we shouldn't get a retry unless we have a packet that we're 7132623SN/A // waiting to transmit 7142623SN/A assert(cpu->ifetch_pkt != NULL); 7152623SN/A assert(cpu->_status == IcacheRetry); 7163349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7172657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 7182657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7192657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7202657Ssaidi@eecs.umich.edu } 7212623SN/A} 7222623SN/A 7232623SN/Avoid 7243349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 7252623SN/A{ 7262623SN/A // received a response from the dcache: complete the load or store 7272623SN/A // instruction 7284870Sstever@eecs.umich.edu assert(!pkt->isError()); 7292623SN/A assert(_status == DcacheWaitResponse); 7302623SN/A _status = Running; 7312623SN/A 7325099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 7333222Sktlim@umich.edu previousTick = curTick; 7343184Srdreslin@umich.edu 7352623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 7362623SN/A 7374998Sgblack@eecs.umich.edu // keep an instruction count 7384998Sgblack@eecs.umich.edu if (fault == NoFault) 7394998Sgblack@eecs.umich.edu countInst(); 7405001Sgblack@eecs.umich.edu else if (traceData) { 7415001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7425001Sgblack@eecs.umich.edu delete traceData; 7435001Sgblack@eecs.umich.edu traceData = NULL; 7445001Sgblack@eecs.umich.edu } 7454998Sgblack@eecs.umich.edu 7465507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 7475507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 7485507Sstever@gmail.com if (pkt->isRead() && pkt->req->isLocked()) { 7493170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 7503170Sstever@eecs.umich.edu } 7513170Sstever@eecs.umich.edu 7522644Sstever@eecs.umich.edu delete pkt->req; 7532644Sstever@eecs.umich.edu delete pkt; 7542644Sstever@eecs.umich.edu 7553184Srdreslin@umich.edu postExecute(); 7563227Sktlim@umich.edu 7573201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 7583201Shsul@eecs.umich.edu advancePC(fault); 7593201Shsul@eecs.umich.edu completeDrain(); 7603201Shsul@eecs.umich.edu 7613201Shsul@eecs.umich.edu return; 7623201Shsul@eecs.umich.edu } 7633201Shsul@eecs.umich.edu 7642644Sstever@eecs.umich.edu advanceInst(fault); 7652623SN/A} 7662623SN/A 7672623SN/A 7682798Sktlim@umich.eduvoid 7692839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 7702798Sktlim@umich.edu{ 7712839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 7722901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 7732839Sktlim@umich.edu drainEvent->process(); 7742798Sktlim@umich.edu} 7752623SN/A 7764192Sktlim@umich.eduvoid 7774192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 7784192Sktlim@umich.edu{ 7794192Sktlim@umich.edu Port::setPeer(port); 7804192Sktlim@umich.edu 7814192Sktlim@umich.edu#if FULL_SYSTEM 7824192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 7834192Sktlim@umich.edu // Ports) 7845497Ssaidi@eecs.umich.edu cpu->tcBase()->connectMemPorts(cpu->tcBase()); 7854192Sktlim@umich.edu#endif 7864192Sktlim@umich.edu} 7874192Sktlim@umich.edu 7882623SN/Abool 7893349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 7902623SN/A{ 7914986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 7923310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 7934584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 7942948Ssaidi@eecs.umich.edu 7953495Sktlim@umich.edu if (next_tick == curTick) 7963310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 7973310Srdreslin@umich.edu else 7983495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 7992948Ssaidi@eecs.umich.edu 8003310Srdreslin@umich.edu return true; 8013310Srdreslin@umich.edu } 8024870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 8034433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 8044433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 8054433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 8064433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 8074433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 8084433Ssaidi@eecs.umich.edu } 8093310Srdreslin@umich.edu } 8104433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 8114433Ssaidi@eecs.umich.edu return true; 8122948Ssaidi@eecs.umich.edu} 8132948Ssaidi@eecs.umich.edu 8142948Ssaidi@eecs.umich.eduvoid 8152948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 8162948Ssaidi@eecs.umich.edu{ 8172630SN/A cpu->completeDataAccess(pkt); 8182623SN/A} 8192623SN/A 8202657Ssaidi@eecs.umich.eduvoid 8212623SN/ATimingSimpleCPU::DcachePort::recvRetry() 8222623SN/A{ 8232623SN/A // we shouldn't get a retry unless we have a packet that we're 8242623SN/A // waiting to transmit 8252623SN/A assert(cpu->dcache_pkt != NULL); 8262623SN/A assert(cpu->_status == DcacheRetry); 8273349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 8282657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 8292657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 8303170Sstever@eecs.umich.edu // memory system takes ownership of packet 8312657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 8322657Ssaidi@eecs.umich.edu } 8332623SN/A} 8342623SN/A 8355606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 8365606Snate@binkert.org Tick t) 8375606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 8385103Ssaidi@eecs.umich.edu{ 8395606Snate@binkert.org cpu->schedule(this, t); 8405103Ssaidi@eecs.umich.edu} 8415103Ssaidi@eecs.umich.edu 8425103Ssaidi@eecs.umich.eduvoid 8435103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 8445103Ssaidi@eecs.umich.edu{ 8455103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 8465103Ssaidi@eecs.umich.edu} 8475103Ssaidi@eecs.umich.edu 8485103Ssaidi@eecs.umich.educonst char * 8495336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 8505103Ssaidi@eecs.umich.edu{ 8515103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 8525103Ssaidi@eecs.umich.edu} 8535103Ssaidi@eecs.umich.edu 8542623SN/A 8555315Sstever@gmail.comvoid 8565315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 8575315Sstever@gmail.com{ 8585315Sstever@gmail.com dcachePort.printAddr(a); 8595315Sstever@gmail.com} 8605315Sstever@gmail.com 8615315Sstever@gmail.com 8622623SN/A//////////////////////////////////////////////////////////////////////// 8632623SN/A// 8642623SN/A// TimingSimpleCPU Simulation Object 8652623SN/A// 8664762Snate@binkert.orgTimingSimpleCPU * 8674762Snate@binkert.orgTimingSimpleCPUParams::create() 8682623SN/A{ 8695529Snate@binkert.org numThreads = 1; 8705529Snate@binkert.org#if !FULL_SYSTEM 8714762Snate@binkert.org if (workload.size() != 1) 8724762Snate@binkert.org panic("only one workload allowed"); 8732623SN/A#endif 8745529Snate@binkert.org return new TimingSimpleCPU(this); 8752623SN/A} 876