timing.cc revision 5529
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 325103Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh" 332623SN/A#include "arch/utility.hh" 344040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 352623SN/A#include "cpu/exetrace.hh" 362623SN/A#include "cpu/simple/timing.hh" 373348Sbinkertn@umich.edu#include "mem/packet.hh" 383348Sbinkertn@umich.edu#include "mem/packet_access.hh" 394762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 402901Ssaidi@eecs.umich.edu#include "sim/system.hh" 412623SN/A 422623SN/Ausing namespace std; 432623SN/Ausing namespace TheISA; 442623SN/A 452856Srdreslin@umich.eduPort * 462856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 472856Srdreslin@umich.edu{ 482856Srdreslin@umich.edu if (if_name == "dcache_port") 492856Srdreslin@umich.edu return &dcachePort; 502856Srdreslin@umich.edu else if (if_name == "icache_port") 512856Srdreslin@umich.edu return &icachePort; 522856Srdreslin@umich.edu else 532856Srdreslin@umich.edu panic("No Such Port\n"); 542856Srdreslin@umich.edu} 552623SN/A 562623SN/Avoid 572623SN/ATimingSimpleCPU::init() 582623SN/A{ 592623SN/A BaseCPU::init(); 605310Ssaidi@eecs.umich.edu cpuId = tc->readCpuId(); 612623SN/A#if FULL_SYSTEM 622680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 632680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 642623SN/A 652623SN/A // initialize CPU, including PC 665310Ssaidi@eecs.umich.edu TheISA::initCPU(tc, cpuId); 672623SN/A } 682623SN/A#endif 692623SN/A} 702623SN/A 712623SN/ATick 723349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 732623SN/A{ 742623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 752623SN/A return curTick; 762623SN/A} 772623SN/A 782623SN/Avoid 793349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 802623SN/A{ 813184Srdreslin@umich.edu //No internal storage to update, jusst return 823184Srdreslin@umich.edu return; 832623SN/A} 842623SN/A 852623SN/Avoid 862623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 872623SN/A{ 883647Srdreslin@umich.edu if (status == RangeChange) { 893647Srdreslin@umich.edu if (!snoopRangeSent) { 903647Srdreslin@umich.edu snoopRangeSent = true; 913647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 923647Srdreslin@umich.edu } 932631SN/A return; 943647Srdreslin@umich.edu } 952631SN/A 962623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 972623SN/A} 982623SN/A 992948Ssaidi@eecs.umich.edu 1002948Ssaidi@eecs.umich.eduvoid 1013349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1022948Ssaidi@eecs.umich.edu{ 1032948Ssaidi@eecs.umich.edu pkt = _pkt; 1042948Ssaidi@eecs.umich.edu Event::schedule(t); 1052948Ssaidi@eecs.umich.edu} 1062948Ssaidi@eecs.umich.edu 1075529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 1085169Ssaidi@eecs.umich.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock) 1092623SN/A{ 1102623SN/A _status = Idle; 1113647Srdreslin@umich.edu 1123647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1133647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1143647Srdreslin@umich.edu 1152623SN/A ifetch_pkt = dcache_pkt = NULL; 1162839Sktlim@umich.edu drainEvent = NULL; 1172867Sktlim@umich.edu fetchEvent = NULL; 1183222Sktlim@umich.edu previousTick = 0; 1192901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1202623SN/A} 1212623SN/A 1222623SN/A 1232623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1242623SN/A{ 1252623SN/A} 1262623SN/A 1272623SN/Avoid 1282623SN/ATimingSimpleCPU::serialize(ostream &os) 1292623SN/A{ 1302915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1312915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1322623SN/A BaseSimpleCPU::serialize(os); 1332623SN/A} 1342623SN/A 1352623SN/Avoid 1362623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1372623SN/A{ 1382915Sktlim@umich.edu SimObject::State so_state; 1392915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1402623SN/A BaseSimpleCPU::unserialize(cp, section); 1412798Sktlim@umich.edu} 1422798Sktlim@umich.edu 1432901Ssaidi@eecs.umich.eduunsigned int 1442839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1452798Sktlim@umich.edu{ 1462839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1472798Sktlim@umich.edu // an access to complete. 1485496Ssaidi@eecs.umich.edu if (_status == Idle || _status == Running || _status == SwitchedOut) { 1492901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1502901Ssaidi@eecs.umich.edu return 0; 1512798Sktlim@umich.edu } else { 1522839Sktlim@umich.edu changeState(SimObject::Draining); 1532839Sktlim@umich.edu drainEvent = drain_event; 1542901Ssaidi@eecs.umich.edu return 1; 1552798Sktlim@umich.edu } 1562623SN/A} 1572623SN/A 1582623SN/Avoid 1592798Sktlim@umich.eduTimingSimpleCPU::resume() 1602623SN/A{ 1615221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1622798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1634762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1643201Shsul@eecs.umich.edu 1652867Sktlim@umich.edu // Delete the old event if it existed. 1662867Sktlim@umich.edu if (fetchEvent) { 1672915Sktlim@umich.edu if (fetchEvent->scheduled()) 1682915Sktlim@umich.edu fetchEvent->deschedule(); 1692915Sktlim@umich.edu 1702867Sktlim@umich.edu delete fetchEvent; 1712867Sktlim@umich.edu } 1722867Sktlim@umich.edu 1734471Sstever@eecs.umich.edu fetchEvent = new FetchEvent(this, nextCycle()); 1742623SN/A } 1752798Sktlim@umich.edu 1762901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1772798Sktlim@umich.edu} 1782798Sktlim@umich.edu 1792798Sktlim@umich.eduvoid 1802798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1812798Sktlim@umich.edu{ 1825496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 1832798Sktlim@umich.edu _status = SwitchedOut; 1845099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 1852867Sktlim@umich.edu 1862867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1872867Sktlim@umich.edu // we'll need to cancel it. 1882867Sktlim@umich.edu if (fetchEvent && fetchEvent->scheduled()) 1892867Sktlim@umich.edu fetchEvent->deschedule(); 1902623SN/A} 1912623SN/A 1922623SN/A 1932623SN/Avoid 1942623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1952623SN/A{ 1964192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 1972623SN/A 1982680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1992623SN/A // running and schedule its tick event. 2002680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2012680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2022680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2032623SN/A _status = Running; 2042623SN/A break; 2052623SN/A } 2062623SN/A } 2073201Shsul@eecs.umich.edu 2083201Shsul@eecs.umich.edu if (_status != Running) { 2093201Shsul@eecs.umich.edu _status = Idle; 2103201Shsul@eecs.umich.edu } 2115169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2125169Ssaidi@eecs.umich.edu cpuId = tc->readCpuId(); 2135101Ssaidi@eecs.umich.edu previousTick = curTick; 2142623SN/A} 2152623SN/A 2162623SN/A 2172623SN/Avoid 2182623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2192623SN/A{ 2205221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2215221Ssaidi@eecs.umich.edu 2222623SN/A assert(thread_num == 0); 2232683Sktlim@umich.edu assert(thread); 2242623SN/A 2252623SN/A assert(_status == Idle); 2262623SN/A 2272623SN/A notIdleFraction++; 2282623SN/A _status = Running; 2293686Sktlim@umich.edu 2302623SN/A // kick things off by initiating the fetch of the next instruction 2315100Ssaidi@eecs.umich.edu fetchEvent = new FetchEvent(this, nextCycle(curTick + ticks(delay))); 2322623SN/A} 2332623SN/A 2342623SN/A 2352623SN/Avoid 2362623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2372623SN/A{ 2385221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2395221Ssaidi@eecs.umich.edu 2402623SN/A assert(thread_num == 0); 2412683Sktlim@umich.edu assert(thread); 2422623SN/A 2432644Sstever@eecs.umich.edu assert(_status == Running); 2442623SN/A 2452644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2462644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2472623SN/A 2482623SN/A notIdleFraction--; 2492623SN/A _status = Idle; 2502623SN/A} 2512623SN/A 2522623SN/A 2532623SN/Atemplate <class T> 2542623SN/AFault 2552623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2562623SN/A{ 2573169Sstever@eecs.umich.edu Request *req = 2583169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 2595169Ssaidi@eecs.umich.edu cpuId, /* thread ID */ 0); 2602623SN/A 2612623SN/A if (traceData) { 2623169Sstever@eecs.umich.edu traceData->setAddr(req->getVaddr()); 2632623SN/A } 2642623SN/A 2652623SN/A // translate to physical address 2663169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2672623SN/A 2682623SN/A // Now do the access. 2692623SN/A if (fault == NoFault) { 2703349Sbinkertn@umich.edu PacketPtr pkt = 2714878Sstever@eecs.umich.edu new Packet(req, 2724878Sstever@eecs.umich.edu (req->isLocked() ? 2734878Sstever@eecs.umich.edu MemCmd::LoadLockedReq : MemCmd::ReadReq), 2744878Sstever@eecs.umich.edu Packet::Broadcast); 2753169Sstever@eecs.umich.edu pkt->dataDynamic<T>(new T); 2762623SN/A 2775103Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) { 2785103Ssaidi@eecs.umich.edu Tick delay; 2795103Ssaidi@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2805103Ssaidi@eecs.umich.edu new IprEvent(pkt, this, nextCycle(curTick + delay)); 2815103Ssaidi@eecs.umich.edu _status = DcacheWaitResponse; 2825103Ssaidi@eecs.umich.edu dcache_pkt = NULL; 2835103Ssaidi@eecs.umich.edu } else if (!dcachePort.sendTiming(pkt)) { 2842623SN/A _status = DcacheRetry; 2853169Sstever@eecs.umich.edu dcache_pkt = pkt; 2862623SN/A } else { 2872623SN/A _status = DcacheWaitResponse; 2883169Sstever@eecs.umich.edu // memory system takes ownership of packet 2892623SN/A dcache_pkt = NULL; 2902623SN/A } 2914200Ssaidi@eecs.umich.edu 2924200Ssaidi@eecs.umich.edu // This will need a new way to tell if it has a dcache attached. 2934200Ssaidi@eecs.umich.edu if (req->isUncacheable()) 2944200Ssaidi@eecs.umich.edu recordEvent("Uncached Read"); 2953658Sktlim@umich.edu } else { 2963658Sktlim@umich.edu delete req; 2972623SN/A } 2982623SN/A 2995408Sgblack@eecs.umich.edu if (traceData) { 3005408Sgblack@eecs.umich.edu traceData->setData(data); 3015408Sgblack@eecs.umich.edu } 3022623SN/A return fault; 3032623SN/A} 3042623SN/A 3055177Sgblack@eecs.umich.eduFault 3065177Sgblack@eecs.umich.eduTimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr, 3075177Sgblack@eecs.umich.edu int size, unsigned flags) 3085177Sgblack@eecs.umich.edu{ 3095177Sgblack@eecs.umich.edu Request *req = 3105177Sgblack@eecs.umich.edu new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0); 3115177Sgblack@eecs.umich.edu 3125177Sgblack@eecs.umich.edu if (traceData) { 3135177Sgblack@eecs.umich.edu traceData->setAddr(vaddr); 3145177Sgblack@eecs.umich.edu } 3155177Sgblack@eecs.umich.edu 3165177Sgblack@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3175177Sgblack@eecs.umich.edu 3185177Sgblack@eecs.umich.edu if (fault == NoFault) 3195177Sgblack@eecs.umich.edu paddr = req->getPaddr(); 3205177Sgblack@eecs.umich.edu 3215177Sgblack@eecs.umich.edu delete req; 3225177Sgblack@eecs.umich.edu return fault; 3235177Sgblack@eecs.umich.edu} 3245177Sgblack@eecs.umich.edu 3252623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3262623SN/A 3272623SN/Atemplate 3282623SN/AFault 3294040Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 3304040Ssaidi@eecs.umich.edu 3314040Ssaidi@eecs.umich.edutemplate 3324040Ssaidi@eecs.umich.eduFault 3334115Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 3344115Ssaidi@eecs.umich.edu 3354115Ssaidi@eecs.umich.edutemplate 3364115Ssaidi@eecs.umich.eduFault 3372623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 3382623SN/A 3392623SN/Atemplate 3402623SN/AFault 3412623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3422623SN/A 3432623SN/Atemplate 3442623SN/AFault 3452623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 3462623SN/A 3472623SN/Atemplate 3482623SN/AFault 3492623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3502623SN/A 3512623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3522623SN/A 3532623SN/Atemplate<> 3542623SN/AFault 3552623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 3562623SN/A{ 3572623SN/A return read(addr, *(uint64_t*)&data, flags); 3582623SN/A} 3592623SN/A 3602623SN/Atemplate<> 3612623SN/AFault 3622623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 3632623SN/A{ 3642623SN/A return read(addr, *(uint32_t*)&data, flags); 3652623SN/A} 3662623SN/A 3672623SN/A 3682623SN/Atemplate<> 3692623SN/AFault 3702623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3712623SN/A{ 3722623SN/A return read(addr, (uint32_t&)data, flags); 3732623SN/A} 3742623SN/A 3752623SN/A 3762623SN/Atemplate <class T> 3772623SN/AFault 3782623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3792623SN/A{ 3803169Sstever@eecs.umich.edu Request *req = 3813169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 3825169Ssaidi@eecs.umich.edu cpuId, /* thread ID */ 0); 3832623SN/A 3844040Ssaidi@eecs.umich.edu if (traceData) { 3854040Ssaidi@eecs.umich.edu traceData->setAddr(req->getVaddr()); 3864040Ssaidi@eecs.umich.edu } 3874040Ssaidi@eecs.umich.edu 3882623SN/A // translate to physical address 3893169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3903169Sstever@eecs.umich.edu 3912623SN/A // Now do the access. 3922623SN/A if (fault == NoFault) { 3934878Sstever@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 3943170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3953170Sstever@eecs.umich.edu 3963170Sstever@eecs.umich.edu if (req->isLocked()) { 3974878Sstever@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3983170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3994878Sstever@eecs.umich.edu } else if (req->isSwap()) { 4004878Sstever@eecs.umich.edu cmd = MemCmd::SwapReq; 4014878Sstever@eecs.umich.edu if (req->isCondSwap()) { 4024878Sstever@eecs.umich.edu assert(res); 4034878Sstever@eecs.umich.edu req->setExtraData(*res); 4044878Sstever@eecs.umich.edu } 4053170Sstever@eecs.umich.edu } 4064584Ssaidi@eecs.umich.edu 4074881Sstever@eecs.umich.edu // Note: need to allocate dcache_pkt even if do_access is 4084881Sstever@eecs.umich.edu // false, as it's used unconditionally to call completeAcc(). 4094881Sstever@eecs.umich.edu assert(dcache_pkt == NULL); 4104881Sstever@eecs.umich.edu dcache_pkt = new Packet(req, cmd, Packet::Broadcast); 4114881Sstever@eecs.umich.edu dcache_pkt->allocate(); 4124881Sstever@eecs.umich.edu dcache_pkt->set(data); 4133170Sstever@eecs.umich.edu 4143170Sstever@eecs.umich.edu if (do_access) { 4155103Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) { 4165103Ssaidi@eecs.umich.edu Tick delay; 4175103Ssaidi@eecs.umich.edu dcache_pkt->set(htog(data)); 4185103Ssaidi@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4195103Ssaidi@eecs.umich.edu new IprEvent(dcache_pkt, this, nextCycle(curTick + delay)); 4205103Ssaidi@eecs.umich.edu _status = DcacheWaitResponse; 4215103Ssaidi@eecs.umich.edu dcache_pkt = NULL; 4225103Ssaidi@eecs.umich.edu } else if (!dcachePort.sendTiming(dcache_pkt)) { 4233170Sstever@eecs.umich.edu _status = DcacheRetry; 4243170Sstever@eecs.umich.edu } else { 4253170Sstever@eecs.umich.edu _status = DcacheWaitResponse; 4263170Sstever@eecs.umich.edu // memory system takes ownership of packet 4273170Sstever@eecs.umich.edu dcache_pkt = NULL; 4283170Sstever@eecs.umich.edu } 4292623SN/A } 4304200Ssaidi@eecs.umich.edu // This will need a new way to tell if it's hooked up to a cache or not. 4314200Ssaidi@eecs.umich.edu if (req->isUncacheable()) 4324200Ssaidi@eecs.umich.edu recordEvent("Uncached Write"); 4333658Sktlim@umich.edu } else { 4343658Sktlim@umich.edu delete req; 4352623SN/A } 4362623SN/A 4375408Sgblack@eecs.umich.edu if (traceData) { 4385408Sgblack@eecs.umich.edu traceData->setData(data); 4395408Sgblack@eecs.umich.edu } 4402623SN/A 4412623SN/A // If the write needs to have a fault on the access, consider calling 4422623SN/A // changeStatus() and changing it to "bad addr write" or something. 4432623SN/A return fault; 4442623SN/A} 4452623SN/A 4465177Sgblack@eecs.umich.eduFault 4475177Sgblack@eecs.umich.eduTimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr, 4485177Sgblack@eecs.umich.edu int size, unsigned flags) 4495177Sgblack@eecs.umich.edu{ 4505177Sgblack@eecs.umich.edu Request *req = 4515177Sgblack@eecs.umich.edu new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0); 4525177Sgblack@eecs.umich.edu 4535177Sgblack@eecs.umich.edu if (traceData) { 4545177Sgblack@eecs.umich.edu traceData->setAddr(vaddr); 4555177Sgblack@eecs.umich.edu } 4565177Sgblack@eecs.umich.edu 4575177Sgblack@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 4585177Sgblack@eecs.umich.edu 4595177Sgblack@eecs.umich.edu if (fault == NoFault) 4605177Sgblack@eecs.umich.edu paddr = req->getPaddr(); 4615177Sgblack@eecs.umich.edu 4625177Sgblack@eecs.umich.edu delete req; 4635177Sgblack@eecs.umich.edu return fault; 4645177Sgblack@eecs.umich.edu} 4655177Sgblack@eecs.umich.edu 4662623SN/A 4672623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4682623SN/Atemplate 4692623SN/AFault 4704224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin32_t data, Addr addr, 4714224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4724224Sgblack@eecs.umich.edu 4734224Sgblack@eecs.umich.edutemplate 4744224Sgblack@eecs.umich.eduFault 4754224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin64_t data, Addr addr, 4764224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4774224Sgblack@eecs.umich.edu 4784224Sgblack@eecs.umich.edutemplate 4794224Sgblack@eecs.umich.eduFault 4802623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 4812623SN/A unsigned flags, uint64_t *res); 4822623SN/A 4832623SN/Atemplate 4842623SN/AFault 4852623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 4862623SN/A unsigned flags, uint64_t *res); 4872623SN/A 4882623SN/Atemplate 4892623SN/AFault 4902623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 4912623SN/A unsigned flags, uint64_t *res); 4922623SN/A 4932623SN/Atemplate 4942623SN/AFault 4952623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 4962623SN/A unsigned flags, uint64_t *res); 4972623SN/A 4982623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4992623SN/A 5002623SN/Atemplate<> 5012623SN/AFault 5022623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 5032623SN/A{ 5042623SN/A return write(*(uint64_t*)&data, addr, flags, res); 5052623SN/A} 5062623SN/A 5072623SN/Atemplate<> 5082623SN/AFault 5092623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 5102623SN/A{ 5112623SN/A return write(*(uint32_t*)&data, addr, flags, res); 5122623SN/A} 5132623SN/A 5142623SN/A 5152623SN/Atemplate<> 5162623SN/AFault 5172623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 5182623SN/A{ 5192623SN/A return write((uint32_t)data, addr, flags, res); 5202623SN/A} 5212623SN/A 5222623SN/A 5232623SN/Avoid 5242623SN/ATimingSimpleCPU::fetch() 5252623SN/A{ 5265221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5275221Ssaidi@eecs.umich.edu 5283387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5293387Sgblack@eecs.umich.edu checkForInterrupts(); 5302631SN/A 5315348Ssaidi@eecs.umich.edu checkPcEventQueue(); 5325348Ssaidi@eecs.umich.edu 5332663Sstever@eecs.umich.edu Request *ifetch_req = new Request(); 5345169Ssaidi@eecs.umich.edu ifetch_req->setThreadContext(cpuId, /* thread ID */ 0); 5352662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 5362623SN/A 5374022Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast); 5382623SN/A ifetch_pkt->dataStatic(&inst); 5392623SN/A 5402623SN/A if (fault == NoFault) { 5412630SN/A if (!icachePort.sendTiming(ifetch_pkt)) { 5422623SN/A // Need to wait for retry 5432623SN/A _status = IcacheRetry; 5442623SN/A } else { 5452623SN/A // Need to wait for cache to respond 5462623SN/A _status = IcacheWaitResponse; 5472623SN/A // ownership of packet transferred to memory system 5482623SN/A ifetch_pkt = NULL; 5492623SN/A } 5502623SN/A } else { 5513658Sktlim@umich.edu delete ifetch_req; 5523658Sktlim@umich.edu delete ifetch_pkt; 5532644Sstever@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 5542644Sstever@eecs.umich.edu advanceInst(fault); 5552623SN/A } 5563222Sktlim@umich.edu 5575099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 5583222Sktlim@umich.edu previousTick = curTick; 5592623SN/A} 5602623SN/A 5612623SN/A 5622623SN/Avoid 5632644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 5642623SN/A{ 5652623SN/A advancePC(fault); 5662623SN/A 5672631SN/A if (_status == Running) { 5682631SN/A // kick off fetch of next instruction... callback from icache 5692631SN/A // response will cause that instruction to be executed, 5702631SN/A // keeping the CPU running. 5712631SN/A fetch(); 5722631SN/A } 5732623SN/A} 5742623SN/A 5752623SN/A 5762623SN/Avoid 5773349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 5782623SN/A{ 5795221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Complete ICache Fetch\n"); 5805221Ssaidi@eecs.umich.edu 5812623SN/A // received a response from the icache: execute the received 5822623SN/A // instruction 5834870Sstever@eecs.umich.edu assert(!pkt->isError()); 5842623SN/A assert(_status == IcacheWaitResponse); 5852798Sktlim@umich.edu 5862623SN/A _status = Running; 5872644Sstever@eecs.umich.edu 5885099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 5893222Sktlim@umich.edu previousTick = curTick; 5903222Sktlim@umich.edu 5912839Sktlim@umich.edu if (getState() == SimObject::Draining) { 5923658Sktlim@umich.edu delete pkt->req; 5933658Sktlim@umich.edu delete pkt; 5943658Sktlim@umich.edu 5952839Sktlim@umich.edu completeDrain(); 5962798Sktlim@umich.edu return; 5972798Sktlim@umich.edu } 5982798Sktlim@umich.edu 5992623SN/A preExecute(); 6002644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 6012623SN/A // load or store: just send to dcache 6022623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 6033170Sstever@eecs.umich.edu if (_status != Running) { 6043170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 6053170Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DcacheRetry); 6063170Sstever@eecs.umich.edu assert(fault == NoFault); 6072644Sstever@eecs.umich.edu } else { 6083170Sstever@eecs.umich.edu if (fault == NoFault) { 6095335Shines@cs.fsu.edu // Note that ARM can have NULL packets if the instruction gets 6105335Shines@cs.fsu.edu // squashed due to predication 6113170Sstever@eecs.umich.edu // early fail on store conditional: complete now 6125335Shines@cs.fsu.edu assert(dcache_pkt != NULL || THE_ISA == ARM_ISA); 6135335Shines@cs.fsu.edu 6143170Sstever@eecs.umich.edu fault = curStaticInst->completeAcc(dcache_pkt, this, 6153170Sstever@eecs.umich.edu traceData); 6165335Shines@cs.fsu.edu if (dcache_pkt != NULL) 6175335Shines@cs.fsu.edu { 6185335Shines@cs.fsu.edu delete dcache_pkt->req; 6195335Shines@cs.fsu.edu delete dcache_pkt; 6205335Shines@cs.fsu.edu dcache_pkt = NULL; 6215335Shines@cs.fsu.edu } 6224998Sgblack@eecs.umich.edu 6234998Sgblack@eecs.umich.edu // keep an instruction count 6244998Sgblack@eecs.umich.edu if (fault == NoFault) 6254998Sgblack@eecs.umich.edu countInst(); 6265001Sgblack@eecs.umich.edu } else if (traceData) { 6275001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6285001Sgblack@eecs.umich.edu delete traceData; 6295001Sgblack@eecs.umich.edu traceData = NULL; 6303170Sstever@eecs.umich.edu } 6314998Sgblack@eecs.umich.edu 6322644Sstever@eecs.umich.edu postExecute(); 6335103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6345103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6355103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6365103Ssaidi@eecs.umich.edu instCnt++; 6372644Sstever@eecs.umich.edu advanceInst(fault); 6382644Sstever@eecs.umich.edu } 6392623SN/A } else { 6402623SN/A // non-memory instruction: execute completely now 6412623SN/A Fault fault = curStaticInst->execute(this, traceData); 6424998Sgblack@eecs.umich.edu 6434998Sgblack@eecs.umich.edu // keep an instruction count 6444998Sgblack@eecs.umich.edu if (fault == NoFault) 6454998Sgblack@eecs.umich.edu countInst(); 6465001Sgblack@eecs.umich.edu else if (traceData) { 6475001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6485001Sgblack@eecs.umich.edu delete traceData; 6495001Sgblack@eecs.umich.edu traceData = NULL; 6505001Sgblack@eecs.umich.edu } 6514998Sgblack@eecs.umich.edu 6522644Sstever@eecs.umich.edu postExecute(); 6535103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6545103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6555103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6565103Ssaidi@eecs.umich.edu instCnt++; 6572644Sstever@eecs.umich.edu advanceInst(fault); 6582623SN/A } 6593658Sktlim@umich.edu 6603658Sktlim@umich.edu delete pkt->req; 6613658Sktlim@umich.edu delete pkt; 6622623SN/A} 6632623SN/A 6642948Ssaidi@eecs.umich.eduvoid 6652948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 6662948Ssaidi@eecs.umich.edu{ 6672948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 6682948Ssaidi@eecs.umich.edu} 6692623SN/A 6702623SN/Abool 6713349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 6722623SN/A{ 6734986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 6743310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 6754584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 6762948Ssaidi@eecs.umich.edu 6773495Sktlim@umich.edu if (next_tick == curTick) 6783310Srdreslin@umich.edu cpu->completeIfetch(pkt); 6793310Srdreslin@umich.edu else 6803495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 6812948Ssaidi@eecs.umich.edu 6823310Srdreslin@umich.edu return true; 6833310Srdreslin@umich.edu } 6844870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 6854433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 6864433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 6874433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 6884433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 6894433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 6904433Ssaidi@eecs.umich.edu } 6913310Srdreslin@umich.edu } 6924433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 6934433Ssaidi@eecs.umich.edu return true; 6942623SN/A} 6952623SN/A 6962657Ssaidi@eecs.umich.eduvoid 6972623SN/ATimingSimpleCPU::IcachePort::recvRetry() 6982623SN/A{ 6992623SN/A // we shouldn't get a retry unless we have a packet that we're 7002623SN/A // waiting to transmit 7012623SN/A assert(cpu->ifetch_pkt != NULL); 7022623SN/A assert(cpu->_status == IcacheRetry); 7033349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7042657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 7052657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7062657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7072657Ssaidi@eecs.umich.edu } 7082623SN/A} 7092623SN/A 7102623SN/Avoid 7113349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 7122623SN/A{ 7132623SN/A // received a response from the dcache: complete the load or store 7142623SN/A // instruction 7154870Sstever@eecs.umich.edu assert(!pkt->isError()); 7162623SN/A assert(_status == DcacheWaitResponse); 7172623SN/A _status = Running; 7182623SN/A 7195099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 7203222Sktlim@umich.edu previousTick = curTick; 7213184Srdreslin@umich.edu 7222623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 7232623SN/A 7244998Sgblack@eecs.umich.edu // keep an instruction count 7254998Sgblack@eecs.umich.edu if (fault == NoFault) 7264998Sgblack@eecs.umich.edu countInst(); 7275001Sgblack@eecs.umich.edu else if (traceData) { 7285001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7295001Sgblack@eecs.umich.edu delete traceData; 7305001Sgblack@eecs.umich.edu traceData = NULL; 7315001Sgblack@eecs.umich.edu } 7324998Sgblack@eecs.umich.edu 7335507Sstever@gmail.com // the locked flag may be cleared on the response packet, so check 7345507Sstever@gmail.com // pkt->req and not pkt to see if it was a load-locked 7355507Sstever@gmail.com if (pkt->isRead() && pkt->req->isLocked()) { 7363170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 7373170Sstever@eecs.umich.edu } 7383170Sstever@eecs.umich.edu 7392644Sstever@eecs.umich.edu delete pkt->req; 7402644Sstever@eecs.umich.edu delete pkt; 7412644Sstever@eecs.umich.edu 7423184Srdreslin@umich.edu postExecute(); 7433227Sktlim@umich.edu 7443201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 7453201Shsul@eecs.umich.edu advancePC(fault); 7463201Shsul@eecs.umich.edu completeDrain(); 7473201Shsul@eecs.umich.edu 7483201Shsul@eecs.umich.edu return; 7493201Shsul@eecs.umich.edu } 7503201Shsul@eecs.umich.edu 7512644Sstever@eecs.umich.edu advanceInst(fault); 7522623SN/A} 7532623SN/A 7542623SN/A 7552798Sktlim@umich.eduvoid 7562839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 7572798Sktlim@umich.edu{ 7582839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 7592901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 7602839Sktlim@umich.edu drainEvent->process(); 7612798Sktlim@umich.edu} 7622623SN/A 7634192Sktlim@umich.eduvoid 7644192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 7654192Sktlim@umich.edu{ 7664192Sktlim@umich.edu Port::setPeer(port); 7674192Sktlim@umich.edu 7684192Sktlim@umich.edu#if FULL_SYSTEM 7694192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 7704192Sktlim@umich.edu // Ports) 7715497Ssaidi@eecs.umich.edu cpu->tcBase()->connectMemPorts(cpu->tcBase()); 7724192Sktlim@umich.edu#endif 7734192Sktlim@umich.edu} 7744192Sktlim@umich.edu 7752623SN/Abool 7763349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 7772623SN/A{ 7784986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 7793310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 7804584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 7812948Ssaidi@eecs.umich.edu 7823495Sktlim@umich.edu if (next_tick == curTick) 7833310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 7843310Srdreslin@umich.edu else 7853495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 7862948Ssaidi@eecs.umich.edu 7873310Srdreslin@umich.edu return true; 7883310Srdreslin@umich.edu } 7894870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 7904433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 7914433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 7924433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 7934433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 7944433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 7954433Ssaidi@eecs.umich.edu } 7963310Srdreslin@umich.edu } 7974433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 7984433Ssaidi@eecs.umich.edu return true; 7992948Ssaidi@eecs.umich.edu} 8002948Ssaidi@eecs.umich.edu 8012948Ssaidi@eecs.umich.eduvoid 8022948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 8032948Ssaidi@eecs.umich.edu{ 8042630SN/A cpu->completeDataAccess(pkt); 8052623SN/A} 8062623SN/A 8072657Ssaidi@eecs.umich.eduvoid 8082623SN/ATimingSimpleCPU::DcachePort::recvRetry() 8092623SN/A{ 8102623SN/A // we shouldn't get a retry unless we have a packet that we're 8112623SN/A // waiting to transmit 8122623SN/A assert(cpu->dcache_pkt != NULL); 8132623SN/A assert(cpu->_status == DcacheRetry); 8143349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 8152657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 8162657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 8173170Sstever@eecs.umich.edu // memory system takes ownership of packet 8182657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 8192657Ssaidi@eecs.umich.edu } 8202623SN/A} 8212623SN/A 8225103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t) 8235103Ssaidi@eecs.umich.edu : Event(&mainEventQueue), pkt(_pkt), cpu(_cpu) 8245103Ssaidi@eecs.umich.edu{ 8255103Ssaidi@eecs.umich.edu schedule(t); 8265103Ssaidi@eecs.umich.edu} 8275103Ssaidi@eecs.umich.edu 8285103Ssaidi@eecs.umich.eduvoid 8295103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 8305103Ssaidi@eecs.umich.edu{ 8315103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 8325103Ssaidi@eecs.umich.edu} 8335103Ssaidi@eecs.umich.edu 8345103Ssaidi@eecs.umich.educonst char * 8355336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 8365103Ssaidi@eecs.umich.edu{ 8375103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 8385103Ssaidi@eecs.umich.edu} 8395103Ssaidi@eecs.umich.edu 8402623SN/A 8415315Sstever@gmail.comvoid 8425315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 8435315Sstever@gmail.com{ 8445315Sstever@gmail.com dcachePort.printAddr(a); 8455315Sstever@gmail.com} 8465315Sstever@gmail.com 8475315Sstever@gmail.com 8482623SN/A//////////////////////////////////////////////////////////////////////// 8492623SN/A// 8502623SN/A// TimingSimpleCPU Simulation Object 8512623SN/A// 8524762Snate@binkert.orgTimingSimpleCPU * 8534762Snate@binkert.orgTimingSimpleCPUParams::create() 8542623SN/A{ 8555529Snate@binkert.org numThreads = 1; 8565529Snate@binkert.org#if !FULL_SYSTEM 8574762Snate@binkert.org if (workload.size() != 1) 8584762Snate@binkert.org panic("only one workload allowed"); 8592623SN/A#endif 8605529Snate@binkert.org return new TimingSimpleCPU(this); 8612623SN/A} 862