timing.cc revision 5221
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 325103Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh" 332623SN/A#include "arch/utility.hh" 344040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 352623SN/A#include "cpu/exetrace.hh" 362623SN/A#include "cpu/simple/timing.hh" 373348Sbinkertn@umich.edu#include "mem/packet.hh" 383348Sbinkertn@umich.edu#include "mem/packet_access.hh" 394762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 402901Ssaidi@eecs.umich.edu#include "sim/system.hh" 412623SN/A 422623SN/Ausing namespace std; 432623SN/Ausing namespace TheISA; 442623SN/A 452856Srdreslin@umich.eduPort * 462856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 472856Srdreslin@umich.edu{ 482856Srdreslin@umich.edu if (if_name == "dcache_port") 492856Srdreslin@umich.edu return &dcachePort; 502856Srdreslin@umich.edu else if (if_name == "icache_port") 512856Srdreslin@umich.edu return &icachePort; 522856Srdreslin@umich.edu else 532856Srdreslin@umich.edu panic("No Such Port\n"); 542856Srdreslin@umich.edu} 552623SN/A 562623SN/Avoid 572623SN/ATimingSimpleCPU::init() 582623SN/A{ 592623SN/A BaseCPU::init(); 602623SN/A#if FULL_SYSTEM 612680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 622680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 632623SN/A 642623SN/A // initialize CPU, including PC 652680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 662623SN/A } 672623SN/A#endif 682623SN/A} 692623SN/A 702623SN/ATick 713349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 722623SN/A{ 732623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 742623SN/A return curTick; 752623SN/A} 762623SN/A 772623SN/Avoid 783349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 792623SN/A{ 803184Srdreslin@umich.edu //No internal storage to update, jusst return 813184Srdreslin@umich.edu return; 822623SN/A} 832623SN/A 842623SN/Avoid 852623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 862623SN/A{ 873647Srdreslin@umich.edu if (status == RangeChange) { 883647Srdreslin@umich.edu if (!snoopRangeSent) { 893647Srdreslin@umich.edu snoopRangeSent = true; 903647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 913647Srdreslin@umich.edu } 922631SN/A return; 933647Srdreslin@umich.edu } 942631SN/A 952623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 962623SN/A} 972623SN/A 982948Ssaidi@eecs.umich.edu 992948Ssaidi@eecs.umich.eduvoid 1003349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1012948Ssaidi@eecs.umich.edu{ 1022948Ssaidi@eecs.umich.edu pkt = _pkt; 1032948Ssaidi@eecs.umich.edu Event::schedule(t); 1042948Ssaidi@eecs.umich.edu} 1052948Ssaidi@eecs.umich.edu 1062623SN/ATimingSimpleCPU::TimingSimpleCPU(Params *p) 1075169Ssaidi@eecs.umich.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock) 1082623SN/A{ 1092623SN/A _status = Idle; 1103647Srdreslin@umich.edu 1113647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1123647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1133647Srdreslin@umich.edu 1142623SN/A ifetch_pkt = dcache_pkt = NULL; 1152839Sktlim@umich.edu drainEvent = NULL; 1162867Sktlim@umich.edu fetchEvent = NULL; 1173222Sktlim@umich.edu previousTick = 0; 1182901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1192623SN/A} 1202623SN/A 1212623SN/A 1222623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1232623SN/A{ 1242623SN/A} 1252623SN/A 1262623SN/Avoid 1272623SN/ATimingSimpleCPU::serialize(ostream &os) 1282623SN/A{ 1292915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1302915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1312623SN/A BaseSimpleCPU::serialize(os); 1322623SN/A} 1332623SN/A 1342623SN/Avoid 1352623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1362623SN/A{ 1372915Sktlim@umich.edu SimObject::State so_state; 1382915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1392623SN/A BaseSimpleCPU::unserialize(cp, section); 1402798Sktlim@umich.edu} 1412798Sktlim@umich.edu 1422901Ssaidi@eecs.umich.eduunsigned int 1432839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1442798Sktlim@umich.edu{ 1452839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1462798Sktlim@umich.edu // an access to complete. 1472798Sktlim@umich.edu if (status() == Idle || status() == Running || status() == SwitchedOut) { 1482901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1492901Ssaidi@eecs.umich.edu return 0; 1502798Sktlim@umich.edu } else { 1512839Sktlim@umich.edu changeState(SimObject::Draining); 1522839Sktlim@umich.edu drainEvent = drain_event; 1532901Ssaidi@eecs.umich.edu return 1; 1542798Sktlim@umich.edu } 1552623SN/A} 1562623SN/A 1572623SN/Avoid 1582798Sktlim@umich.eduTimingSimpleCPU::resume() 1592623SN/A{ 1605221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1612798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1624762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1633201Shsul@eecs.umich.edu 1642867Sktlim@umich.edu // Delete the old event if it existed. 1652867Sktlim@umich.edu if (fetchEvent) { 1662915Sktlim@umich.edu if (fetchEvent->scheduled()) 1672915Sktlim@umich.edu fetchEvent->deschedule(); 1682915Sktlim@umich.edu 1692867Sktlim@umich.edu delete fetchEvent; 1702867Sktlim@umich.edu } 1712867Sktlim@umich.edu 1724471Sstever@eecs.umich.edu fetchEvent = new FetchEvent(this, nextCycle()); 1732623SN/A } 1742798Sktlim@umich.edu 1752901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1762798Sktlim@umich.edu} 1772798Sktlim@umich.edu 1782798Sktlim@umich.eduvoid 1792798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1802798Sktlim@umich.edu{ 1812798Sktlim@umich.edu assert(status() == Running || status() == Idle); 1822798Sktlim@umich.edu _status = SwitchedOut; 1835099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 1842867Sktlim@umich.edu 1852867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1862867Sktlim@umich.edu // we'll need to cancel it. 1872867Sktlim@umich.edu if (fetchEvent && fetchEvent->scheduled()) 1882867Sktlim@umich.edu fetchEvent->deschedule(); 1892623SN/A} 1902623SN/A 1912623SN/A 1922623SN/Avoid 1932623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1942623SN/A{ 1954192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 1962623SN/A 1972680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1982623SN/A // running and schedule its tick event. 1992680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2002680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2012680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2022623SN/A _status = Running; 2032623SN/A break; 2042623SN/A } 2052623SN/A } 2063201Shsul@eecs.umich.edu 2073201Shsul@eecs.umich.edu if (_status != Running) { 2083201Shsul@eecs.umich.edu _status = Idle; 2093201Shsul@eecs.umich.edu } 2105169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2115169Ssaidi@eecs.umich.edu cpuId = tc->readCpuId(); 2125101Ssaidi@eecs.umich.edu previousTick = curTick; 2132623SN/A} 2142623SN/A 2152623SN/A 2162623SN/Avoid 2172623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2182623SN/A{ 2195221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2205221Ssaidi@eecs.umich.edu 2212623SN/A assert(thread_num == 0); 2222683Sktlim@umich.edu assert(thread); 2232623SN/A 2242623SN/A assert(_status == Idle); 2252623SN/A 2262623SN/A notIdleFraction++; 2272623SN/A _status = Running; 2283686Sktlim@umich.edu 2292623SN/A // kick things off by initiating the fetch of the next instruction 2305100Ssaidi@eecs.umich.edu fetchEvent = new FetchEvent(this, nextCycle(curTick + ticks(delay))); 2312623SN/A} 2322623SN/A 2332623SN/A 2342623SN/Avoid 2352623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2362623SN/A{ 2375221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2385221Ssaidi@eecs.umich.edu 2392623SN/A assert(thread_num == 0); 2402683Sktlim@umich.edu assert(thread); 2412623SN/A 2422644Sstever@eecs.umich.edu assert(_status == Running); 2432623SN/A 2442644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2452644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2462623SN/A 2472623SN/A notIdleFraction--; 2482623SN/A _status = Idle; 2492623SN/A} 2502623SN/A 2512623SN/A 2522623SN/Atemplate <class T> 2532623SN/AFault 2542623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2552623SN/A{ 2563169Sstever@eecs.umich.edu Request *req = 2573169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 2585169Ssaidi@eecs.umich.edu cpuId, /* thread ID */ 0); 2592623SN/A 2602623SN/A if (traceData) { 2613169Sstever@eecs.umich.edu traceData->setAddr(req->getVaddr()); 2622623SN/A } 2632623SN/A 2642623SN/A // translate to physical address 2653169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2662623SN/A 2672623SN/A // Now do the access. 2682623SN/A if (fault == NoFault) { 2693349Sbinkertn@umich.edu PacketPtr pkt = 2704878Sstever@eecs.umich.edu new Packet(req, 2714878Sstever@eecs.umich.edu (req->isLocked() ? 2724878Sstever@eecs.umich.edu MemCmd::LoadLockedReq : MemCmd::ReadReq), 2734878Sstever@eecs.umich.edu Packet::Broadcast); 2743169Sstever@eecs.umich.edu pkt->dataDynamic<T>(new T); 2752623SN/A 2765103Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) { 2775103Ssaidi@eecs.umich.edu Tick delay; 2785103Ssaidi@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2795103Ssaidi@eecs.umich.edu new IprEvent(pkt, this, nextCycle(curTick + delay)); 2805103Ssaidi@eecs.umich.edu _status = DcacheWaitResponse; 2815103Ssaidi@eecs.umich.edu dcache_pkt = NULL; 2825103Ssaidi@eecs.umich.edu } else if (!dcachePort.sendTiming(pkt)) { 2832623SN/A _status = DcacheRetry; 2843169Sstever@eecs.umich.edu dcache_pkt = pkt; 2852623SN/A } else { 2862623SN/A _status = DcacheWaitResponse; 2873169Sstever@eecs.umich.edu // memory system takes ownership of packet 2882623SN/A dcache_pkt = NULL; 2892623SN/A } 2904200Ssaidi@eecs.umich.edu 2914200Ssaidi@eecs.umich.edu // This will need a new way to tell if it has a dcache attached. 2924200Ssaidi@eecs.umich.edu if (req->isUncacheable()) 2934200Ssaidi@eecs.umich.edu recordEvent("Uncached Read"); 2943658Sktlim@umich.edu } else { 2953658Sktlim@umich.edu delete req; 2962623SN/A } 2972623SN/A 2982623SN/A return fault; 2992623SN/A} 3002623SN/A 3015177Sgblack@eecs.umich.eduFault 3025177Sgblack@eecs.umich.eduTimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr, 3035177Sgblack@eecs.umich.edu int size, unsigned flags) 3045177Sgblack@eecs.umich.edu{ 3055177Sgblack@eecs.umich.edu Request *req = 3065177Sgblack@eecs.umich.edu new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0); 3075177Sgblack@eecs.umich.edu 3085177Sgblack@eecs.umich.edu if (traceData) { 3095177Sgblack@eecs.umich.edu traceData->setAddr(vaddr); 3105177Sgblack@eecs.umich.edu } 3115177Sgblack@eecs.umich.edu 3125177Sgblack@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3135177Sgblack@eecs.umich.edu 3145177Sgblack@eecs.umich.edu if (fault == NoFault) 3155177Sgblack@eecs.umich.edu paddr = req->getPaddr(); 3165177Sgblack@eecs.umich.edu 3175177Sgblack@eecs.umich.edu delete req; 3185177Sgblack@eecs.umich.edu return fault; 3195177Sgblack@eecs.umich.edu} 3205177Sgblack@eecs.umich.edu 3212623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3222623SN/A 3232623SN/Atemplate 3242623SN/AFault 3254040Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 3264040Ssaidi@eecs.umich.edu 3274040Ssaidi@eecs.umich.edutemplate 3284040Ssaidi@eecs.umich.eduFault 3294115Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 3304115Ssaidi@eecs.umich.edu 3314115Ssaidi@eecs.umich.edutemplate 3324115Ssaidi@eecs.umich.eduFault 3332623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 3342623SN/A 3352623SN/Atemplate 3362623SN/AFault 3372623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3382623SN/A 3392623SN/Atemplate 3402623SN/AFault 3412623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 3422623SN/A 3432623SN/Atemplate 3442623SN/AFault 3452623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3462623SN/A 3472623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3482623SN/A 3492623SN/Atemplate<> 3502623SN/AFault 3512623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 3522623SN/A{ 3532623SN/A return read(addr, *(uint64_t*)&data, flags); 3542623SN/A} 3552623SN/A 3562623SN/Atemplate<> 3572623SN/AFault 3582623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 3592623SN/A{ 3602623SN/A return read(addr, *(uint32_t*)&data, flags); 3612623SN/A} 3622623SN/A 3632623SN/A 3642623SN/Atemplate<> 3652623SN/AFault 3662623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3672623SN/A{ 3682623SN/A return read(addr, (uint32_t&)data, flags); 3692623SN/A} 3702623SN/A 3712623SN/A 3722623SN/Atemplate <class T> 3732623SN/AFault 3742623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3752623SN/A{ 3763169Sstever@eecs.umich.edu Request *req = 3773169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 3785169Ssaidi@eecs.umich.edu cpuId, /* thread ID */ 0); 3792623SN/A 3804040Ssaidi@eecs.umich.edu if (traceData) { 3814040Ssaidi@eecs.umich.edu traceData->setAddr(req->getVaddr()); 3824040Ssaidi@eecs.umich.edu } 3834040Ssaidi@eecs.umich.edu 3842623SN/A // translate to physical address 3853169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3863169Sstever@eecs.umich.edu 3872623SN/A // Now do the access. 3882623SN/A if (fault == NoFault) { 3894878Sstever@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 3903170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3913170Sstever@eecs.umich.edu 3923170Sstever@eecs.umich.edu if (req->isLocked()) { 3934878Sstever@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3943170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3954878Sstever@eecs.umich.edu } else if (req->isSwap()) { 3964878Sstever@eecs.umich.edu cmd = MemCmd::SwapReq; 3974878Sstever@eecs.umich.edu if (req->isCondSwap()) { 3984878Sstever@eecs.umich.edu assert(res); 3994878Sstever@eecs.umich.edu req->setExtraData(*res); 4004878Sstever@eecs.umich.edu } 4013170Sstever@eecs.umich.edu } 4024584Ssaidi@eecs.umich.edu 4034881Sstever@eecs.umich.edu // Note: need to allocate dcache_pkt even if do_access is 4044881Sstever@eecs.umich.edu // false, as it's used unconditionally to call completeAcc(). 4054881Sstever@eecs.umich.edu assert(dcache_pkt == NULL); 4064881Sstever@eecs.umich.edu dcache_pkt = new Packet(req, cmd, Packet::Broadcast); 4074881Sstever@eecs.umich.edu dcache_pkt->allocate(); 4084881Sstever@eecs.umich.edu dcache_pkt->set(data); 4093170Sstever@eecs.umich.edu 4103170Sstever@eecs.umich.edu if (do_access) { 4115103Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) { 4125103Ssaidi@eecs.umich.edu Tick delay; 4135103Ssaidi@eecs.umich.edu dcache_pkt->set(htog(data)); 4145103Ssaidi@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4155103Ssaidi@eecs.umich.edu new IprEvent(dcache_pkt, this, nextCycle(curTick + delay)); 4165103Ssaidi@eecs.umich.edu _status = DcacheWaitResponse; 4175103Ssaidi@eecs.umich.edu dcache_pkt = NULL; 4185103Ssaidi@eecs.umich.edu } else if (!dcachePort.sendTiming(dcache_pkt)) { 4193170Sstever@eecs.umich.edu _status = DcacheRetry; 4203170Sstever@eecs.umich.edu } else { 4213170Sstever@eecs.umich.edu _status = DcacheWaitResponse; 4223170Sstever@eecs.umich.edu // memory system takes ownership of packet 4233170Sstever@eecs.umich.edu dcache_pkt = NULL; 4243170Sstever@eecs.umich.edu } 4252623SN/A } 4264200Ssaidi@eecs.umich.edu // This will need a new way to tell if it's hooked up to a cache or not. 4274200Ssaidi@eecs.umich.edu if (req->isUncacheable()) 4284200Ssaidi@eecs.umich.edu recordEvent("Uncached Write"); 4293658Sktlim@umich.edu } else { 4303658Sktlim@umich.edu delete req; 4312623SN/A } 4322623SN/A 4332623SN/A 4342623SN/A // If the write needs to have a fault on the access, consider calling 4352623SN/A // changeStatus() and changing it to "bad addr write" or something. 4362623SN/A return fault; 4372623SN/A} 4382623SN/A 4395177Sgblack@eecs.umich.eduFault 4405177Sgblack@eecs.umich.eduTimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr, 4415177Sgblack@eecs.umich.edu int size, unsigned flags) 4425177Sgblack@eecs.umich.edu{ 4435177Sgblack@eecs.umich.edu Request *req = 4445177Sgblack@eecs.umich.edu new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0); 4455177Sgblack@eecs.umich.edu 4465177Sgblack@eecs.umich.edu if (traceData) { 4475177Sgblack@eecs.umich.edu traceData->setAddr(vaddr); 4485177Sgblack@eecs.umich.edu } 4495177Sgblack@eecs.umich.edu 4505177Sgblack@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 4515177Sgblack@eecs.umich.edu 4525177Sgblack@eecs.umich.edu if (fault == NoFault) 4535177Sgblack@eecs.umich.edu paddr = req->getPaddr(); 4545177Sgblack@eecs.umich.edu 4555177Sgblack@eecs.umich.edu delete req; 4565177Sgblack@eecs.umich.edu return fault; 4575177Sgblack@eecs.umich.edu} 4585177Sgblack@eecs.umich.edu 4592623SN/A 4602623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4612623SN/Atemplate 4622623SN/AFault 4634224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin32_t data, Addr addr, 4644224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4654224Sgblack@eecs.umich.edu 4664224Sgblack@eecs.umich.edutemplate 4674224Sgblack@eecs.umich.eduFault 4684224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin64_t data, Addr addr, 4694224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4704224Sgblack@eecs.umich.edu 4714224Sgblack@eecs.umich.edutemplate 4724224Sgblack@eecs.umich.eduFault 4732623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 4742623SN/A unsigned flags, uint64_t *res); 4752623SN/A 4762623SN/Atemplate 4772623SN/AFault 4782623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 4792623SN/A unsigned flags, uint64_t *res); 4802623SN/A 4812623SN/Atemplate 4822623SN/AFault 4832623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 4842623SN/A unsigned flags, uint64_t *res); 4852623SN/A 4862623SN/Atemplate 4872623SN/AFault 4882623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 4892623SN/A unsigned flags, uint64_t *res); 4902623SN/A 4912623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4922623SN/A 4932623SN/Atemplate<> 4942623SN/AFault 4952623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 4962623SN/A{ 4972623SN/A return write(*(uint64_t*)&data, addr, flags, res); 4982623SN/A} 4992623SN/A 5002623SN/Atemplate<> 5012623SN/AFault 5022623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 5032623SN/A{ 5042623SN/A return write(*(uint32_t*)&data, addr, flags, res); 5052623SN/A} 5062623SN/A 5072623SN/A 5082623SN/Atemplate<> 5092623SN/AFault 5102623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 5112623SN/A{ 5122623SN/A return write((uint32_t)data, addr, flags, res); 5132623SN/A} 5142623SN/A 5152623SN/A 5162623SN/Avoid 5172623SN/ATimingSimpleCPU::fetch() 5182623SN/A{ 5195221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5205221Ssaidi@eecs.umich.edu 5213387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5223387Sgblack@eecs.umich.edu checkForInterrupts(); 5232631SN/A 5242663Sstever@eecs.umich.edu Request *ifetch_req = new Request(); 5255169Ssaidi@eecs.umich.edu ifetch_req->setThreadContext(cpuId, /* thread ID */ 0); 5262662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 5272623SN/A 5284022Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast); 5292623SN/A ifetch_pkt->dataStatic(&inst); 5302623SN/A 5312623SN/A if (fault == NoFault) { 5322630SN/A if (!icachePort.sendTiming(ifetch_pkt)) { 5332623SN/A // Need to wait for retry 5342623SN/A _status = IcacheRetry; 5352623SN/A } else { 5362623SN/A // Need to wait for cache to respond 5372623SN/A _status = IcacheWaitResponse; 5382623SN/A // ownership of packet transferred to memory system 5392623SN/A ifetch_pkt = NULL; 5402623SN/A } 5412623SN/A } else { 5423658Sktlim@umich.edu delete ifetch_req; 5433658Sktlim@umich.edu delete ifetch_pkt; 5442644Sstever@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 5452644Sstever@eecs.umich.edu advanceInst(fault); 5462623SN/A } 5473222Sktlim@umich.edu 5485099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 5493222Sktlim@umich.edu previousTick = curTick; 5502623SN/A} 5512623SN/A 5522623SN/A 5532623SN/Avoid 5542644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 5552623SN/A{ 5562623SN/A advancePC(fault); 5572623SN/A 5582631SN/A if (_status == Running) { 5592631SN/A // kick off fetch of next instruction... callback from icache 5602631SN/A // response will cause that instruction to be executed, 5612631SN/A // keeping the CPU running. 5622631SN/A fetch(); 5632631SN/A } 5642623SN/A} 5652623SN/A 5662623SN/A 5672623SN/Avoid 5683349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 5692623SN/A{ 5705221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Complete ICache Fetch\n"); 5715221Ssaidi@eecs.umich.edu 5722623SN/A // received a response from the icache: execute the received 5732623SN/A // instruction 5744870Sstever@eecs.umich.edu assert(!pkt->isError()); 5752623SN/A assert(_status == IcacheWaitResponse); 5762798Sktlim@umich.edu 5772623SN/A _status = Running; 5782644Sstever@eecs.umich.edu 5795099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 5803222Sktlim@umich.edu previousTick = curTick; 5813222Sktlim@umich.edu 5822839Sktlim@umich.edu if (getState() == SimObject::Draining) { 5833658Sktlim@umich.edu delete pkt->req; 5843658Sktlim@umich.edu delete pkt; 5853658Sktlim@umich.edu 5862839Sktlim@umich.edu completeDrain(); 5872798Sktlim@umich.edu return; 5882798Sktlim@umich.edu } 5892798Sktlim@umich.edu 5902623SN/A preExecute(); 5912644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 5922623SN/A // load or store: just send to dcache 5932623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 5943170Sstever@eecs.umich.edu if (_status != Running) { 5953170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 5963170Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DcacheRetry); 5973170Sstever@eecs.umich.edu assert(fault == NoFault); 5982644Sstever@eecs.umich.edu } else { 5993170Sstever@eecs.umich.edu if (fault == NoFault) { 6003170Sstever@eecs.umich.edu // early fail on store conditional: complete now 6013170Sstever@eecs.umich.edu assert(dcache_pkt != NULL); 6023170Sstever@eecs.umich.edu fault = curStaticInst->completeAcc(dcache_pkt, this, 6033170Sstever@eecs.umich.edu traceData); 6043170Sstever@eecs.umich.edu delete dcache_pkt->req; 6053170Sstever@eecs.umich.edu delete dcache_pkt; 6063170Sstever@eecs.umich.edu dcache_pkt = NULL; 6074998Sgblack@eecs.umich.edu 6084998Sgblack@eecs.umich.edu // keep an instruction count 6094998Sgblack@eecs.umich.edu if (fault == NoFault) 6104998Sgblack@eecs.umich.edu countInst(); 6115001Sgblack@eecs.umich.edu } else if (traceData) { 6125001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6135001Sgblack@eecs.umich.edu delete traceData; 6145001Sgblack@eecs.umich.edu traceData = NULL; 6153170Sstever@eecs.umich.edu } 6164998Sgblack@eecs.umich.edu 6172644Sstever@eecs.umich.edu postExecute(); 6185103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6195103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6205103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6215103Ssaidi@eecs.umich.edu instCnt++; 6222644Sstever@eecs.umich.edu advanceInst(fault); 6232644Sstever@eecs.umich.edu } 6242623SN/A } else { 6252623SN/A // non-memory instruction: execute completely now 6262623SN/A Fault fault = curStaticInst->execute(this, traceData); 6274998Sgblack@eecs.umich.edu 6284998Sgblack@eecs.umich.edu // keep an instruction count 6294998Sgblack@eecs.umich.edu if (fault == NoFault) 6304998Sgblack@eecs.umich.edu countInst(); 6315001Sgblack@eecs.umich.edu else if (traceData) { 6325001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6335001Sgblack@eecs.umich.edu delete traceData; 6345001Sgblack@eecs.umich.edu traceData = NULL; 6355001Sgblack@eecs.umich.edu } 6364998Sgblack@eecs.umich.edu 6372644Sstever@eecs.umich.edu postExecute(); 6385103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6395103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6405103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6415103Ssaidi@eecs.umich.edu instCnt++; 6422644Sstever@eecs.umich.edu advanceInst(fault); 6432623SN/A } 6443658Sktlim@umich.edu 6453658Sktlim@umich.edu delete pkt->req; 6463658Sktlim@umich.edu delete pkt; 6472623SN/A} 6482623SN/A 6492948Ssaidi@eecs.umich.eduvoid 6502948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 6512948Ssaidi@eecs.umich.edu{ 6522948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 6532948Ssaidi@eecs.umich.edu} 6542623SN/A 6552623SN/Abool 6563349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 6572623SN/A{ 6584986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 6593310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 6604584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 6612948Ssaidi@eecs.umich.edu 6623495Sktlim@umich.edu if (next_tick == curTick) 6633310Srdreslin@umich.edu cpu->completeIfetch(pkt); 6643310Srdreslin@umich.edu else 6653495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 6662948Ssaidi@eecs.umich.edu 6673310Srdreslin@umich.edu return true; 6683310Srdreslin@umich.edu } 6694870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 6704433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 6714433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 6724433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 6734433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 6744433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 6754433Ssaidi@eecs.umich.edu } 6763310Srdreslin@umich.edu } 6774433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 6784433Ssaidi@eecs.umich.edu return true; 6792623SN/A} 6802623SN/A 6812657Ssaidi@eecs.umich.eduvoid 6822623SN/ATimingSimpleCPU::IcachePort::recvRetry() 6832623SN/A{ 6842623SN/A // we shouldn't get a retry unless we have a packet that we're 6852623SN/A // waiting to transmit 6862623SN/A assert(cpu->ifetch_pkt != NULL); 6872623SN/A assert(cpu->_status == IcacheRetry); 6883349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 6892657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 6902657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 6912657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 6922657Ssaidi@eecs.umich.edu } 6932623SN/A} 6942623SN/A 6952623SN/Avoid 6963349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 6972623SN/A{ 6982623SN/A // received a response from the dcache: complete the load or store 6992623SN/A // instruction 7004870Sstever@eecs.umich.edu assert(!pkt->isError()); 7012623SN/A assert(_status == DcacheWaitResponse); 7022623SN/A _status = Running; 7032623SN/A 7045099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 7053222Sktlim@umich.edu previousTick = curTick; 7063184Srdreslin@umich.edu 7072623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 7082623SN/A 7094998Sgblack@eecs.umich.edu // keep an instruction count 7104998Sgblack@eecs.umich.edu if (fault == NoFault) 7114998Sgblack@eecs.umich.edu countInst(); 7125001Sgblack@eecs.umich.edu else if (traceData) { 7135001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7145001Sgblack@eecs.umich.edu delete traceData; 7155001Sgblack@eecs.umich.edu traceData = NULL; 7165001Sgblack@eecs.umich.edu } 7174998Sgblack@eecs.umich.edu 7184878Sstever@eecs.umich.edu if (pkt->isRead() && pkt->isLocked()) { 7193170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 7203170Sstever@eecs.umich.edu } 7213170Sstever@eecs.umich.edu 7222644Sstever@eecs.umich.edu delete pkt->req; 7232644Sstever@eecs.umich.edu delete pkt; 7242644Sstever@eecs.umich.edu 7253184Srdreslin@umich.edu postExecute(); 7263227Sktlim@umich.edu 7273201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 7283201Shsul@eecs.umich.edu advancePC(fault); 7293201Shsul@eecs.umich.edu completeDrain(); 7303201Shsul@eecs.umich.edu 7313201Shsul@eecs.umich.edu return; 7323201Shsul@eecs.umich.edu } 7333201Shsul@eecs.umich.edu 7342644Sstever@eecs.umich.edu advanceInst(fault); 7352623SN/A} 7362623SN/A 7372623SN/A 7382798Sktlim@umich.eduvoid 7392839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 7402798Sktlim@umich.edu{ 7412839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 7422901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 7432839Sktlim@umich.edu drainEvent->process(); 7442798Sktlim@umich.edu} 7452623SN/A 7464192Sktlim@umich.eduvoid 7474192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 7484192Sktlim@umich.edu{ 7494192Sktlim@umich.edu Port::setPeer(port); 7504192Sktlim@umich.edu 7514192Sktlim@umich.edu#if FULL_SYSTEM 7524192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 7534192Sktlim@umich.edu // Ports) 7544192Sktlim@umich.edu cpu->tcBase()->connectMemPorts(); 7554192Sktlim@umich.edu#endif 7564192Sktlim@umich.edu} 7574192Sktlim@umich.edu 7582623SN/Abool 7593349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 7602623SN/A{ 7614986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 7623310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 7634584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 7642948Ssaidi@eecs.umich.edu 7653495Sktlim@umich.edu if (next_tick == curTick) 7663310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 7673310Srdreslin@umich.edu else 7683495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 7692948Ssaidi@eecs.umich.edu 7703310Srdreslin@umich.edu return true; 7713310Srdreslin@umich.edu } 7724870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 7734433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 7744433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 7754433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 7764433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 7774433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 7784433Ssaidi@eecs.umich.edu } 7793310Srdreslin@umich.edu } 7804433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 7814433Ssaidi@eecs.umich.edu return true; 7822948Ssaidi@eecs.umich.edu} 7832948Ssaidi@eecs.umich.edu 7842948Ssaidi@eecs.umich.eduvoid 7852948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 7862948Ssaidi@eecs.umich.edu{ 7872630SN/A cpu->completeDataAccess(pkt); 7882623SN/A} 7892623SN/A 7902657Ssaidi@eecs.umich.eduvoid 7912623SN/ATimingSimpleCPU::DcachePort::recvRetry() 7922623SN/A{ 7932623SN/A // we shouldn't get a retry unless we have a packet that we're 7942623SN/A // waiting to transmit 7952623SN/A assert(cpu->dcache_pkt != NULL); 7962623SN/A assert(cpu->_status == DcacheRetry); 7973349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 7982657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 7992657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 8003170Sstever@eecs.umich.edu // memory system takes ownership of packet 8012657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 8022657Ssaidi@eecs.umich.edu } 8032623SN/A} 8042623SN/A 8055103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t) 8065103Ssaidi@eecs.umich.edu : Event(&mainEventQueue), pkt(_pkt), cpu(_cpu) 8075103Ssaidi@eecs.umich.edu{ 8085103Ssaidi@eecs.umich.edu schedule(t); 8095103Ssaidi@eecs.umich.edu} 8105103Ssaidi@eecs.umich.edu 8115103Ssaidi@eecs.umich.eduvoid 8125103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 8135103Ssaidi@eecs.umich.edu{ 8145103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 8155103Ssaidi@eecs.umich.edu} 8165103Ssaidi@eecs.umich.edu 8175103Ssaidi@eecs.umich.educonst char * 8185103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::description() 8195103Ssaidi@eecs.umich.edu{ 8205103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 8215103Ssaidi@eecs.umich.edu} 8225103Ssaidi@eecs.umich.edu 8232623SN/A 8242623SN/A//////////////////////////////////////////////////////////////////////// 8252623SN/A// 8262623SN/A// TimingSimpleCPU Simulation Object 8272623SN/A// 8284762Snate@binkert.orgTimingSimpleCPU * 8294762Snate@binkert.orgTimingSimpleCPUParams::create() 8302623SN/A{ 8312623SN/A TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 8324762Snate@binkert.org params->name = name; 8332623SN/A params->numberOfThreads = 1; 8342623SN/A params->max_insts_any_thread = max_insts_any_thread; 8352623SN/A params->max_insts_all_threads = max_insts_all_threads; 8362623SN/A params->max_loads_any_thread = max_loads_any_thread; 8372623SN/A params->max_loads_all_threads = max_loads_all_threads; 8383119Sktlim@umich.edu params->progress_interval = progress_interval; 8392623SN/A params->deferRegistration = defer_registration; 8402623SN/A params->clock = clock; 8413661Srdreslin@umich.edu params->phase = phase; 8422623SN/A params->functionTrace = function_trace; 8432623SN/A params->functionTraceStart = function_trace_start; 8442901Ssaidi@eecs.umich.edu params->system = system; 8453170Sstever@eecs.umich.edu params->cpu_id = cpu_id; 8464776Sgblack@eecs.umich.edu params->tracer = tracer; 8472623SN/A 8482623SN/A params->itb = itb; 8492623SN/A params->dtb = dtb; 8504997Sgblack@eecs.umich.edu#if FULL_SYSTEM 8512623SN/A params->profile = profile; 8523617Sbinkertn@umich.edu params->do_quiesce = do_quiesce; 8533617Sbinkertn@umich.edu params->do_checkpoint_insts = do_checkpoint_insts; 8543617Sbinkertn@umich.edu params->do_statistics_insts = do_statistics_insts; 8552623SN/A#else 8564762Snate@binkert.org if (workload.size() != 1) 8574762Snate@binkert.org panic("only one workload allowed"); 8584762Snate@binkert.org params->process = workload[0]; 8592623SN/A#endif 8602623SN/A 8612623SN/A TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 8622623SN/A return cpu; 8632623SN/A} 864