timing.cc revision 5103
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 325103Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh" 332623SN/A#include "arch/utility.hh" 344040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 352623SN/A#include "cpu/exetrace.hh" 362623SN/A#include "cpu/simple/timing.hh" 373348Sbinkertn@umich.edu#include "mem/packet.hh" 383348Sbinkertn@umich.edu#include "mem/packet_access.hh" 394762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 402901Ssaidi@eecs.umich.edu#include "sim/system.hh" 412623SN/A 422623SN/Ausing namespace std; 432623SN/Ausing namespace TheISA; 442623SN/A 452856Srdreslin@umich.eduPort * 462856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 472856Srdreslin@umich.edu{ 482856Srdreslin@umich.edu if (if_name == "dcache_port") 492856Srdreslin@umich.edu return &dcachePort; 502856Srdreslin@umich.edu else if (if_name == "icache_port") 512856Srdreslin@umich.edu return &icachePort; 522856Srdreslin@umich.edu else 532856Srdreslin@umich.edu panic("No Such Port\n"); 542856Srdreslin@umich.edu} 552623SN/A 562623SN/Avoid 572623SN/ATimingSimpleCPU::init() 582623SN/A{ 592623SN/A BaseCPU::init(); 602623SN/A#if FULL_SYSTEM 612680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 622680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 632623SN/A 642623SN/A // initialize CPU, including PC 652680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 662623SN/A } 672623SN/A#endif 682623SN/A} 692623SN/A 702623SN/ATick 713349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 722623SN/A{ 732623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 742623SN/A return curTick; 752623SN/A} 762623SN/A 772623SN/Avoid 783349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 792623SN/A{ 803184Srdreslin@umich.edu //No internal storage to update, jusst return 813184Srdreslin@umich.edu return; 822623SN/A} 832623SN/A 842623SN/Avoid 852623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 862623SN/A{ 873647Srdreslin@umich.edu if (status == RangeChange) { 883647Srdreslin@umich.edu if (!snoopRangeSent) { 893647Srdreslin@umich.edu snoopRangeSent = true; 903647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 913647Srdreslin@umich.edu } 922631SN/A return; 933647Srdreslin@umich.edu } 942631SN/A 952623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 962623SN/A} 972623SN/A 982948Ssaidi@eecs.umich.edu 992948Ssaidi@eecs.umich.eduvoid 1003349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1012948Ssaidi@eecs.umich.edu{ 1022948Ssaidi@eecs.umich.edu pkt = _pkt; 1032948Ssaidi@eecs.umich.edu Event::schedule(t); 1042948Ssaidi@eecs.umich.edu} 1052948Ssaidi@eecs.umich.edu 1062623SN/ATimingSimpleCPU::TimingSimpleCPU(Params *p) 1073170Sstever@eecs.umich.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), 1083170Sstever@eecs.umich.edu cpu_id(p->cpu_id) 1092623SN/A{ 1102623SN/A _status = Idle; 1113647Srdreslin@umich.edu 1123647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1133647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1143647Srdreslin@umich.edu 1152623SN/A ifetch_pkt = dcache_pkt = NULL; 1162839Sktlim@umich.edu drainEvent = NULL; 1172867Sktlim@umich.edu fetchEvent = NULL; 1183222Sktlim@umich.edu previousTick = 0; 1192901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1202623SN/A} 1212623SN/A 1222623SN/A 1232623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1242623SN/A{ 1252623SN/A} 1262623SN/A 1272623SN/Avoid 1282623SN/ATimingSimpleCPU::serialize(ostream &os) 1292623SN/A{ 1302915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1312915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1322623SN/A BaseSimpleCPU::serialize(os); 1332623SN/A} 1342623SN/A 1352623SN/Avoid 1362623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1372623SN/A{ 1382915Sktlim@umich.edu SimObject::State so_state; 1392915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1402623SN/A BaseSimpleCPU::unserialize(cp, section); 1412798Sktlim@umich.edu} 1422798Sktlim@umich.edu 1432901Ssaidi@eecs.umich.eduunsigned int 1442839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1452798Sktlim@umich.edu{ 1462839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1472798Sktlim@umich.edu // an access to complete. 1482798Sktlim@umich.edu if (status() == Idle || status() == Running || status() == SwitchedOut) { 1492901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1502901Ssaidi@eecs.umich.edu return 0; 1512798Sktlim@umich.edu } else { 1522839Sktlim@umich.edu changeState(SimObject::Draining); 1532839Sktlim@umich.edu drainEvent = drain_event; 1542901Ssaidi@eecs.umich.edu return 1; 1552798Sktlim@umich.edu } 1562623SN/A} 1572623SN/A 1582623SN/Avoid 1592798Sktlim@umich.eduTimingSimpleCPU::resume() 1602623SN/A{ 1612798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1624762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1633201Shsul@eecs.umich.edu 1642867Sktlim@umich.edu // Delete the old event if it existed. 1652867Sktlim@umich.edu if (fetchEvent) { 1662915Sktlim@umich.edu if (fetchEvent->scheduled()) 1672915Sktlim@umich.edu fetchEvent->deschedule(); 1682915Sktlim@umich.edu 1692867Sktlim@umich.edu delete fetchEvent; 1702867Sktlim@umich.edu } 1712867Sktlim@umich.edu 1724471Sstever@eecs.umich.edu fetchEvent = new FetchEvent(this, nextCycle()); 1732623SN/A } 1742798Sktlim@umich.edu 1752901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1762798Sktlim@umich.edu} 1772798Sktlim@umich.edu 1782798Sktlim@umich.eduvoid 1792798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1802798Sktlim@umich.edu{ 1812798Sktlim@umich.edu assert(status() == Running || status() == Idle); 1822798Sktlim@umich.edu _status = SwitchedOut; 1835099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 1842867Sktlim@umich.edu 1852867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1862867Sktlim@umich.edu // we'll need to cancel it. 1872867Sktlim@umich.edu if (fetchEvent && fetchEvent->scheduled()) 1882867Sktlim@umich.edu fetchEvent->deschedule(); 1892623SN/A} 1902623SN/A 1912623SN/A 1922623SN/Avoid 1932623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1942623SN/A{ 1954192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 1962623SN/A 1972680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1982623SN/A // running and schedule its tick event. 1992680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2002680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2012680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2022623SN/A _status = Running; 2032623SN/A break; 2042623SN/A } 2052623SN/A } 2063201Shsul@eecs.umich.edu 2073201Shsul@eecs.umich.edu if (_status != Running) { 2083201Shsul@eecs.umich.edu _status = Idle; 2093201Shsul@eecs.umich.edu } 2105101Ssaidi@eecs.umich.edu previousTick = curTick; 2112623SN/A} 2122623SN/A 2132623SN/A 2142623SN/Avoid 2152623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2162623SN/A{ 2172623SN/A assert(thread_num == 0); 2182683Sktlim@umich.edu assert(thread); 2192623SN/A 2202623SN/A assert(_status == Idle); 2212623SN/A 2222623SN/A notIdleFraction++; 2232623SN/A _status = Running; 2243686Sktlim@umich.edu 2252623SN/A // kick things off by initiating the fetch of the next instruction 2265100Ssaidi@eecs.umich.edu fetchEvent = new FetchEvent(this, nextCycle(curTick + ticks(delay))); 2272623SN/A} 2282623SN/A 2292623SN/A 2302623SN/Avoid 2312623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2322623SN/A{ 2332623SN/A assert(thread_num == 0); 2342683Sktlim@umich.edu assert(thread); 2352623SN/A 2362644Sstever@eecs.umich.edu assert(_status == Running); 2372623SN/A 2382644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2392644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2402623SN/A 2412623SN/A notIdleFraction--; 2422623SN/A _status = Idle; 2432623SN/A} 2442623SN/A 2452623SN/A 2462623SN/Atemplate <class T> 2472623SN/AFault 2482623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2492623SN/A{ 2503169Sstever@eecs.umich.edu Request *req = 2513169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 2523170Sstever@eecs.umich.edu cpu_id, /* thread ID */ 0); 2532623SN/A 2542623SN/A if (traceData) { 2553169Sstever@eecs.umich.edu traceData->setAddr(req->getVaddr()); 2562623SN/A } 2572623SN/A 2582623SN/A // translate to physical address 2593169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2602623SN/A 2612623SN/A // Now do the access. 2622623SN/A if (fault == NoFault) { 2633349Sbinkertn@umich.edu PacketPtr pkt = 2644878Sstever@eecs.umich.edu new Packet(req, 2654878Sstever@eecs.umich.edu (req->isLocked() ? 2664878Sstever@eecs.umich.edu MemCmd::LoadLockedReq : MemCmd::ReadReq), 2674878Sstever@eecs.umich.edu Packet::Broadcast); 2683169Sstever@eecs.umich.edu pkt->dataDynamic<T>(new T); 2692623SN/A 2705103Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) { 2715103Ssaidi@eecs.umich.edu Tick delay; 2725103Ssaidi@eecs.umich.edu delay = TheISA::handleIprRead(thread->getTC(), pkt); 2735103Ssaidi@eecs.umich.edu new IprEvent(pkt, this, nextCycle(curTick + delay)); 2745103Ssaidi@eecs.umich.edu _status = DcacheWaitResponse; 2755103Ssaidi@eecs.umich.edu dcache_pkt = NULL; 2765103Ssaidi@eecs.umich.edu } else if (!dcachePort.sendTiming(pkt)) { 2772623SN/A _status = DcacheRetry; 2783169Sstever@eecs.umich.edu dcache_pkt = pkt; 2792623SN/A } else { 2802623SN/A _status = DcacheWaitResponse; 2813169Sstever@eecs.umich.edu // memory system takes ownership of packet 2822623SN/A dcache_pkt = NULL; 2832623SN/A } 2844200Ssaidi@eecs.umich.edu 2854200Ssaidi@eecs.umich.edu // This will need a new way to tell if it has a dcache attached. 2864200Ssaidi@eecs.umich.edu if (req->isUncacheable()) 2874200Ssaidi@eecs.umich.edu recordEvent("Uncached Read"); 2883658Sktlim@umich.edu } else { 2893658Sktlim@umich.edu delete req; 2902623SN/A } 2912623SN/A 2922623SN/A return fault; 2932623SN/A} 2942623SN/A 2952623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 2962623SN/A 2972623SN/Atemplate 2982623SN/AFault 2994040Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 3004040Ssaidi@eecs.umich.edu 3014040Ssaidi@eecs.umich.edutemplate 3024040Ssaidi@eecs.umich.eduFault 3034115Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 3044115Ssaidi@eecs.umich.edu 3054115Ssaidi@eecs.umich.edutemplate 3064115Ssaidi@eecs.umich.eduFault 3072623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 3082623SN/A 3092623SN/Atemplate 3102623SN/AFault 3112623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3122623SN/A 3132623SN/Atemplate 3142623SN/AFault 3152623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 3162623SN/A 3172623SN/Atemplate 3182623SN/AFault 3192623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3202623SN/A 3212623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3222623SN/A 3232623SN/Atemplate<> 3242623SN/AFault 3252623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 3262623SN/A{ 3272623SN/A return read(addr, *(uint64_t*)&data, flags); 3282623SN/A} 3292623SN/A 3302623SN/Atemplate<> 3312623SN/AFault 3322623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 3332623SN/A{ 3342623SN/A return read(addr, *(uint32_t*)&data, flags); 3352623SN/A} 3362623SN/A 3372623SN/A 3382623SN/Atemplate<> 3392623SN/AFault 3402623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3412623SN/A{ 3422623SN/A return read(addr, (uint32_t&)data, flags); 3432623SN/A} 3442623SN/A 3452623SN/A 3462623SN/Atemplate <class T> 3472623SN/AFault 3482623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3492623SN/A{ 3503169Sstever@eecs.umich.edu Request *req = 3513169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 3523170Sstever@eecs.umich.edu cpu_id, /* thread ID */ 0); 3532623SN/A 3544040Ssaidi@eecs.umich.edu if (traceData) { 3554040Ssaidi@eecs.umich.edu traceData->setAddr(req->getVaddr()); 3564040Ssaidi@eecs.umich.edu } 3574040Ssaidi@eecs.umich.edu 3582623SN/A // translate to physical address 3593169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3603169Sstever@eecs.umich.edu 3612623SN/A // Now do the access. 3622623SN/A if (fault == NoFault) { 3634878Sstever@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 3643170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3653170Sstever@eecs.umich.edu 3663170Sstever@eecs.umich.edu if (req->isLocked()) { 3674878Sstever@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3683170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3694878Sstever@eecs.umich.edu } else if (req->isSwap()) { 3704878Sstever@eecs.umich.edu cmd = MemCmd::SwapReq; 3714878Sstever@eecs.umich.edu if (req->isCondSwap()) { 3724878Sstever@eecs.umich.edu assert(res); 3734878Sstever@eecs.umich.edu req->setExtraData(*res); 3744878Sstever@eecs.umich.edu } 3753170Sstever@eecs.umich.edu } 3764584Ssaidi@eecs.umich.edu 3774881Sstever@eecs.umich.edu // Note: need to allocate dcache_pkt even if do_access is 3784881Sstever@eecs.umich.edu // false, as it's used unconditionally to call completeAcc(). 3794881Sstever@eecs.umich.edu assert(dcache_pkt == NULL); 3804881Sstever@eecs.umich.edu dcache_pkt = new Packet(req, cmd, Packet::Broadcast); 3814881Sstever@eecs.umich.edu dcache_pkt->allocate(); 3824881Sstever@eecs.umich.edu dcache_pkt->set(data); 3833170Sstever@eecs.umich.edu 3843170Sstever@eecs.umich.edu if (do_access) { 3855103Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) { 3865103Ssaidi@eecs.umich.edu Tick delay; 3875103Ssaidi@eecs.umich.edu dcache_pkt->set(htog(data)); 3885103Ssaidi@eecs.umich.edu delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 3895103Ssaidi@eecs.umich.edu new IprEvent(dcache_pkt, this, nextCycle(curTick + delay)); 3905103Ssaidi@eecs.umich.edu _status = DcacheWaitResponse; 3915103Ssaidi@eecs.umich.edu dcache_pkt = NULL; 3925103Ssaidi@eecs.umich.edu } else if (!dcachePort.sendTiming(dcache_pkt)) { 3933170Sstever@eecs.umich.edu _status = DcacheRetry; 3943170Sstever@eecs.umich.edu } else { 3953170Sstever@eecs.umich.edu _status = DcacheWaitResponse; 3963170Sstever@eecs.umich.edu // memory system takes ownership of packet 3973170Sstever@eecs.umich.edu dcache_pkt = NULL; 3983170Sstever@eecs.umich.edu } 3992623SN/A } 4004200Ssaidi@eecs.umich.edu // This will need a new way to tell if it's hooked up to a cache or not. 4014200Ssaidi@eecs.umich.edu if (req->isUncacheable()) 4024200Ssaidi@eecs.umich.edu recordEvent("Uncached Write"); 4033658Sktlim@umich.edu } else { 4043658Sktlim@umich.edu delete req; 4052623SN/A } 4062623SN/A 4072623SN/A 4082623SN/A // If the write needs to have a fault on the access, consider calling 4092623SN/A // changeStatus() and changing it to "bad addr write" or something. 4102623SN/A return fault; 4112623SN/A} 4122623SN/A 4132623SN/A 4142623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4152623SN/Atemplate 4162623SN/AFault 4174224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin32_t data, Addr addr, 4184224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4194224Sgblack@eecs.umich.edu 4204224Sgblack@eecs.umich.edutemplate 4214224Sgblack@eecs.umich.eduFault 4224224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin64_t data, Addr addr, 4234224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4244224Sgblack@eecs.umich.edu 4254224Sgblack@eecs.umich.edutemplate 4264224Sgblack@eecs.umich.eduFault 4272623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 4282623SN/A unsigned flags, uint64_t *res); 4292623SN/A 4302623SN/Atemplate 4312623SN/AFault 4322623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 4332623SN/A unsigned flags, uint64_t *res); 4342623SN/A 4352623SN/Atemplate 4362623SN/AFault 4372623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 4382623SN/A unsigned flags, uint64_t *res); 4392623SN/A 4402623SN/Atemplate 4412623SN/AFault 4422623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 4432623SN/A unsigned flags, uint64_t *res); 4442623SN/A 4452623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4462623SN/A 4472623SN/Atemplate<> 4482623SN/AFault 4492623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 4502623SN/A{ 4512623SN/A return write(*(uint64_t*)&data, addr, flags, res); 4522623SN/A} 4532623SN/A 4542623SN/Atemplate<> 4552623SN/AFault 4562623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 4572623SN/A{ 4582623SN/A return write(*(uint32_t*)&data, addr, flags, res); 4592623SN/A} 4602623SN/A 4612623SN/A 4622623SN/Atemplate<> 4632623SN/AFault 4642623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 4652623SN/A{ 4662623SN/A return write((uint32_t)data, addr, flags, res); 4672623SN/A} 4682623SN/A 4692623SN/A 4702623SN/Avoid 4712623SN/ATimingSimpleCPU::fetch() 4722623SN/A{ 4733387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 4743387Sgblack@eecs.umich.edu checkForInterrupts(); 4752631SN/A 4762663Sstever@eecs.umich.edu Request *ifetch_req = new Request(); 4773170Sstever@eecs.umich.edu ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0); 4782662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 4792623SN/A 4804022Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast); 4812623SN/A ifetch_pkt->dataStatic(&inst); 4822623SN/A 4832623SN/A if (fault == NoFault) { 4842630SN/A if (!icachePort.sendTiming(ifetch_pkt)) { 4852623SN/A // Need to wait for retry 4862623SN/A _status = IcacheRetry; 4872623SN/A } else { 4882623SN/A // Need to wait for cache to respond 4892623SN/A _status = IcacheWaitResponse; 4902623SN/A // ownership of packet transferred to memory system 4912623SN/A ifetch_pkt = NULL; 4922623SN/A } 4932623SN/A } else { 4943658Sktlim@umich.edu delete ifetch_req; 4953658Sktlim@umich.edu delete ifetch_pkt; 4962644Sstever@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 4972644Sstever@eecs.umich.edu advanceInst(fault); 4982623SN/A } 4993222Sktlim@umich.edu 5005099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 5013222Sktlim@umich.edu previousTick = curTick; 5022623SN/A} 5032623SN/A 5042623SN/A 5052623SN/Avoid 5062644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 5072623SN/A{ 5082623SN/A advancePC(fault); 5092623SN/A 5102631SN/A if (_status == Running) { 5112631SN/A // kick off fetch of next instruction... callback from icache 5122631SN/A // response will cause that instruction to be executed, 5132631SN/A // keeping the CPU running. 5142631SN/A fetch(); 5152631SN/A } 5162623SN/A} 5172623SN/A 5182623SN/A 5192623SN/Avoid 5203349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 5212623SN/A{ 5222623SN/A // received a response from the icache: execute the received 5232623SN/A // instruction 5244870Sstever@eecs.umich.edu assert(!pkt->isError()); 5252623SN/A assert(_status == IcacheWaitResponse); 5262798Sktlim@umich.edu 5272623SN/A _status = Running; 5282644Sstever@eecs.umich.edu 5295099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 5303222Sktlim@umich.edu previousTick = curTick; 5313222Sktlim@umich.edu 5322839Sktlim@umich.edu if (getState() == SimObject::Draining) { 5333658Sktlim@umich.edu delete pkt->req; 5343658Sktlim@umich.edu delete pkt; 5353658Sktlim@umich.edu 5362839Sktlim@umich.edu completeDrain(); 5372798Sktlim@umich.edu return; 5382798Sktlim@umich.edu } 5392798Sktlim@umich.edu 5402623SN/A preExecute(); 5412644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 5422623SN/A // load or store: just send to dcache 5432623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 5443170Sstever@eecs.umich.edu if (_status != Running) { 5453170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 5463170Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DcacheRetry); 5473170Sstever@eecs.umich.edu assert(fault == NoFault); 5482644Sstever@eecs.umich.edu } else { 5493170Sstever@eecs.umich.edu if (fault == NoFault) { 5503170Sstever@eecs.umich.edu // early fail on store conditional: complete now 5513170Sstever@eecs.umich.edu assert(dcache_pkt != NULL); 5523170Sstever@eecs.umich.edu fault = curStaticInst->completeAcc(dcache_pkt, this, 5533170Sstever@eecs.umich.edu traceData); 5543170Sstever@eecs.umich.edu delete dcache_pkt->req; 5553170Sstever@eecs.umich.edu delete dcache_pkt; 5563170Sstever@eecs.umich.edu dcache_pkt = NULL; 5574998Sgblack@eecs.umich.edu 5584998Sgblack@eecs.umich.edu // keep an instruction count 5594998Sgblack@eecs.umich.edu if (fault == NoFault) 5604998Sgblack@eecs.umich.edu countInst(); 5615001Sgblack@eecs.umich.edu } else if (traceData) { 5625001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 5635001Sgblack@eecs.umich.edu delete traceData; 5645001Sgblack@eecs.umich.edu traceData = NULL; 5653170Sstever@eecs.umich.edu } 5664998Sgblack@eecs.umich.edu 5672644Sstever@eecs.umich.edu postExecute(); 5685103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 5695103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 5705103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 5715103Ssaidi@eecs.umich.edu instCnt++; 5722644Sstever@eecs.umich.edu advanceInst(fault); 5732644Sstever@eecs.umich.edu } 5742623SN/A } else { 5752623SN/A // non-memory instruction: execute completely now 5762623SN/A Fault fault = curStaticInst->execute(this, traceData); 5774998Sgblack@eecs.umich.edu 5784998Sgblack@eecs.umich.edu // keep an instruction count 5794998Sgblack@eecs.umich.edu if (fault == NoFault) 5804998Sgblack@eecs.umich.edu countInst(); 5815001Sgblack@eecs.umich.edu else if (traceData) { 5825001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 5835001Sgblack@eecs.umich.edu delete traceData; 5845001Sgblack@eecs.umich.edu traceData = NULL; 5855001Sgblack@eecs.umich.edu } 5864998Sgblack@eecs.umich.edu 5872644Sstever@eecs.umich.edu postExecute(); 5885103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 5895103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 5905103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 5915103Ssaidi@eecs.umich.edu instCnt++; 5922644Sstever@eecs.umich.edu advanceInst(fault); 5932623SN/A } 5943658Sktlim@umich.edu 5953658Sktlim@umich.edu delete pkt->req; 5963658Sktlim@umich.edu delete pkt; 5972623SN/A} 5982623SN/A 5992948Ssaidi@eecs.umich.eduvoid 6002948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 6012948Ssaidi@eecs.umich.edu{ 6022948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 6032948Ssaidi@eecs.umich.edu} 6042623SN/A 6052623SN/Abool 6063349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 6072623SN/A{ 6084986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 6093310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 6104584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 6112948Ssaidi@eecs.umich.edu 6123495Sktlim@umich.edu if (next_tick == curTick) 6133310Srdreslin@umich.edu cpu->completeIfetch(pkt); 6143310Srdreslin@umich.edu else 6153495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 6162948Ssaidi@eecs.umich.edu 6173310Srdreslin@umich.edu return true; 6183310Srdreslin@umich.edu } 6194870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 6204433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 6214433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 6224433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 6234433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 6244433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 6254433Ssaidi@eecs.umich.edu } 6263310Srdreslin@umich.edu } 6274433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 6284433Ssaidi@eecs.umich.edu return true; 6292623SN/A} 6302623SN/A 6312657Ssaidi@eecs.umich.eduvoid 6322623SN/ATimingSimpleCPU::IcachePort::recvRetry() 6332623SN/A{ 6342623SN/A // we shouldn't get a retry unless we have a packet that we're 6352623SN/A // waiting to transmit 6362623SN/A assert(cpu->ifetch_pkt != NULL); 6372623SN/A assert(cpu->_status == IcacheRetry); 6383349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 6392657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 6402657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 6412657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 6422657Ssaidi@eecs.umich.edu } 6432623SN/A} 6442623SN/A 6452623SN/Avoid 6463349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 6472623SN/A{ 6482623SN/A // received a response from the dcache: complete the load or store 6492623SN/A // instruction 6504870Sstever@eecs.umich.edu assert(!pkt->isError()); 6512623SN/A assert(_status == DcacheWaitResponse); 6522623SN/A _status = Running; 6532623SN/A 6545099Ssaidi@eecs.umich.edu numCycles += tickToCycles(curTick - previousTick); 6553222Sktlim@umich.edu previousTick = curTick; 6563184Srdreslin@umich.edu 6572623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 6582623SN/A 6594998Sgblack@eecs.umich.edu // keep an instruction count 6604998Sgblack@eecs.umich.edu if (fault == NoFault) 6614998Sgblack@eecs.umich.edu countInst(); 6625001Sgblack@eecs.umich.edu else if (traceData) { 6635001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6645001Sgblack@eecs.umich.edu delete traceData; 6655001Sgblack@eecs.umich.edu traceData = NULL; 6665001Sgblack@eecs.umich.edu } 6674998Sgblack@eecs.umich.edu 6684878Sstever@eecs.umich.edu if (pkt->isRead() && pkt->isLocked()) { 6693170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 6703170Sstever@eecs.umich.edu } 6713170Sstever@eecs.umich.edu 6722644Sstever@eecs.umich.edu delete pkt->req; 6732644Sstever@eecs.umich.edu delete pkt; 6742644Sstever@eecs.umich.edu 6753184Srdreslin@umich.edu postExecute(); 6763227Sktlim@umich.edu 6773201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 6783201Shsul@eecs.umich.edu advancePC(fault); 6793201Shsul@eecs.umich.edu completeDrain(); 6803201Shsul@eecs.umich.edu 6813201Shsul@eecs.umich.edu return; 6823201Shsul@eecs.umich.edu } 6833201Shsul@eecs.umich.edu 6842644Sstever@eecs.umich.edu advanceInst(fault); 6852623SN/A} 6862623SN/A 6872623SN/A 6882798Sktlim@umich.eduvoid 6892839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 6902798Sktlim@umich.edu{ 6912839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 6922901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 6932839Sktlim@umich.edu drainEvent->process(); 6942798Sktlim@umich.edu} 6952623SN/A 6964192Sktlim@umich.eduvoid 6974192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 6984192Sktlim@umich.edu{ 6994192Sktlim@umich.edu Port::setPeer(port); 7004192Sktlim@umich.edu 7014192Sktlim@umich.edu#if FULL_SYSTEM 7024192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 7034192Sktlim@umich.edu // Ports) 7044192Sktlim@umich.edu cpu->tcBase()->connectMemPorts(); 7054192Sktlim@umich.edu#endif 7064192Sktlim@umich.edu} 7074192Sktlim@umich.edu 7082623SN/Abool 7093349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 7102623SN/A{ 7114986Ssaidi@eecs.umich.edu if (pkt->isResponse() && !pkt->wasNacked()) { 7123310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 7134584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 7142948Ssaidi@eecs.umich.edu 7153495Sktlim@umich.edu if (next_tick == curTick) 7163310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 7173310Srdreslin@umich.edu else 7183495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 7192948Ssaidi@eecs.umich.edu 7203310Srdreslin@umich.edu return true; 7213310Srdreslin@umich.edu } 7224870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 7234433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 7244433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 7254433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 7264433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 7274433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 7284433Ssaidi@eecs.umich.edu } 7293310Srdreslin@umich.edu } 7304433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 7314433Ssaidi@eecs.umich.edu return true; 7322948Ssaidi@eecs.umich.edu} 7332948Ssaidi@eecs.umich.edu 7342948Ssaidi@eecs.umich.eduvoid 7352948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 7362948Ssaidi@eecs.umich.edu{ 7372630SN/A cpu->completeDataAccess(pkt); 7382623SN/A} 7392623SN/A 7402657Ssaidi@eecs.umich.eduvoid 7412623SN/ATimingSimpleCPU::DcachePort::recvRetry() 7422623SN/A{ 7432623SN/A // we shouldn't get a retry unless we have a packet that we're 7442623SN/A // waiting to transmit 7452623SN/A assert(cpu->dcache_pkt != NULL); 7462623SN/A assert(cpu->_status == DcacheRetry); 7473349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 7482657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 7492657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 7503170Sstever@eecs.umich.edu // memory system takes ownership of packet 7512657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 7522657Ssaidi@eecs.umich.edu } 7532623SN/A} 7542623SN/A 7555103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t) 7565103Ssaidi@eecs.umich.edu : Event(&mainEventQueue), pkt(_pkt), cpu(_cpu) 7575103Ssaidi@eecs.umich.edu{ 7585103Ssaidi@eecs.umich.edu schedule(t); 7595103Ssaidi@eecs.umich.edu} 7605103Ssaidi@eecs.umich.edu 7615103Ssaidi@eecs.umich.eduvoid 7625103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 7635103Ssaidi@eecs.umich.edu{ 7645103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 7655103Ssaidi@eecs.umich.edu} 7665103Ssaidi@eecs.umich.edu 7675103Ssaidi@eecs.umich.educonst char * 7685103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::description() 7695103Ssaidi@eecs.umich.edu{ 7705103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 7715103Ssaidi@eecs.umich.edu} 7725103Ssaidi@eecs.umich.edu 7732623SN/A 7742623SN/A//////////////////////////////////////////////////////////////////////// 7752623SN/A// 7762623SN/A// TimingSimpleCPU Simulation Object 7772623SN/A// 7784762Snate@binkert.orgTimingSimpleCPU * 7794762Snate@binkert.orgTimingSimpleCPUParams::create() 7802623SN/A{ 7812623SN/A TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 7824762Snate@binkert.org params->name = name; 7832623SN/A params->numberOfThreads = 1; 7842623SN/A params->max_insts_any_thread = max_insts_any_thread; 7852623SN/A params->max_insts_all_threads = max_insts_all_threads; 7862623SN/A params->max_loads_any_thread = max_loads_any_thread; 7872623SN/A params->max_loads_all_threads = max_loads_all_threads; 7883119Sktlim@umich.edu params->progress_interval = progress_interval; 7892623SN/A params->deferRegistration = defer_registration; 7902623SN/A params->clock = clock; 7913661Srdreslin@umich.edu params->phase = phase; 7922623SN/A params->functionTrace = function_trace; 7932623SN/A params->functionTraceStart = function_trace_start; 7942901Ssaidi@eecs.umich.edu params->system = system; 7953170Sstever@eecs.umich.edu params->cpu_id = cpu_id; 7964776Sgblack@eecs.umich.edu params->tracer = tracer; 7972623SN/A 7982623SN/A params->itb = itb; 7992623SN/A params->dtb = dtb; 8004997Sgblack@eecs.umich.edu#if FULL_SYSTEM 8012623SN/A params->profile = profile; 8023617Sbinkertn@umich.edu params->do_quiesce = do_quiesce; 8033617Sbinkertn@umich.edu params->do_checkpoint_insts = do_checkpoint_insts; 8043617Sbinkertn@umich.edu params->do_statistics_insts = do_statistics_insts; 8052623SN/A#else 8064762Snate@binkert.org if (workload.size() != 1) 8074762Snate@binkert.org panic("only one workload allowed"); 8084762Snate@binkert.org params->process = workload[0]; 8092623SN/A#endif 8102623SN/A 8112623SN/A TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 8122623SN/A return cpu; 8132623SN/A} 814