timing.cc revision 5001
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 322623SN/A#include "arch/utility.hh" 334040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 342623SN/A#include "cpu/exetrace.hh" 352623SN/A#include "cpu/simple/timing.hh" 363348Sbinkertn@umich.edu#include "mem/packet.hh" 373348Sbinkertn@umich.edu#include "mem/packet_access.hh" 384762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 392901Ssaidi@eecs.umich.edu#include "sim/system.hh" 402623SN/A 412623SN/Ausing namespace std; 422623SN/Ausing namespace TheISA; 432623SN/A 442856Srdreslin@umich.eduPort * 452856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 462856Srdreslin@umich.edu{ 472856Srdreslin@umich.edu if (if_name == "dcache_port") 482856Srdreslin@umich.edu return &dcachePort; 492856Srdreslin@umich.edu else if (if_name == "icache_port") 502856Srdreslin@umich.edu return &icachePort; 512856Srdreslin@umich.edu else 522856Srdreslin@umich.edu panic("No Such Port\n"); 532856Srdreslin@umich.edu} 542623SN/A 552623SN/Avoid 562623SN/ATimingSimpleCPU::init() 572623SN/A{ 582623SN/A BaseCPU::init(); 592623SN/A#if FULL_SYSTEM 602680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 612680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 622623SN/A 632623SN/A // initialize CPU, including PC 642680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 652623SN/A } 662623SN/A#endif 672623SN/A} 682623SN/A 692623SN/ATick 703349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 712623SN/A{ 722623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 732623SN/A return curTick; 742623SN/A} 752623SN/A 762623SN/Avoid 773349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 782623SN/A{ 793184Srdreslin@umich.edu //No internal storage to update, jusst return 803184Srdreslin@umich.edu return; 812623SN/A} 822623SN/A 832623SN/Avoid 842623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 852623SN/A{ 863647Srdreslin@umich.edu if (status == RangeChange) { 873647Srdreslin@umich.edu if (!snoopRangeSent) { 883647Srdreslin@umich.edu snoopRangeSent = true; 893647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 903647Srdreslin@umich.edu } 912631SN/A return; 923647Srdreslin@umich.edu } 932631SN/A 942623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 952623SN/A} 962623SN/A 972948Ssaidi@eecs.umich.edu 982948Ssaidi@eecs.umich.eduvoid 993349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1002948Ssaidi@eecs.umich.edu{ 1012948Ssaidi@eecs.umich.edu pkt = _pkt; 1022948Ssaidi@eecs.umich.edu Event::schedule(t); 1032948Ssaidi@eecs.umich.edu} 1042948Ssaidi@eecs.umich.edu 1052623SN/ATimingSimpleCPU::TimingSimpleCPU(Params *p) 1063170Sstever@eecs.umich.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), 1073170Sstever@eecs.umich.edu cpu_id(p->cpu_id) 1082623SN/A{ 1092623SN/A _status = Idle; 1103647Srdreslin@umich.edu 1113647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1123647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1133647Srdreslin@umich.edu 1142623SN/A ifetch_pkt = dcache_pkt = NULL; 1152839Sktlim@umich.edu drainEvent = NULL; 1162867Sktlim@umich.edu fetchEvent = NULL; 1173222Sktlim@umich.edu previousTick = 0; 1182901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1192623SN/A} 1202623SN/A 1212623SN/A 1222623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1232623SN/A{ 1242623SN/A} 1252623SN/A 1262623SN/Avoid 1272623SN/ATimingSimpleCPU::serialize(ostream &os) 1282623SN/A{ 1292915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1302915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1312623SN/A BaseSimpleCPU::serialize(os); 1322623SN/A} 1332623SN/A 1342623SN/Avoid 1352623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1362623SN/A{ 1372915Sktlim@umich.edu SimObject::State so_state; 1382915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1392623SN/A BaseSimpleCPU::unserialize(cp, section); 1402798Sktlim@umich.edu} 1412798Sktlim@umich.edu 1422901Ssaidi@eecs.umich.eduunsigned int 1432839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1442798Sktlim@umich.edu{ 1452839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1462798Sktlim@umich.edu // an access to complete. 1472798Sktlim@umich.edu if (status() == Idle || status() == Running || status() == SwitchedOut) { 1482901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1492901Ssaidi@eecs.umich.edu return 0; 1502798Sktlim@umich.edu } else { 1512839Sktlim@umich.edu changeState(SimObject::Draining); 1522839Sktlim@umich.edu drainEvent = drain_event; 1532901Ssaidi@eecs.umich.edu return 1; 1542798Sktlim@umich.edu } 1552623SN/A} 1562623SN/A 1572623SN/Avoid 1582798Sktlim@umich.eduTimingSimpleCPU::resume() 1592623SN/A{ 1602798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1614762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 1623201Shsul@eecs.umich.edu 1632867Sktlim@umich.edu // Delete the old event if it existed. 1642867Sktlim@umich.edu if (fetchEvent) { 1652915Sktlim@umich.edu if (fetchEvent->scheduled()) 1662915Sktlim@umich.edu fetchEvent->deschedule(); 1672915Sktlim@umich.edu 1682867Sktlim@umich.edu delete fetchEvent; 1692867Sktlim@umich.edu } 1702867Sktlim@umich.edu 1714471Sstever@eecs.umich.edu fetchEvent = new FetchEvent(this, nextCycle()); 1722623SN/A } 1732798Sktlim@umich.edu 1742901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1753222Sktlim@umich.edu previousTick = curTick; 1762798Sktlim@umich.edu} 1772798Sktlim@umich.edu 1782798Sktlim@umich.eduvoid 1792798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1802798Sktlim@umich.edu{ 1812798Sktlim@umich.edu assert(status() == Running || status() == Idle); 1822798Sktlim@umich.edu _status = SwitchedOut; 1833222Sktlim@umich.edu numCycles += curTick - previousTick; 1842867Sktlim@umich.edu 1852867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1862867Sktlim@umich.edu // we'll need to cancel it. 1872867Sktlim@umich.edu if (fetchEvent && fetchEvent->scheduled()) 1882867Sktlim@umich.edu fetchEvent->deschedule(); 1892623SN/A} 1902623SN/A 1912623SN/A 1922623SN/Avoid 1932623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1942623SN/A{ 1954192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 1962623SN/A 1972680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1982623SN/A // running and schedule its tick event. 1992680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2002680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2012680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2022623SN/A _status = Running; 2032623SN/A break; 2042623SN/A } 2052623SN/A } 2063201Shsul@eecs.umich.edu 2073201Shsul@eecs.umich.edu if (_status != Running) { 2083201Shsul@eecs.umich.edu _status = Idle; 2093201Shsul@eecs.umich.edu } 2102623SN/A} 2112623SN/A 2122623SN/A 2132623SN/Avoid 2142623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2152623SN/A{ 2162623SN/A assert(thread_num == 0); 2172683Sktlim@umich.edu assert(thread); 2182623SN/A 2192623SN/A assert(_status == Idle); 2202623SN/A 2212623SN/A notIdleFraction++; 2222623SN/A _status = Running; 2233686Sktlim@umich.edu 2242623SN/A // kick things off by initiating the fetch of the next instruction 2254471Sstever@eecs.umich.edu fetchEvent = new FetchEvent(this, nextCycle(curTick + cycles(delay))); 2262623SN/A} 2272623SN/A 2282623SN/A 2292623SN/Avoid 2302623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2312623SN/A{ 2322623SN/A assert(thread_num == 0); 2332683Sktlim@umich.edu assert(thread); 2342623SN/A 2352644Sstever@eecs.umich.edu assert(_status == Running); 2362623SN/A 2372644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2382644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2392623SN/A 2402623SN/A notIdleFraction--; 2412623SN/A _status = Idle; 2422623SN/A} 2432623SN/A 2442623SN/A 2452623SN/Atemplate <class T> 2462623SN/AFault 2472623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2482623SN/A{ 2493169Sstever@eecs.umich.edu Request *req = 2503169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 2513170Sstever@eecs.umich.edu cpu_id, /* thread ID */ 0); 2522623SN/A 2532623SN/A if (traceData) { 2543169Sstever@eecs.umich.edu traceData->setAddr(req->getVaddr()); 2552623SN/A } 2562623SN/A 2572623SN/A // translate to physical address 2583169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2592623SN/A 2602623SN/A // Now do the access. 2612623SN/A if (fault == NoFault) { 2623349Sbinkertn@umich.edu PacketPtr pkt = 2634878Sstever@eecs.umich.edu new Packet(req, 2644878Sstever@eecs.umich.edu (req->isLocked() ? 2654878Sstever@eecs.umich.edu MemCmd::LoadLockedReq : MemCmd::ReadReq), 2664878Sstever@eecs.umich.edu Packet::Broadcast); 2673169Sstever@eecs.umich.edu pkt->dataDynamic<T>(new T); 2682623SN/A 2693169Sstever@eecs.umich.edu if (!dcachePort.sendTiming(pkt)) { 2702623SN/A _status = DcacheRetry; 2713169Sstever@eecs.umich.edu dcache_pkt = pkt; 2722623SN/A } else { 2732623SN/A _status = DcacheWaitResponse; 2743169Sstever@eecs.umich.edu // memory system takes ownership of packet 2752623SN/A dcache_pkt = NULL; 2762623SN/A } 2774200Ssaidi@eecs.umich.edu 2784200Ssaidi@eecs.umich.edu // This will need a new way to tell if it has a dcache attached. 2794200Ssaidi@eecs.umich.edu if (req->isUncacheable()) 2804200Ssaidi@eecs.umich.edu recordEvent("Uncached Read"); 2813658Sktlim@umich.edu } else { 2823658Sktlim@umich.edu delete req; 2832623SN/A } 2842623SN/A 2852623SN/A return fault; 2862623SN/A} 2872623SN/A 2882623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 2892623SN/A 2902623SN/Atemplate 2912623SN/AFault 2924040Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 2934040Ssaidi@eecs.umich.edu 2944040Ssaidi@eecs.umich.edutemplate 2954040Ssaidi@eecs.umich.eduFault 2964115Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 2974115Ssaidi@eecs.umich.edu 2984115Ssaidi@eecs.umich.edutemplate 2994115Ssaidi@eecs.umich.eduFault 3002623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 3012623SN/A 3022623SN/Atemplate 3032623SN/AFault 3042623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3052623SN/A 3062623SN/Atemplate 3072623SN/AFault 3082623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 3092623SN/A 3102623SN/Atemplate 3112623SN/AFault 3122623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3132623SN/A 3142623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3152623SN/A 3162623SN/Atemplate<> 3172623SN/AFault 3182623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 3192623SN/A{ 3202623SN/A return read(addr, *(uint64_t*)&data, flags); 3212623SN/A} 3222623SN/A 3232623SN/Atemplate<> 3242623SN/AFault 3252623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 3262623SN/A{ 3272623SN/A return read(addr, *(uint32_t*)&data, flags); 3282623SN/A} 3292623SN/A 3302623SN/A 3312623SN/Atemplate<> 3322623SN/AFault 3332623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3342623SN/A{ 3352623SN/A return read(addr, (uint32_t&)data, flags); 3362623SN/A} 3372623SN/A 3382623SN/A 3392623SN/Atemplate <class T> 3402623SN/AFault 3412623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3422623SN/A{ 3433169Sstever@eecs.umich.edu Request *req = 3443169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 3453170Sstever@eecs.umich.edu cpu_id, /* thread ID */ 0); 3462623SN/A 3474040Ssaidi@eecs.umich.edu if (traceData) { 3484040Ssaidi@eecs.umich.edu traceData->setAddr(req->getVaddr()); 3494040Ssaidi@eecs.umich.edu } 3504040Ssaidi@eecs.umich.edu 3512623SN/A // translate to physical address 3523169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3533169Sstever@eecs.umich.edu 3542623SN/A // Now do the access. 3552623SN/A if (fault == NoFault) { 3564878Sstever@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 3573170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3583170Sstever@eecs.umich.edu 3593170Sstever@eecs.umich.edu if (req->isLocked()) { 3604878Sstever@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3613170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3624878Sstever@eecs.umich.edu } else if (req->isSwap()) { 3634878Sstever@eecs.umich.edu cmd = MemCmd::SwapReq; 3644878Sstever@eecs.umich.edu if (req->isCondSwap()) { 3654878Sstever@eecs.umich.edu assert(res); 3664878Sstever@eecs.umich.edu req->setExtraData(*res); 3674878Sstever@eecs.umich.edu } 3683170Sstever@eecs.umich.edu } 3694584Ssaidi@eecs.umich.edu 3704881Sstever@eecs.umich.edu // Note: need to allocate dcache_pkt even if do_access is 3714881Sstever@eecs.umich.edu // false, as it's used unconditionally to call completeAcc(). 3724881Sstever@eecs.umich.edu assert(dcache_pkt == NULL); 3734881Sstever@eecs.umich.edu dcache_pkt = new Packet(req, cmd, Packet::Broadcast); 3744881Sstever@eecs.umich.edu dcache_pkt->allocate(); 3754881Sstever@eecs.umich.edu dcache_pkt->set(data); 3763170Sstever@eecs.umich.edu 3773170Sstever@eecs.umich.edu if (do_access) { 3783170Sstever@eecs.umich.edu if (!dcachePort.sendTiming(dcache_pkt)) { 3793170Sstever@eecs.umich.edu _status = DcacheRetry; 3803170Sstever@eecs.umich.edu } else { 3813170Sstever@eecs.umich.edu _status = DcacheWaitResponse; 3823170Sstever@eecs.umich.edu // memory system takes ownership of packet 3833170Sstever@eecs.umich.edu dcache_pkt = NULL; 3843170Sstever@eecs.umich.edu } 3852623SN/A } 3864200Ssaidi@eecs.umich.edu // This will need a new way to tell if it's hooked up to a cache or not. 3874200Ssaidi@eecs.umich.edu if (req->isUncacheable()) 3884200Ssaidi@eecs.umich.edu recordEvent("Uncached Write"); 3893658Sktlim@umich.edu } else { 3903658Sktlim@umich.edu delete req; 3912623SN/A } 3922623SN/A 3932623SN/A 3942623SN/A // If the write needs to have a fault on the access, consider calling 3952623SN/A // changeStatus() and changing it to "bad addr write" or something. 3962623SN/A return fault; 3972623SN/A} 3982623SN/A 3992623SN/A 4002623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4012623SN/Atemplate 4022623SN/AFault 4034224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin32_t data, Addr addr, 4044224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4054224Sgblack@eecs.umich.edu 4064224Sgblack@eecs.umich.edutemplate 4074224Sgblack@eecs.umich.eduFault 4084224Sgblack@eecs.umich.eduTimingSimpleCPU::write(Twin64_t data, Addr addr, 4094224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4104224Sgblack@eecs.umich.edu 4114224Sgblack@eecs.umich.edutemplate 4124224Sgblack@eecs.umich.eduFault 4132623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 4142623SN/A unsigned flags, uint64_t *res); 4152623SN/A 4162623SN/Atemplate 4172623SN/AFault 4182623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 4192623SN/A unsigned flags, uint64_t *res); 4202623SN/A 4212623SN/Atemplate 4222623SN/AFault 4232623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 4242623SN/A unsigned flags, uint64_t *res); 4252623SN/A 4262623SN/Atemplate 4272623SN/AFault 4282623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 4292623SN/A unsigned flags, uint64_t *res); 4302623SN/A 4312623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4322623SN/A 4332623SN/Atemplate<> 4342623SN/AFault 4352623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 4362623SN/A{ 4372623SN/A return write(*(uint64_t*)&data, addr, flags, res); 4382623SN/A} 4392623SN/A 4402623SN/Atemplate<> 4412623SN/AFault 4422623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 4432623SN/A{ 4442623SN/A return write(*(uint32_t*)&data, addr, flags, res); 4452623SN/A} 4462623SN/A 4472623SN/A 4482623SN/Atemplate<> 4492623SN/AFault 4502623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 4512623SN/A{ 4522623SN/A return write((uint32_t)data, addr, flags, res); 4532623SN/A} 4542623SN/A 4552623SN/A 4562623SN/Avoid 4572623SN/ATimingSimpleCPU::fetch() 4582623SN/A{ 4593387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 4603387Sgblack@eecs.umich.edu checkForInterrupts(); 4612631SN/A 4622663Sstever@eecs.umich.edu Request *ifetch_req = new Request(); 4633170Sstever@eecs.umich.edu ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0); 4642662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 4652623SN/A 4664022Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast); 4672623SN/A ifetch_pkt->dataStatic(&inst); 4682623SN/A 4692623SN/A if (fault == NoFault) { 4702630SN/A if (!icachePort.sendTiming(ifetch_pkt)) { 4712623SN/A // Need to wait for retry 4722623SN/A _status = IcacheRetry; 4732623SN/A } else { 4742623SN/A // Need to wait for cache to respond 4752623SN/A _status = IcacheWaitResponse; 4762623SN/A // ownership of packet transferred to memory system 4772623SN/A ifetch_pkt = NULL; 4782623SN/A } 4792623SN/A } else { 4803658Sktlim@umich.edu delete ifetch_req; 4813658Sktlim@umich.edu delete ifetch_pkt; 4822644Sstever@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 4832644Sstever@eecs.umich.edu advanceInst(fault); 4842623SN/A } 4853222Sktlim@umich.edu 4863222Sktlim@umich.edu numCycles += curTick - previousTick; 4873222Sktlim@umich.edu previousTick = curTick; 4882623SN/A} 4892623SN/A 4902623SN/A 4912623SN/Avoid 4922644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 4932623SN/A{ 4942623SN/A advancePC(fault); 4952623SN/A 4962631SN/A if (_status == Running) { 4972631SN/A // kick off fetch of next instruction... callback from icache 4982631SN/A // response will cause that instruction to be executed, 4992631SN/A // keeping the CPU running. 5002631SN/A fetch(); 5012631SN/A } 5022623SN/A} 5032623SN/A 5042623SN/A 5052623SN/Avoid 5063349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 5072623SN/A{ 5082623SN/A // received a response from the icache: execute the received 5092623SN/A // instruction 5104870Sstever@eecs.umich.edu assert(!pkt->isError()); 5112623SN/A assert(_status == IcacheWaitResponse); 5122798Sktlim@umich.edu 5132623SN/A _status = Running; 5142644Sstever@eecs.umich.edu 5153222Sktlim@umich.edu numCycles += curTick - previousTick; 5163222Sktlim@umich.edu previousTick = curTick; 5173222Sktlim@umich.edu 5182839Sktlim@umich.edu if (getState() == SimObject::Draining) { 5193658Sktlim@umich.edu delete pkt->req; 5203658Sktlim@umich.edu delete pkt; 5213658Sktlim@umich.edu 5222839Sktlim@umich.edu completeDrain(); 5232798Sktlim@umich.edu return; 5242798Sktlim@umich.edu } 5252798Sktlim@umich.edu 5262623SN/A preExecute(); 5272644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 5282623SN/A // load or store: just send to dcache 5292623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 5303170Sstever@eecs.umich.edu if (_status != Running) { 5313170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 5323170Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DcacheRetry); 5333170Sstever@eecs.umich.edu assert(fault == NoFault); 5342644Sstever@eecs.umich.edu } else { 5353170Sstever@eecs.umich.edu if (fault == NoFault) { 5363170Sstever@eecs.umich.edu // early fail on store conditional: complete now 5373170Sstever@eecs.umich.edu assert(dcache_pkt != NULL); 5383170Sstever@eecs.umich.edu fault = curStaticInst->completeAcc(dcache_pkt, this, 5393170Sstever@eecs.umich.edu traceData); 5403170Sstever@eecs.umich.edu delete dcache_pkt->req; 5413170Sstever@eecs.umich.edu delete dcache_pkt; 5423170Sstever@eecs.umich.edu dcache_pkt = NULL; 5434998Sgblack@eecs.umich.edu 5444998Sgblack@eecs.umich.edu // keep an instruction count 5454998Sgblack@eecs.umich.edu if (fault == NoFault) 5464998Sgblack@eecs.umich.edu countInst(); 5475001Sgblack@eecs.umich.edu } else if (traceData) { 5485001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 5495001Sgblack@eecs.umich.edu delete traceData; 5505001Sgblack@eecs.umich.edu traceData = NULL; 5513170Sstever@eecs.umich.edu } 5524998Sgblack@eecs.umich.edu 5532644Sstever@eecs.umich.edu postExecute(); 5542644Sstever@eecs.umich.edu advanceInst(fault); 5552644Sstever@eecs.umich.edu } 5562623SN/A } else { 5572623SN/A // non-memory instruction: execute completely now 5582623SN/A Fault fault = curStaticInst->execute(this, traceData); 5594998Sgblack@eecs.umich.edu 5604998Sgblack@eecs.umich.edu // keep an instruction count 5614998Sgblack@eecs.umich.edu if (fault == NoFault) 5624998Sgblack@eecs.umich.edu countInst(); 5635001Sgblack@eecs.umich.edu else if (traceData) { 5645001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 5655001Sgblack@eecs.umich.edu delete traceData; 5665001Sgblack@eecs.umich.edu traceData = NULL; 5675001Sgblack@eecs.umich.edu } 5684998Sgblack@eecs.umich.edu 5692644Sstever@eecs.umich.edu postExecute(); 5702644Sstever@eecs.umich.edu advanceInst(fault); 5712623SN/A } 5723658Sktlim@umich.edu 5733658Sktlim@umich.edu delete pkt->req; 5743658Sktlim@umich.edu delete pkt; 5752623SN/A} 5762623SN/A 5772948Ssaidi@eecs.umich.eduvoid 5782948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 5792948Ssaidi@eecs.umich.edu{ 5802948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 5812948Ssaidi@eecs.umich.edu} 5822623SN/A 5832623SN/Abool 5843349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 5852623SN/A{ 5863310Srdreslin@umich.edu if (pkt->isResponse()) { 5873310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 5884584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 5892948Ssaidi@eecs.umich.edu 5903495Sktlim@umich.edu if (next_tick == curTick) 5913310Srdreslin@umich.edu cpu->completeIfetch(pkt); 5923310Srdreslin@umich.edu else 5933495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 5942948Ssaidi@eecs.umich.edu 5953310Srdreslin@umich.edu return true; 5963310Srdreslin@umich.edu } 5974870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 5984433Ssaidi@eecs.umich.edu assert(cpu->_status == IcacheWaitResponse); 5994433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 6004433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 6014433Ssaidi@eecs.umich.edu cpu->_status = IcacheRetry; 6024433Ssaidi@eecs.umich.edu cpu->ifetch_pkt = pkt; 6034433Ssaidi@eecs.umich.edu } 6043310Srdreslin@umich.edu } 6054433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 6064433Ssaidi@eecs.umich.edu return true; 6072623SN/A} 6082623SN/A 6092657Ssaidi@eecs.umich.eduvoid 6102623SN/ATimingSimpleCPU::IcachePort::recvRetry() 6112623SN/A{ 6122623SN/A // we shouldn't get a retry unless we have a packet that we're 6132623SN/A // waiting to transmit 6142623SN/A assert(cpu->ifetch_pkt != NULL); 6152623SN/A assert(cpu->_status == IcacheRetry); 6163349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 6172657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 6182657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 6192657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 6202657Ssaidi@eecs.umich.edu } 6212623SN/A} 6222623SN/A 6232623SN/Avoid 6243349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 6252623SN/A{ 6262623SN/A // received a response from the dcache: complete the load or store 6272623SN/A // instruction 6284870Sstever@eecs.umich.edu assert(!pkt->isError()); 6292623SN/A assert(_status == DcacheWaitResponse); 6302623SN/A _status = Running; 6312623SN/A 6323222Sktlim@umich.edu numCycles += curTick - previousTick; 6333222Sktlim@umich.edu previousTick = curTick; 6343184Srdreslin@umich.edu 6352623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 6362623SN/A 6374998Sgblack@eecs.umich.edu // keep an instruction count 6384998Sgblack@eecs.umich.edu if (fault == NoFault) 6394998Sgblack@eecs.umich.edu countInst(); 6405001Sgblack@eecs.umich.edu else if (traceData) { 6415001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6425001Sgblack@eecs.umich.edu delete traceData; 6435001Sgblack@eecs.umich.edu traceData = NULL; 6445001Sgblack@eecs.umich.edu } 6454998Sgblack@eecs.umich.edu 6464878Sstever@eecs.umich.edu if (pkt->isRead() && pkt->isLocked()) { 6473170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 6483170Sstever@eecs.umich.edu } 6493170Sstever@eecs.umich.edu 6502644Sstever@eecs.umich.edu delete pkt->req; 6512644Sstever@eecs.umich.edu delete pkt; 6522644Sstever@eecs.umich.edu 6533184Srdreslin@umich.edu postExecute(); 6543227Sktlim@umich.edu 6553201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 6563201Shsul@eecs.umich.edu advancePC(fault); 6573201Shsul@eecs.umich.edu completeDrain(); 6583201Shsul@eecs.umich.edu 6593201Shsul@eecs.umich.edu return; 6603201Shsul@eecs.umich.edu } 6613201Shsul@eecs.umich.edu 6622644Sstever@eecs.umich.edu advanceInst(fault); 6632623SN/A} 6642623SN/A 6652623SN/A 6662798Sktlim@umich.eduvoid 6672839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 6682798Sktlim@umich.edu{ 6692839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 6702901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 6712839Sktlim@umich.edu drainEvent->process(); 6722798Sktlim@umich.edu} 6732623SN/A 6744192Sktlim@umich.eduvoid 6754192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 6764192Sktlim@umich.edu{ 6774192Sktlim@umich.edu Port::setPeer(port); 6784192Sktlim@umich.edu 6794192Sktlim@umich.edu#if FULL_SYSTEM 6804192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 6814192Sktlim@umich.edu // Ports) 6824192Sktlim@umich.edu cpu->tcBase()->connectMemPorts(); 6834192Sktlim@umich.edu#endif 6844192Sktlim@umich.edu} 6854192Sktlim@umich.edu 6862623SN/Abool 6873349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 6882623SN/A{ 6893310Srdreslin@umich.edu if (pkt->isResponse()) { 6903310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 6914584Ssaidi@eecs.umich.edu Tick next_tick = cpu->nextCycle(curTick); 6922948Ssaidi@eecs.umich.edu 6933495Sktlim@umich.edu if (next_tick == curTick) 6943310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 6953310Srdreslin@umich.edu else 6963495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 6972948Ssaidi@eecs.umich.edu 6983310Srdreslin@umich.edu return true; 6993310Srdreslin@umich.edu } 7004870Sstever@eecs.umich.edu else if (pkt->wasNacked()) { 7014433Ssaidi@eecs.umich.edu assert(cpu->_status == DcacheWaitResponse); 7024433Ssaidi@eecs.umich.edu pkt->reinitNacked(); 7034433Ssaidi@eecs.umich.edu if (!sendTiming(pkt)) { 7044433Ssaidi@eecs.umich.edu cpu->_status = DcacheRetry; 7054433Ssaidi@eecs.umich.edu cpu->dcache_pkt = pkt; 7064433Ssaidi@eecs.umich.edu } 7073310Srdreslin@umich.edu } 7084433Ssaidi@eecs.umich.edu //Snooping a Coherence Request, do nothing 7094433Ssaidi@eecs.umich.edu return true; 7102948Ssaidi@eecs.umich.edu} 7112948Ssaidi@eecs.umich.edu 7122948Ssaidi@eecs.umich.eduvoid 7132948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 7142948Ssaidi@eecs.umich.edu{ 7152630SN/A cpu->completeDataAccess(pkt); 7162623SN/A} 7172623SN/A 7182657Ssaidi@eecs.umich.eduvoid 7192623SN/ATimingSimpleCPU::DcachePort::recvRetry() 7202623SN/A{ 7212623SN/A // we shouldn't get a retry unless we have a packet that we're 7222623SN/A // waiting to transmit 7232623SN/A assert(cpu->dcache_pkt != NULL); 7242623SN/A assert(cpu->_status == DcacheRetry); 7253349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 7262657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 7272657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 7283170Sstever@eecs.umich.edu // memory system takes ownership of packet 7292657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 7302657Ssaidi@eecs.umich.edu } 7312623SN/A} 7322623SN/A 7332623SN/A 7342623SN/A//////////////////////////////////////////////////////////////////////// 7352623SN/A// 7362623SN/A// TimingSimpleCPU Simulation Object 7372623SN/A// 7384762Snate@binkert.orgTimingSimpleCPU * 7394762Snate@binkert.orgTimingSimpleCPUParams::create() 7402623SN/A{ 7412623SN/A TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 7424762Snate@binkert.org params->name = name; 7432623SN/A params->numberOfThreads = 1; 7442623SN/A params->max_insts_any_thread = max_insts_any_thread; 7452623SN/A params->max_insts_all_threads = max_insts_all_threads; 7462623SN/A params->max_loads_any_thread = max_loads_any_thread; 7472623SN/A params->max_loads_all_threads = max_loads_all_threads; 7483119Sktlim@umich.edu params->progress_interval = progress_interval; 7492623SN/A params->deferRegistration = defer_registration; 7502623SN/A params->clock = clock; 7513661Srdreslin@umich.edu params->phase = phase; 7522623SN/A params->functionTrace = function_trace; 7532623SN/A params->functionTraceStart = function_trace_start; 7542901Ssaidi@eecs.umich.edu params->system = system; 7553170Sstever@eecs.umich.edu params->cpu_id = cpu_id; 7564776Sgblack@eecs.umich.edu params->tracer = tracer; 7572623SN/A 7582623SN/A params->itb = itb; 7592623SN/A params->dtb = dtb; 7604997Sgblack@eecs.umich.edu#if FULL_SYSTEM 7612623SN/A params->profile = profile; 7623617Sbinkertn@umich.edu params->do_quiesce = do_quiesce; 7633617Sbinkertn@umich.edu params->do_checkpoint_insts = do_checkpoint_insts; 7643617Sbinkertn@umich.edu params->do_statistics_insts = do_statistics_insts; 7652623SN/A#else 7664762Snate@binkert.org if (workload.size() != 1) 7674762Snate@binkert.org panic("only one workload allowed"); 7684762Snate@binkert.org params->process = workload[0]; 7692623SN/A#endif 7702623SN/A 7712623SN/A TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 7722623SN/A return cpu; 7732623SN/A} 774