timing.cc revision 4192
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 322623SN/A#include "arch/utility.hh" 334040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 342623SN/A#include "cpu/exetrace.hh" 352623SN/A#include "cpu/simple/timing.hh" 363348Sbinkertn@umich.edu#include "mem/packet.hh" 373348Sbinkertn@umich.edu#include "mem/packet_access.hh" 382623SN/A#include "sim/builder.hh" 392901Ssaidi@eecs.umich.edu#include "sim/system.hh" 402623SN/A 412623SN/Ausing namespace std; 422623SN/Ausing namespace TheISA; 432623SN/A 442856Srdreslin@umich.eduPort * 452856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 462856Srdreslin@umich.edu{ 472856Srdreslin@umich.edu if (if_name == "dcache_port") 482856Srdreslin@umich.edu return &dcachePort; 492856Srdreslin@umich.edu else if (if_name == "icache_port") 502856Srdreslin@umich.edu return &icachePort; 512856Srdreslin@umich.edu else 522856Srdreslin@umich.edu panic("No Such Port\n"); 532856Srdreslin@umich.edu} 542623SN/A 552623SN/Avoid 562623SN/ATimingSimpleCPU::init() 572623SN/A{ 582623SN/A BaseCPU::init(); 592623SN/A#if FULL_SYSTEM 602680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 612680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 622623SN/A 632623SN/A // initialize CPU, including PC 642680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 652623SN/A } 662623SN/A#endif 672623SN/A} 682623SN/A 692623SN/ATick 703349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 712623SN/A{ 722623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 732623SN/A return curTick; 742623SN/A} 752623SN/A 762623SN/Avoid 773349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 782623SN/A{ 793184Srdreslin@umich.edu //No internal storage to update, jusst return 803184Srdreslin@umich.edu return; 812623SN/A} 822623SN/A 832623SN/Avoid 842623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 852623SN/A{ 863647Srdreslin@umich.edu if (status == RangeChange) { 873647Srdreslin@umich.edu if (!snoopRangeSent) { 883647Srdreslin@umich.edu snoopRangeSent = true; 893647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 903647Srdreslin@umich.edu } 912631SN/A return; 923647Srdreslin@umich.edu } 932631SN/A 942623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 952623SN/A} 962623SN/A 972948Ssaidi@eecs.umich.edu 982948Ssaidi@eecs.umich.eduvoid 993349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1002948Ssaidi@eecs.umich.edu{ 1012948Ssaidi@eecs.umich.edu pkt = _pkt; 1022948Ssaidi@eecs.umich.edu Event::schedule(t); 1032948Ssaidi@eecs.umich.edu} 1042948Ssaidi@eecs.umich.edu 1052623SN/ATimingSimpleCPU::TimingSimpleCPU(Params *p) 1063170Sstever@eecs.umich.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), 1073170Sstever@eecs.umich.edu cpu_id(p->cpu_id) 1082623SN/A{ 1092623SN/A _status = Idle; 1103647Srdreslin@umich.edu 1113647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1123647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1133647Srdreslin@umich.edu 1142623SN/A ifetch_pkt = dcache_pkt = NULL; 1152839Sktlim@umich.edu drainEvent = NULL; 1162867Sktlim@umich.edu fetchEvent = NULL; 1173222Sktlim@umich.edu previousTick = 0; 1182901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1192623SN/A} 1202623SN/A 1212623SN/A 1222623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1232623SN/A{ 1242623SN/A} 1252623SN/A 1262623SN/Avoid 1272623SN/ATimingSimpleCPU::serialize(ostream &os) 1282623SN/A{ 1292915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1302915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1312623SN/A BaseSimpleCPU::serialize(os); 1322623SN/A} 1332623SN/A 1342623SN/Avoid 1352623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1362623SN/A{ 1372915Sktlim@umich.edu SimObject::State so_state; 1382915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1392623SN/A BaseSimpleCPU::unserialize(cp, section); 1402798Sktlim@umich.edu} 1412798Sktlim@umich.edu 1422901Ssaidi@eecs.umich.eduunsigned int 1432839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1442798Sktlim@umich.edu{ 1452839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1462798Sktlim@umich.edu // an access to complete. 1472798Sktlim@umich.edu if (status() == Idle || status() == Running || status() == SwitchedOut) { 1482901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1492901Ssaidi@eecs.umich.edu return 0; 1502798Sktlim@umich.edu } else { 1512839Sktlim@umich.edu changeState(SimObject::Draining); 1522839Sktlim@umich.edu drainEvent = drain_event; 1532901Ssaidi@eecs.umich.edu return 1; 1542798Sktlim@umich.edu } 1552623SN/A} 1562623SN/A 1572623SN/Avoid 1582798Sktlim@umich.eduTimingSimpleCPU::resume() 1592623SN/A{ 1602798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1613201Shsul@eecs.umich.edu assert(system->getMemoryMode() == System::Timing); 1623201Shsul@eecs.umich.edu 1632867Sktlim@umich.edu // Delete the old event if it existed. 1642867Sktlim@umich.edu if (fetchEvent) { 1652915Sktlim@umich.edu if (fetchEvent->scheduled()) 1662915Sktlim@umich.edu fetchEvent->deschedule(); 1672915Sktlim@umich.edu 1682867Sktlim@umich.edu delete fetchEvent; 1692867Sktlim@umich.edu } 1702867Sktlim@umich.edu 1712867Sktlim@umich.edu fetchEvent = 1722867Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 1733661Srdreslin@umich.edu fetchEvent->schedule(nextCycle()); 1742623SN/A } 1752798Sktlim@umich.edu 1762901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1773222Sktlim@umich.edu previousTick = curTick; 1782798Sktlim@umich.edu} 1792798Sktlim@umich.edu 1802798Sktlim@umich.eduvoid 1812798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1822798Sktlim@umich.edu{ 1832798Sktlim@umich.edu assert(status() == Running || status() == Idle); 1842798Sktlim@umich.edu _status = SwitchedOut; 1853222Sktlim@umich.edu numCycles += curTick - previousTick; 1862867Sktlim@umich.edu 1872867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1882867Sktlim@umich.edu // we'll need to cancel it. 1892867Sktlim@umich.edu if (fetchEvent && fetchEvent->scheduled()) 1902867Sktlim@umich.edu fetchEvent->deschedule(); 1912623SN/A} 1922623SN/A 1932623SN/A 1942623SN/Avoid 1952623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1962623SN/A{ 1974192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 1982623SN/A 1992680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 2002623SN/A // running and schedule its tick event. 2012680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2022680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2032680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2042623SN/A _status = Running; 2052623SN/A break; 2062623SN/A } 2072623SN/A } 2083201Shsul@eecs.umich.edu 2093201Shsul@eecs.umich.edu if (_status != Running) { 2103201Shsul@eecs.umich.edu _status = Idle; 2113201Shsul@eecs.umich.edu } 2122623SN/A} 2132623SN/A 2142623SN/A 2152623SN/Avoid 2162623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2172623SN/A{ 2182623SN/A assert(thread_num == 0); 2192683Sktlim@umich.edu assert(thread); 2202623SN/A 2212623SN/A assert(_status == Idle); 2222623SN/A 2232623SN/A notIdleFraction++; 2242623SN/A _status = Running; 2253686Sktlim@umich.edu 2262623SN/A // kick things off by initiating the fetch of the next instruction 2272867Sktlim@umich.edu fetchEvent = 2282867Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 2293661Srdreslin@umich.edu fetchEvent->schedule(nextCycle(curTick + cycles(delay))); 2302623SN/A} 2312623SN/A 2322623SN/A 2332623SN/Avoid 2342623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2352623SN/A{ 2362623SN/A assert(thread_num == 0); 2372683Sktlim@umich.edu assert(thread); 2382623SN/A 2392644Sstever@eecs.umich.edu assert(_status == Running); 2402623SN/A 2412644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2422644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2432623SN/A 2442623SN/A notIdleFraction--; 2452623SN/A _status = Idle; 2462623SN/A} 2472623SN/A 2482623SN/A 2492623SN/Atemplate <class T> 2502623SN/AFault 2512623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2522623SN/A{ 2533169Sstever@eecs.umich.edu Request *req = 2543169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 2553170Sstever@eecs.umich.edu cpu_id, /* thread ID */ 0); 2562623SN/A 2572623SN/A if (traceData) { 2583169Sstever@eecs.umich.edu traceData->setAddr(req->getVaddr()); 2592623SN/A } 2602623SN/A 2612623SN/A // translate to physical address 2623169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2632623SN/A 2642623SN/A // Now do the access. 2652623SN/A if (fault == NoFault) { 2663349Sbinkertn@umich.edu PacketPtr pkt = 2674022Sstever@eecs.umich.edu new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 2683169Sstever@eecs.umich.edu pkt->dataDynamic<T>(new T); 2692623SN/A 2703169Sstever@eecs.umich.edu if (!dcachePort.sendTiming(pkt)) { 2712623SN/A _status = DcacheRetry; 2723169Sstever@eecs.umich.edu dcache_pkt = pkt; 2732623SN/A } else { 2742623SN/A _status = DcacheWaitResponse; 2753169Sstever@eecs.umich.edu // memory system takes ownership of packet 2762623SN/A dcache_pkt = NULL; 2772623SN/A } 2783658Sktlim@umich.edu } else { 2793658Sktlim@umich.edu delete req; 2802623SN/A } 2812623SN/A 2822623SN/A // This will need a new way to tell if it has a dcache attached. 2833172Sstever@eecs.umich.edu if (req->isUncacheable()) 2842623SN/A recordEvent("Uncached Read"); 2852623SN/A 2862623SN/A return fault; 2872623SN/A} 2882623SN/A 2892623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 2902623SN/A 2912623SN/Atemplate 2922623SN/AFault 2934040Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 2944040Ssaidi@eecs.umich.edu 2954040Ssaidi@eecs.umich.edutemplate 2964040Ssaidi@eecs.umich.eduFault 2974115Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 2984115Ssaidi@eecs.umich.edu 2994115Ssaidi@eecs.umich.edutemplate 3004115Ssaidi@eecs.umich.eduFault 3012623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 3022623SN/A 3032623SN/Atemplate 3042623SN/AFault 3052623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3062623SN/A 3072623SN/Atemplate 3082623SN/AFault 3092623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 3102623SN/A 3112623SN/Atemplate 3122623SN/AFault 3132623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3142623SN/A 3152623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3162623SN/A 3172623SN/Atemplate<> 3182623SN/AFault 3192623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 3202623SN/A{ 3212623SN/A return read(addr, *(uint64_t*)&data, flags); 3222623SN/A} 3232623SN/A 3242623SN/Atemplate<> 3252623SN/AFault 3262623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 3272623SN/A{ 3282623SN/A return read(addr, *(uint32_t*)&data, flags); 3292623SN/A} 3302623SN/A 3312623SN/A 3322623SN/Atemplate<> 3332623SN/AFault 3342623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3352623SN/A{ 3362623SN/A return read(addr, (uint32_t&)data, flags); 3372623SN/A} 3382623SN/A 3392623SN/A 3402623SN/Atemplate <class T> 3412623SN/AFault 3422623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3432623SN/A{ 3443169Sstever@eecs.umich.edu Request *req = 3453169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 3463170Sstever@eecs.umich.edu cpu_id, /* thread ID */ 0); 3472623SN/A 3484040Ssaidi@eecs.umich.edu if (traceData) { 3494040Ssaidi@eecs.umich.edu traceData->setAddr(req->getVaddr()); 3504040Ssaidi@eecs.umich.edu } 3514040Ssaidi@eecs.umich.edu 3522623SN/A // translate to physical address 3533169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3543169Sstever@eecs.umich.edu 3552623SN/A // Now do the access. 3562623SN/A if (fault == NoFault) { 3573169Sstever@eecs.umich.edu assert(dcache_pkt == NULL); 3584040Ssaidi@eecs.umich.edu if (req->isSwap()) 3594040Ssaidi@eecs.umich.edu dcache_pkt = new Packet(req, MemCmd::SwapReq, Packet::Broadcast); 3604040Ssaidi@eecs.umich.edu else 3614040Ssaidi@eecs.umich.edu dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast); 3623169Sstever@eecs.umich.edu dcache_pkt->allocate(); 3633169Sstever@eecs.umich.edu dcache_pkt->set(data); 3642623SN/A 3653170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3663170Sstever@eecs.umich.edu 3673170Sstever@eecs.umich.edu if (req->isLocked()) { 3683170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3693170Sstever@eecs.umich.edu } 3704040Ssaidi@eecs.umich.edu if (req->isCondSwap()) { 3714040Ssaidi@eecs.umich.edu assert(res); 3724040Ssaidi@eecs.umich.edu req->setExtraData(*res); 3734040Ssaidi@eecs.umich.edu } 3743170Sstever@eecs.umich.edu 3753170Sstever@eecs.umich.edu if (do_access) { 3763170Sstever@eecs.umich.edu if (!dcachePort.sendTiming(dcache_pkt)) { 3773170Sstever@eecs.umich.edu _status = DcacheRetry; 3783170Sstever@eecs.umich.edu } else { 3793170Sstever@eecs.umich.edu _status = DcacheWaitResponse; 3803170Sstever@eecs.umich.edu // memory system takes ownership of packet 3813170Sstever@eecs.umich.edu dcache_pkt = NULL; 3823170Sstever@eecs.umich.edu } 3832623SN/A } 3843658Sktlim@umich.edu } else { 3853658Sktlim@umich.edu delete req; 3862623SN/A } 3872623SN/A 3882623SN/A // This will need a new way to tell if it's hooked up to a cache or not. 3893172Sstever@eecs.umich.edu if (req->isUncacheable()) 3902623SN/A recordEvent("Uncached Write"); 3912623SN/A 3922623SN/A // If the write needs to have a fault on the access, consider calling 3932623SN/A // changeStatus() and changing it to "bad addr write" or something. 3942623SN/A return fault; 3952623SN/A} 3962623SN/A 3972623SN/A 3982623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3992623SN/Atemplate 4002623SN/AFault 4012623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 4022623SN/A unsigned flags, uint64_t *res); 4032623SN/A 4042623SN/Atemplate 4052623SN/AFault 4062623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 4072623SN/A unsigned flags, uint64_t *res); 4082623SN/A 4092623SN/Atemplate 4102623SN/AFault 4112623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 4122623SN/A unsigned flags, uint64_t *res); 4132623SN/A 4142623SN/Atemplate 4152623SN/AFault 4162623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 4172623SN/A unsigned flags, uint64_t *res); 4182623SN/A 4192623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4202623SN/A 4212623SN/Atemplate<> 4222623SN/AFault 4232623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 4242623SN/A{ 4252623SN/A return write(*(uint64_t*)&data, addr, flags, res); 4262623SN/A} 4272623SN/A 4282623SN/Atemplate<> 4292623SN/AFault 4302623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 4312623SN/A{ 4322623SN/A return write(*(uint32_t*)&data, addr, flags, res); 4332623SN/A} 4342623SN/A 4352623SN/A 4362623SN/Atemplate<> 4372623SN/AFault 4382623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 4392623SN/A{ 4402623SN/A return write((uint32_t)data, addr, flags, res); 4412623SN/A} 4422623SN/A 4432623SN/A 4442623SN/Avoid 4452623SN/ATimingSimpleCPU::fetch() 4462623SN/A{ 4473387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 4483387Sgblack@eecs.umich.edu checkForInterrupts(); 4492631SN/A 4502663Sstever@eecs.umich.edu Request *ifetch_req = new Request(); 4513170Sstever@eecs.umich.edu ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0); 4522662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 4532623SN/A 4544022Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast); 4552623SN/A ifetch_pkt->dataStatic(&inst); 4562623SN/A 4572623SN/A if (fault == NoFault) { 4582630SN/A if (!icachePort.sendTiming(ifetch_pkt)) { 4592623SN/A // Need to wait for retry 4602623SN/A _status = IcacheRetry; 4612623SN/A } else { 4622623SN/A // Need to wait for cache to respond 4632623SN/A _status = IcacheWaitResponse; 4642623SN/A // ownership of packet transferred to memory system 4652623SN/A ifetch_pkt = NULL; 4662623SN/A } 4672623SN/A } else { 4683658Sktlim@umich.edu delete ifetch_req; 4693658Sktlim@umich.edu delete ifetch_pkt; 4702644Sstever@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 4712644Sstever@eecs.umich.edu advanceInst(fault); 4722623SN/A } 4733222Sktlim@umich.edu 4743222Sktlim@umich.edu numCycles += curTick - previousTick; 4753222Sktlim@umich.edu previousTick = curTick; 4762623SN/A} 4772623SN/A 4782623SN/A 4792623SN/Avoid 4802644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 4812623SN/A{ 4822623SN/A advancePC(fault); 4832623SN/A 4842631SN/A if (_status == Running) { 4852631SN/A // kick off fetch of next instruction... callback from icache 4862631SN/A // response will cause that instruction to be executed, 4872631SN/A // keeping the CPU running. 4882631SN/A fetch(); 4892631SN/A } 4902623SN/A} 4912623SN/A 4922623SN/A 4932623SN/Avoid 4943349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 4952623SN/A{ 4962623SN/A // received a response from the icache: execute the received 4972623SN/A // instruction 4982644Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 4992623SN/A assert(_status == IcacheWaitResponse); 5002798Sktlim@umich.edu 5012623SN/A _status = Running; 5022644Sstever@eecs.umich.edu 5033222Sktlim@umich.edu numCycles += curTick - previousTick; 5043222Sktlim@umich.edu previousTick = curTick; 5053222Sktlim@umich.edu 5062839Sktlim@umich.edu if (getState() == SimObject::Draining) { 5073658Sktlim@umich.edu delete pkt->req; 5083658Sktlim@umich.edu delete pkt; 5093658Sktlim@umich.edu 5102839Sktlim@umich.edu completeDrain(); 5112798Sktlim@umich.edu return; 5122798Sktlim@umich.edu } 5132798Sktlim@umich.edu 5142623SN/A preExecute(); 5152644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 5162623SN/A // load or store: just send to dcache 5172623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 5183170Sstever@eecs.umich.edu if (_status != Running) { 5193170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 5203170Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DcacheRetry); 5213170Sstever@eecs.umich.edu assert(fault == NoFault); 5222644Sstever@eecs.umich.edu } else { 5233170Sstever@eecs.umich.edu if (fault == NoFault) { 5243170Sstever@eecs.umich.edu // early fail on store conditional: complete now 5253170Sstever@eecs.umich.edu assert(dcache_pkt != NULL); 5263170Sstever@eecs.umich.edu fault = curStaticInst->completeAcc(dcache_pkt, this, 5273170Sstever@eecs.umich.edu traceData); 5283170Sstever@eecs.umich.edu delete dcache_pkt->req; 5293170Sstever@eecs.umich.edu delete dcache_pkt; 5303170Sstever@eecs.umich.edu dcache_pkt = NULL; 5313170Sstever@eecs.umich.edu } 5322644Sstever@eecs.umich.edu postExecute(); 5332644Sstever@eecs.umich.edu advanceInst(fault); 5342644Sstever@eecs.umich.edu } 5352623SN/A } else { 5362623SN/A // non-memory instruction: execute completely now 5372623SN/A Fault fault = curStaticInst->execute(this, traceData); 5382644Sstever@eecs.umich.edu postExecute(); 5392644Sstever@eecs.umich.edu advanceInst(fault); 5402623SN/A } 5413658Sktlim@umich.edu 5423658Sktlim@umich.edu delete pkt->req; 5433658Sktlim@umich.edu delete pkt; 5442623SN/A} 5452623SN/A 5462948Ssaidi@eecs.umich.eduvoid 5472948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 5482948Ssaidi@eecs.umich.edu{ 5492948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 5502948Ssaidi@eecs.umich.edu} 5512623SN/A 5522623SN/Abool 5533349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 5542623SN/A{ 5553310Srdreslin@umich.edu if (pkt->isResponse()) { 5563310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 5573495Sktlim@umich.edu Tick mem_time = pkt->req->getTime(); 5583495Sktlim@umich.edu Tick next_tick = cpu->nextCycle(mem_time); 5592948Ssaidi@eecs.umich.edu 5603495Sktlim@umich.edu if (next_tick == curTick) 5613310Srdreslin@umich.edu cpu->completeIfetch(pkt); 5623310Srdreslin@umich.edu else 5633495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 5642948Ssaidi@eecs.umich.edu 5653310Srdreslin@umich.edu return true; 5663310Srdreslin@umich.edu } 5673310Srdreslin@umich.edu else { 5683310Srdreslin@umich.edu //Snooping a Coherence Request, do nothing 5693310Srdreslin@umich.edu return true; 5703310Srdreslin@umich.edu } 5712623SN/A} 5722623SN/A 5732657Ssaidi@eecs.umich.eduvoid 5742623SN/ATimingSimpleCPU::IcachePort::recvRetry() 5752623SN/A{ 5762623SN/A // we shouldn't get a retry unless we have a packet that we're 5772623SN/A // waiting to transmit 5782623SN/A assert(cpu->ifetch_pkt != NULL); 5792623SN/A assert(cpu->_status == IcacheRetry); 5803349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 5812657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 5822657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 5832657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 5842657Ssaidi@eecs.umich.edu } 5852623SN/A} 5862623SN/A 5872623SN/Avoid 5883349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 5892623SN/A{ 5902623SN/A // received a response from the dcache: complete the load or store 5912623SN/A // instruction 5922641Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 5932623SN/A assert(_status == DcacheWaitResponse); 5942623SN/A _status = Running; 5952623SN/A 5963222Sktlim@umich.edu numCycles += curTick - previousTick; 5973222Sktlim@umich.edu previousTick = curTick; 5983184Srdreslin@umich.edu 5992623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 6002623SN/A 6013170Sstever@eecs.umich.edu if (pkt->isRead() && pkt->req->isLocked()) { 6023170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 6033170Sstever@eecs.umich.edu } 6043170Sstever@eecs.umich.edu 6052644Sstever@eecs.umich.edu delete pkt->req; 6062644Sstever@eecs.umich.edu delete pkt; 6072644Sstever@eecs.umich.edu 6083184Srdreslin@umich.edu postExecute(); 6093227Sktlim@umich.edu 6103201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 6113201Shsul@eecs.umich.edu advancePC(fault); 6123201Shsul@eecs.umich.edu completeDrain(); 6133201Shsul@eecs.umich.edu 6143201Shsul@eecs.umich.edu return; 6153201Shsul@eecs.umich.edu } 6163201Shsul@eecs.umich.edu 6172644Sstever@eecs.umich.edu advanceInst(fault); 6182623SN/A} 6192623SN/A 6202623SN/A 6212798Sktlim@umich.eduvoid 6222839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 6232798Sktlim@umich.edu{ 6242839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 6252901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 6262839Sktlim@umich.edu drainEvent->process(); 6272798Sktlim@umich.edu} 6282623SN/A 6294192Sktlim@umich.eduvoid 6304192Sktlim@umich.eduTimingSimpleCPU::DcachePort::setPeer(Port *port) 6314192Sktlim@umich.edu{ 6324192Sktlim@umich.edu Port::setPeer(port); 6334192Sktlim@umich.edu 6344192Sktlim@umich.edu#if FULL_SYSTEM 6354192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 6364192Sktlim@umich.edu // Ports) 6374192Sktlim@umich.edu cpu->tcBase()->connectMemPorts(); 6384192Sktlim@umich.edu#endif 6394192Sktlim@umich.edu} 6404192Sktlim@umich.edu 6412623SN/Abool 6423349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 6432623SN/A{ 6443310Srdreslin@umich.edu if (pkt->isResponse()) { 6453310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 6463495Sktlim@umich.edu Tick mem_time = pkt->req->getTime(); 6473495Sktlim@umich.edu Tick next_tick = cpu->nextCycle(mem_time); 6482948Ssaidi@eecs.umich.edu 6493495Sktlim@umich.edu if (next_tick == curTick) 6503310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 6513310Srdreslin@umich.edu else 6523495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 6532948Ssaidi@eecs.umich.edu 6543310Srdreslin@umich.edu return true; 6553310Srdreslin@umich.edu } 6563310Srdreslin@umich.edu else { 6573310Srdreslin@umich.edu //Snooping a coherence req, do nothing 6583310Srdreslin@umich.edu return true; 6593310Srdreslin@umich.edu } 6602948Ssaidi@eecs.umich.edu} 6612948Ssaidi@eecs.umich.edu 6622948Ssaidi@eecs.umich.eduvoid 6632948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 6642948Ssaidi@eecs.umich.edu{ 6652630SN/A cpu->completeDataAccess(pkt); 6662623SN/A} 6672623SN/A 6682657Ssaidi@eecs.umich.eduvoid 6692623SN/ATimingSimpleCPU::DcachePort::recvRetry() 6702623SN/A{ 6712623SN/A // we shouldn't get a retry unless we have a packet that we're 6722623SN/A // waiting to transmit 6732623SN/A assert(cpu->dcache_pkt != NULL); 6742623SN/A assert(cpu->_status == DcacheRetry); 6753349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 6762657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 6772657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 6783170Sstever@eecs.umich.edu // memory system takes ownership of packet 6792657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 6802657Ssaidi@eecs.umich.edu } 6812623SN/A} 6822623SN/A 6832623SN/A 6842623SN/A//////////////////////////////////////////////////////////////////////// 6852623SN/A// 6862623SN/A// TimingSimpleCPU Simulation Object 6872623SN/A// 6882623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6892623SN/A 6902623SN/A Param<Counter> max_insts_any_thread; 6912623SN/A Param<Counter> max_insts_all_threads; 6922623SN/A Param<Counter> max_loads_any_thread; 6932623SN/A Param<Counter> max_loads_all_threads; 6943119Sktlim@umich.edu Param<Tick> progress_interval; 6952901Ssaidi@eecs.umich.edu SimObjectParam<System *> system; 6963170Sstever@eecs.umich.edu Param<int> cpu_id; 6972623SN/A 6982623SN/A#if FULL_SYSTEM 6993453Sgblack@eecs.umich.edu SimObjectParam<TheISA::ITB *> itb; 7003453Sgblack@eecs.umich.edu SimObjectParam<TheISA::DTB *> dtb; 7012623SN/A Param<Tick> profile; 7023617Sbinkertn@umich.edu 7033617Sbinkertn@umich.edu Param<bool> do_quiesce; 7043617Sbinkertn@umich.edu Param<bool> do_checkpoint_insts; 7053617Sbinkertn@umich.edu Param<bool> do_statistics_insts; 7062623SN/A#else 7072623SN/A SimObjectParam<Process *> workload; 7082623SN/A#endif // FULL_SYSTEM 7092623SN/A 7102623SN/A Param<int> clock; 7113661Srdreslin@umich.edu Param<int> phase; 7122623SN/A 7132623SN/A Param<bool> defer_registration; 7142623SN/A Param<int> width; 7152623SN/A Param<bool> function_trace; 7162623SN/A Param<Tick> function_trace_start; 7172623SN/A Param<bool> simulate_stalls; 7182623SN/A 7192623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 7202623SN/A 7212623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 7222623SN/A 7232623SN/A INIT_PARAM(max_insts_any_thread, 7242623SN/A "terminate when any thread reaches this inst count"), 7252623SN/A INIT_PARAM(max_insts_all_threads, 7262623SN/A "terminate when all threads have reached this inst count"), 7272623SN/A INIT_PARAM(max_loads_any_thread, 7282623SN/A "terminate when any thread reaches this load count"), 7292623SN/A INIT_PARAM(max_loads_all_threads, 7302623SN/A "terminate when all threads have reached this load count"), 7313119Sktlim@umich.edu INIT_PARAM(progress_interval, "Progress interval"), 7322901Ssaidi@eecs.umich.edu INIT_PARAM(system, "system object"), 7333170Sstever@eecs.umich.edu INIT_PARAM(cpu_id, "processor ID"), 7342623SN/A 7352623SN/A#if FULL_SYSTEM 7362623SN/A INIT_PARAM(itb, "Instruction TLB"), 7372623SN/A INIT_PARAM(dtb, "Data TLB"), 7382623SN/A INIT_PARAM(profile, ""), 7393617Sbinkertn@umich.edu INIT_PARAM(do_quiesce, ""), 7403617Sbinkertn@umich.edu INIT_PARAM(do_checkpoint_insts, ""), 7413617Sbinkertn@umich.edu INIT_PARAM(do_statistics_insts, ""), 7422623SN/A#else 7432623SN/A INIT_PARAM(workload, "processes to run"), 7442623SN/A#endif // FULL_SYSTEM 7452623SN/A 7462623SN/A INIT_PARAM(clock, "clock speed"), 7473661Srdreslin@umich.edu INIT_PARAM_DFLT(phase, "clock phase", 0), 7482623SN/A INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 7492623SN/A INIT_PARAM(width, "cpu width"), 7502623SN/A INIT_PARAM(function_trace, "Enable function trace"), 7512623SN/A INIT_PARAM(function_trace_start, "Cycle to start function trace"), 7522623SN/A INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 7532623SN/A 7542623SN/AEND_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 7552623SN/A 7562623SN/A 7572623SN/ACREATE_SIM_OBJECT(TimingSimpleCPU) 7582623SN/A{ 7592623SN/A TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 7602623SN/A params->name = getInstanceName(); 7612623SN/A params->numberOfThreads = 1; 7622623SN/A params->max_insts_any_thread = max_insts_any_thread; 7632623SN/A params->max_insts_all_threads = max_insts_all_threads; 7642623SN/A params->max_loads_any_thread = max_loads_any_thread; 7652623SN/A params->max_loads_all_threads = max_loads_all_threads; 7663119Sktlim@umich.edu params->progress_interval = progress_interval; 7672623SN/A params->deferRegistration = defer_registration; 7682623SN/A params->clock = clock; 7693661Srdreslin@umich.edu params->phase = phase; 7702623SN/A params->functionTrace = function_trace; 7712623SN/A params->functionTraceStart = function_trace_start; 7722901Ssaidi@eecs.umich.edu params->system = system; 7733170Sstever@eecs.umich.edu params->cpu_id = cpu_id; 7742623SN/A 7752623SN/A#if FULL_SYSTEM 7762623SN/A params->itb = itb; 7772623SN/A params->dtb = dtb; 7782623SN/A params->profile = profile; 7793617Sbinkertn@umich.edu params->do_quiesce = do_quiesce; 7803617Sbinkertn@umich.edu params->do_checkpoint_insts = do_checkpoint_insts; 7813617Sbinkertn@umich.edu params->do_statistics_insts = do_statistics_insts; 7822623SN/A#else 7832623SN/A params->process = workload; 7842623SN/A#endif 7852623SN/A 7862623SN/A TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 7872623SN/A return cpu; 7882623SN/A} 7892623SN/A 7902623SN/AREGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 7912623SN/A 792