timing.cc revision 4040
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 322623SN/A#include "arch/utility.hh" 334040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 342623SN/A#include "cpu/exetrace.hh" 352623SN/A#include "cpu/simple/timing.hh" 363348Sbinkertn@umich.edu#include "mem/packet.hh" 373348Sbinkertn@umich.edu#include "mem/packet_access.hh" 382623SN/A#include "sim/builder.hh" 392901Ssaidi@eecs.umich.edu#include "sim/system.hh" 402623SN/A 412623SN/Ausing namespace std; 422623SN/Ausing namespace TheISA; 432623SN/A 442856Srdreslin@umich.eduPort * 452856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 462856Srdreslin@umich.edu{ 472856Srdreslin@umich.edu if (if_name == "dcache_port") 482856Srdreslin@umich.edu return &dcachePort; 492856Srdreslin@umich.edu else if (if_name == "icache_port") 502856Srdreslin@umich.edu return &icachePort; 512856Srdreslin@umich.edu else 522856Srdreslin@umich.edu panic("No Such Port\n"); 532856Srdreslin@umich.edu} 542623SN/A 552623SN/Avoid 562623SN/ATimingSimpleCPU::init() 572623SN/A{ 582623SN/A BaseCPU::init(); 592623SN/A#if FULL_SYSTEM 602680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 612680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 622623SN/A 632623SN/A // initialize CPU, including PC 642680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 652623SN/A } 662623SN/A#endif 672623SN/A} 682623SN/A 692623SN/ATick 703349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 712623SN/A{ 722623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 732623SN/A return curTick; 742623SN/A} 752623SN/A 762623SN/Avoid 773349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 782623SN/A{ 793184Srdreslin@umich.edu //No internal storage to update, jusst return 803184Srdreslin@umich.edu return; 812623SN/A} 822623SN/A 832623SN/Avoid 842623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 852623SN/A{ 863647Srdreslin@umich.edu if (status == RangeChange) { 873647Srdreslin@umich.edu if (!snoopRangeSent) { 883647Srdreslin@umich.edu snoopRangeSent = true; 893647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 903647Srdreslin@umich.edu } 912631SN/A return; 923647Srdreslin@umich.edu } 932631SN/A 942623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 952623SN/A} 962623SN/A 972948Ssaidi@eecs.umich.edu 982948Ssaidi@eecs.umich.eduvoid 993349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 1002948Ssaidi@eecs.umich.edu{ 1012948Ssaidi@eecs.umich.edu pkt = _pkt; 1022948Ssaidi@eecs.umich.edu Event::schedule(t); 1032948Ssaidi@eecs.umich.edu} 1042948Ssaidi@eecs.umich.edu 1052623SN/ATimingSimpleCPU::TimingSimpleCPU(Params *p) 1063170Sstever@eecs.umich.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), 1073170Sstever@eecs.umich.edu cpu_id(p->cpu_id) 1082623SN/A{ 1092623SN/A _status = Idle; 1103647Srdreslin@umich.edu 1113647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1123647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1133647Srdreslin@umich.edu 1142623SN/A ifetch_pkt = dcache_pkt = NULL; 1152839Sktlim@umich.edu drainEvent = NULL; 1162867Sktlim@umich.edu fetchEvent = NULL; 1173222Sktlim@umich.edu previousTick = 0; 1182901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1192623SN/A} 1202623SN/A 1212623SN/A 1222623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1232623SN/A{ 1242623SN/A} 1252623SN/A 1262623SN/Avoid 1272623SN/ATimingSimpleCPU::serialize(ostream &os) 1282623SN/A{ 1292915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1302915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1312623SN/A BaseSimpleCPU::serialize(os); 1322623SN/A} 1332623SN/A 1342623SN/Avoid 1352623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1362623SN/A{ 1372915Sktlim@umich.edu SimObject::State so_state; 1382915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1392623SN/A BaseSimpleCPU::unserialize(cp, section); 1402798Sktlim@umich.edu} 1412798Sktlim@umich.edu 1422901Ssaidi@eecs.umich.eduunsigned int 1432839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1442798Sktlim@umich.edu{ 1452839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1462798Sktlim@umich.edu // an access to complete. 1472798Sktlim@umich.edu if (status() == Idle || status() == Running || status() == SwitchedOut) { 1482901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1492901Ssaidi@eecs.umich.edu return 0; 1502798Sktlim@umich.edu } else { 1512839Sktlim@umich.edu changeState(SimObject::Draining); 1522839Sktlim@umich.edu drainEvent = drain_event; 1532901Ssaidi@eecs.umich.edu return 1; 1542798Sktlim@umich.edu } 1552623SN/A} 1562623SN/A 1572623SN/Avoid 1582798Sktlim@umich.eduTimingSimpleCPU::resume() 1592623SN/A{ 1602798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1613201Shsul@eecs.umich.edu assert(system->getMemoryMode() == System::Timing); 1623201Shsul@eecs.umich.edu 1632867Sktlim@umich.edu // Delete the old event if it existed. 1642867Sktlim@umich.edu if (fetchEvent) { 1652915Sktlim@umich.edu if (fetchEvent->scheduled()) 1662915Sktlim@umich.edu fetchEvent->deschedule(); 1672915Sktlim@umich.edu 1682867Sktlim@umich.edu delete fetchEvent; 1692867Sktlim@umich.edu } 1702867Sktlim@umich.edu 1712867Sktlim@umich.edu fetchEvent = 1722867Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 1733661Srdreslin@umich.edu fetchEvent->schedule(nextCycle()); 1742623SN/A } 1752798Sktlim@umich.edu 1762901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1773222Sktlim@umich.edu previousTick = curTick; 1782798Sktlim@umich.edu} 1792798Sktlim@umich.edu 1802798Sktlim@umich.eduvoid 1812798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1822798Sktlim@umich.edu{ 1832798Sktlim@umich.edu assert(status() == Running || status() == Idle); 1842798Sktlim@umich.edu _status = SwitchedOut; 1853222Sktlim@umich.edu numCycles += curTick - previousTick; 1862867Sktlim@umich.edu 1872867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1882867Sktlim@umich.edu // we'll need to cancel it. 1892867Sktlim@umich.edu if (fetchEvent && fetchEvent->scheduled()) 1902867Sktlim@umich.edu fetchEvent->deschedule(); 1912623SN/A} 1922623SN/A 1932623SN/A 1942623SN/Avoid 1952623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1962623SN/A{ 1972623SN/A BaseCPU::takeOverFrom(oldCPU); 1982623SN/A 1992680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 2002623SN/A // running and schedule its tick event. 2012680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2022680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2032680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2042623SN/A _status = Running; 2052623SN/A break; 2062623SN/A } 2072623SN/A } 2083201Shsul@eecs.umich.edu 2093201Shsul@eecs.umich.edu if (_status != Running) { 2103201Shsul@eecs.umich.edu _status = Idle; 2113201Shsul@eecs.umich.edu } 2123227Sktlim@umich.edu 2133222Sktlim@umich.edu Port *peer; 2143222Sktlim@umich.edu if (icachePort.getPeer() == NULL) { 2153227Sktlim@umich.edu peer = oldCPU->getPort("icache_port")->getPeer(); 2163222Sktlim@umich.edu icachePort.setPeer(peer); 2173222Sktlim@umich.edu } else { 2183222Sktlim@umich.edu peer = icachePort.getPeer(); 2193222Sktlim@umich.edu } 2203222Sktlim@umich.edu peer->setPeer(&icachePort); 2213222Sktlim@umich.edu 2223222Sktlim@umich.edu if (dcachePort.getPeer() == NULL) { 2233227Sktlim@umich.edu peer = oldCPU->getPort("dcache_port")->getPeer(); 2243222Sktlim@umich.edu dcachePort.setPeer(peer); 2253222Sktlim@umich.edu } else { 2263222Sktlim@umich.edu peer = dcachePort.getPeer(); 2273222Sktlim@umich.edu } 2283222Sktlim@umich.edu peer->setPeer(&dcachePort); 2292623SN/A} 2302623SN/A 2312623SN/A 2322623SN/Avoid 2332623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2342623SN/A{ 2352623SN/A assert(thread_num == 0); 2362683Sktlim@umich.edu assert(thread); 2372623SN/A 2382623SN/A assert(_status == Idle); 2392623SN/A 2402623SN/A notIdleFraction++; 2412623SN/A _status = Running; 2423686Sktlim@umich.edu 2433686Sktlim@umich.edu#if FULL_SYSTEM 2443686Sktlim@umich.edu // Connect the ThreadContext's memory ports (Functional/Virtual 2453686Sktlim@umich.edu // Ports) 2463686Sktlim@umich.edu tc->connectMemPorts(); 2473686Sktlim@umich.edu#endif 2483686Sktlim@umich.edu 2492623SN/A // kick things off by initiating the fetch of the next instruction 2502867Sktlim@umich.edu fetchEvent = 2512867Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 2523661Srdreslin@umich.edu fetchEvent->schedule(nextCycle(curTick + cycles(delay))); 2532623SN/A} 2542623SN/A 2552623SN/A 2562623SN/Avoid 2572623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2582623SN/A{ 2592623SN/A assert(thread_num == 0); 2602683Sktlim@umich.edu assert(thread); 2612623SN/A 2622644Sstever@eecs.umich.edu assert(_status == Running); 2632623SN/A 2642644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2652644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2662623SN/A 2672623SN/A notIdleFraction--; 2682623SN/A _status = Idle; 2692623SN/A} 2702623SN/A 2712623SN/A 2722623SN/Atemplate <class T> 2732623SN/AFault 2742623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2752623SN/A{ 2763169Sstever@eecs.umich.edu Request *req = 2773169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 2783170Sstever@eecs.umich.edu cpu_id, /* thread ID */ 0); 2792623SN/A 2802623SN/A if (traceData) { 2813169Sstever@eecs.umich.edu traceData->setAddr(req->getVaddr()); 2822623SN/A } 2832623SN/A 2842623SN/A // translate to physical address 2853169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2862623SN/A 2872623SN/A // Now do the access. 2882623SN/A if (fault == NoFault) { 2893349Sbinkertn@umich.edu PacketPtr pkt = 2904022Sstever@eecs.umich.edu new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 2913169Sstever@eecs.umich.edu pkt->dataDynamic<T>(new T); 2922623SN/A 2933169Sstever@eecs.umich.edu if (!dcachePort.sendTiming(pkt)) { 2942623SN/A _status = DcacheRetry; 2953169Sstever@eecs.umich.edu dcache_pkt = pkt; 2962623SN/A } else { 2972623SN/A _status = DcacheWaitResponse; 2983169Sstever@eecs.umich.edu // memory system takes ownership of packet 2992623SN/A dcache_pkt = NULL; 3002623SN/A } 3013658Sktlim@umich.edu } else { 3023658Sktlim@umich.edu delete req; 3032623SN/A } 3042623SN/A 3052623SN/A // This will need a new way to tell if it has a dcache attached. 3063172Sstever@eecs.umich.edu if (req->isUncacheable()) 3072623SN/A recordEvent("Uncached Read"); 3082623SN/A 3092623SN/A return fault; 3102623SN/A} 3112623SN/A 3122623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3132623SN/A 3142623SN/Atemplate 3152623SN/AFault 3164040Ssaidi@eecs.umich.eduTimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 3174040Ssaidi@eecs.umich.edu 3184040Ssaidi@eecs.umich.edutemplate 3194040Ssaidi@eecs.umich.eduFault 3202623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 3212623SN/A 3222623SN/Atemplate 3232623SN/AFault 3242623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3252623SN/A 3262623SN/Atemplate 3272623SN/AFault 3282623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 3292623SN/A 3302623SN/Atemplate 3312623SN/AFault 3322623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3332623SN/A 3342623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3352623SN/A 3362623SN/Atemplate<> 3372623SN/AFault 3382623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 3392623SN/A{ 3402623SN/A return read(addr, *(uint64_t*)&data, flags); 3412623SN/A} 3422623SN/A 3432623SN/Atemplate<> 3442623SN/AFault 3452623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 3462623SN/A{ 3472623SN/A return read(addr, *(uint32_t*)&data, flags); 3482623SN/A} 3492623SN/A 3502623SN/A 3512623SN/Atemplate<> 3522623SN/AFault 3532623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3542623SN/A{ 3552623SN/A return read(addr, (uint32_t&)data, flags); 3562623SN/A} 3572623SN/A 3582623SN/A 3592623SN/Atemplate <class T> 3602623SN/AFault 3612623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3622623SN/A{ 3633169Sstever@eecs.umich.edu Request *req = 3643169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 3653170Sstever@eecs.umich.edu cpu_id, /* thread ID */ 0); 3662623SN/A 3674040Ssaidi@eecs.umich.edu if (traceData) { 3684040Ssaidi@eecs.umich.edu traceData->setAddr(req->getVaddr()); 3694040Ssaidi@eecs.umich.edu } 3704040Ssaidi@eecs.umich.edu 3712623SN/A // translate to physical address 3723169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3733169Sstever@eecs.umich.edu 3742623SN/A // Now do the access. 3752623SN/A if (fault == NoFault) { 3763169Sstever@eecs.umich.edu assert(dcache_pkt == NULL); 3774040Ssaidi@eecs.umich.edu if (req->isSwap()) 3784040Ssaidi@eecs.umich.edu dcache_pkt = new Packet(req, MemCmd::SwapReq, Packet::Broadcast); 3794040Ssaidi@eecs.umich.edu else 3804040Ssaidi@eecs.umich.edu dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast); 3813169Sstever@eecs.umich.edu dcache_pkt->allocate(); 3823169Sstever@eecs.umich.edu dcache_pkt->set(data); 3832623SN/A 3843170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3853170Sstever@eecs.umich.edu 3863170Sstever@eecs.umich.edu if (req->isLocked()) { 3873170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3883170Sstever@eecs.umich.edu } 3894040Ssaidi@eecs.umich.edu if (req->isCondSwap()) { 3904040Ssaidi@eecs.umich.edu assert(res); 3914040Ssaidi@eecs.umich.edu req->setExtraData(*res); 3924040Ssaidi@eecs.umich.edu } 3933170Sstever@eecs.umich.edu 3943170Sstever@eecs.umich.edu if (do_access) { 3953170Sstever@eecs.umich.edu if (!dcachePort.sendTiming(dcache_pkt)) { 3963170Sstever@eecs.umich.edu _status = DcacheRetry; 3973170Sstever@eecs.umich.edu } else { 3983170Sstever@eecs.umich.edu _status = DcacheWaitResponse; 3993170Sstever@eecs.umich.edu // memory system takes ownership of packet 4003170Sstever@eecs.umich.edu dcache_pkt = NULL; 4013170Sstever@eecs.umich.edu } 4022623SN/A } 4033658Sktlim@umich.edu } else { 4043658Sktlim@umich.edu delete req; 4052623SN/A } 4062623SN/A 4072623SN/A // This will need a new way to tell if it's hooked up to a cache or not. 4083172Sstever@eecs.umich.edu if (req->isUncacheable()) 4092623SN/A recordEvent("Uncached Write"); 4102623SN/A 4112623SN/A // If the write needs to have a fault on the access, consider calling 4122623SN/A // changeStatus() and changing it to "bad addr write" or something. 4132623SN/A return fault; 4142623SN/A} 4152623SN/A 4162623SN/A 4172623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4182623SN/Atemplate 4192623SN/AFault 4202623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 4212623SN/A unsigned flags, uint64_t *res); 4222623SN/A 4232623SN/Atemplate 4242623SN/AFault 4252623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 4262623SN/A unsigned flags, uint64_t *res); 4272623SN/A 4282623SN/Atemplate 4292623SN/AFault 4302623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 4312623SN/A unsigned flags, uint64_t *res); 4322623SN/A 4332623SN/Atemplate 4342623SN/AFault 4352623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 4362623SN/A unsigned flags, uint64_t *res); 4372623SN/A 4382623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4392623SN/A 4402623SN/Atemplate<> 4412623SN/AFault 4422623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 4432623SN/A{ 4442623SN/A return write(*(uint64_t*)&data, addr, flags, res); 4452623SN/A} 4462623SN/A 4472623SN/Atemplate<> 4482623SN/AFault 4492623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 4502623SN/A{ 4512623SN/A return write(*(uint32_t*)&data, addr, flags, res); 4522623SN/A} 4532623SN/A 4542623SN/A 4552623SN/Atemplate<> 4562623SN/AFault 4572623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 4582623SN/A{ 4592623SN/A return write((uint32_t)data, addr, flags, res); 4602623SN/A} 4612623SN/A 4622623SN/A 4632623SN/Avoid 4642623SN/ATimingSimpleCPU::fetch() 4652623SN/A{ 4663387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 4673387Sgblack@eecs.umich.edu checkForInterrupts(); 4682631SN/A 4692663Sstever@eecs.umich.edu Request *ifetch_req = new Request(); 4703170Sstever@eecs.umich.edu ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0); 4712662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 4722623SN/A 4734022Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast); 4742623SN/A ifetch_pkt->dataStatic(&inst); 4752623SN/A 4762623SN/A if (fault == NoFault) { 4772630SN/A if (!icachePort.sendTiming(ifetch_pkt)) { 4782623SN/A // Need to wait for retry 4792623SN/A _status = IcacheRetry; 4802623SN/A } else { 4812623SN/A // Need to wait for cache to respond 4822623SN/A _status = IcacheWaitResponse; 4832623SN/A // ownership of packet transferred to memory system 4842623SN/A ifetch_pkt = NULL; 4852623SN/A } 4862623SN/A } else { 4873658Sktlim@umich.edu delete ifetch_req; 4883658Sktlim@umich.edu delete ifetch_pkt; 4892644Sstever@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 4902644Sstever@eecs.umich.edu advanceInst(fault); 4912623SN/A } 4923222Sktlim@umich.edu 4933222Sktlim@umich.edu numCycles += curTick - previousTick; 4943222Sktlim@umich.edu previousTick = curTick; 4952623SN/A} 4962623SN/A 4972623SN/A 4982623SN/Avoid 4992644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 5002623SN/A{ 5012623SN/A advancePC(fault); 5022623SN/A 5032631SN/A if (_status == Running) { 5042631SN/A // kick off fetch of next instruction... callback from icache 5052631SN/A // response will cause that instruction to be executed, 5062631SN/A // keeping the CPU running. 5072631SN/A fetch(); 5082631SN/A } 5092623SN/A} 5102623SN/A 5112623SN/A 5122623SN/Avoid 5133349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 5142623SN/A{ 5152623SN/A // received a response from the icache: execute the received 5162623SN/A // instruction 5172644Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 5182623SN/A assert(_status == IcacheWaitResponse); 5192798Sktlim@umich.edu 5202623SN/A _status = Running; 5212644Sstever@eecs.umich.edu 5223222Sktlim@umich.edu numCycles += curTick - previousTick; 5233222Sktlim@umich.edu previousTick = curTick; 5243222Sktlim@umich.edu 5252839Sktlim@umich.edu if (getState() == SimObject::Draining) { 5263658Sktlim@umich.edu delete pkt->req; 5273658Sktlim@umich.edu delete pkt; 5283658Sktlim@umich.edu 5292839Sktlim@umich.edu completeDrain(); 5302798Sktlim@umich.edu return; 5312798Sktlim@umich.edu } 5322798Sktlim@umich.edu 5332623SN/A preExecute(); 5342644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 5352623SN/A // load or store: just send to dcache 5362623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 5373170Sstever@eecs.umich.edu if (_status != Running) { 5383170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 5393170Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DcacheRetry); 5403170Sstever@eecs.umich.edu assert(fault == NoFault); 5412644Sstever@eecs.umich.edu } else { 5423170Sstever@eecs.umich.edu if (fault == NoFault) { 5433170Sstever@eecs.umich.edu // early fail on store conditional: complete now 5443170Sstever@eecs.umich.edu assert(dcache_pkt != NULL); 5453170Sstever@eecs.umich.edu fault = curStaticInst->completeAcc(dcache_pkt, this, 5463170Sstever@eecs.umich.edu traceData); 5473170Sstever@eecs.umich.edu delete dcache_pkt->req; 5483170Sstever@eecs.umich.edu delete dcache_pkt; 5493170Sstever@eecs.umich.edu dcache_pkt = NULL; 5503170Sstever@eecs.umich.edu } 5512644Sstever@eecs.umich.edu postExecute(); 5522644Sstever@eecs.umich.edu advanceInst(fault); 5532644Sstever@eecs.umich.edu } 5542623SN/A } else { 5552623SN/A // non-memory instruction: execute completely now 5562623SN/A Fault fault = curStaticInst->execute(this, traceData); 5572644Sstever@eecs.umich.edu postExecute(); 5582644Sstever@eecs.umich.edu advanceInst(fault); 5592623SN/A } 5603658Sktlim@umich.edu 5613658Sktlim@umich.edu delete pkt->req; 5623658Sktlim@umich.edu delete pkt; 5632623SN/A} 5642623SN/A 5652948Ssaidi@eecs.umich.eduvoid 5662948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 5672948Ssaidi@eecs.umich.edu{ 5682948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 5692948Ssaidi@eecs.umich.edu} 5702623SN/A 5712623SN/Abool 5723349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 5732623SN/A{ 5743310Srdreslin@umich.edu if (pkt->isResponse()) { 5753310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 5763495Sktlim@umich.edu Tick mem_time = pkt->req->getTime(); 5773495Sktlim@umich.edu Tick next_tick = cpu->nextCycle(mem_time); 5782948Ssaidi@eecs.umich.edu 5793495Sktlim@umich.edu if (next_tick == curTick) 5803310Srdreslin@umich.edu cpu->completeIfetch(pkt); 5813310Srdreslin@umich.edu else 5823495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 5832948Ssaidi@eecs.umich.edu 5843310Srdreslin@umich.edu return true; 5853310Srdreslin@umich.edu } 5863310Srdreslin@umich.edu else { 5873310Srdreslin@umich.edu //Snooping a Coherence Request, do nothing 5883310Srdreslin@umich.edu return true; 5893310Srdreslin@umich.edu } 5902623SN/A} 5912623SN/A 5922657Ssaidi@eecs.umich.eduvoid 5932623SN/ATimingSimpleCPU::IcachePort::recvRetry() 5942623SN/A{ 5952623SN/A // we shouldn't get a retry unless we have a packet that we're 5962623SN/A // waiting to transmit 5972623SN/A assert(cpu->ifetch_pkt != NULL); 5982623SN/A assert(cpu->_status == IcacheRetry); 5993349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 6002657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 6012657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 6022657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 6032657Ssaidi@eecs.umich.edu } 6042623SN/A} 6052623SN/A 6062623SN/Avoid 6073349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 6082623SN/A{ 6092623SN/A // received a response from the dcache: complete the load or store 6102623SN/A // instruction 6112641Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 6122623SN/A assert(_status == DcacheWaitResponse); 6132623SN/A _status = Running; 6142623SN/A 6153222Sktlim@umich.edu numCycles += curTick - previousTick; 6163222Sktlim@umich.edu previousTick = curTick; 6173184Srdreslin@umich.edu 6182623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 6192623SN/A 6203170Sstever@eecs.umich.edu if (pkt->isRead() && pkt->req->isLocked()) { 6213170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 6223170Sstever@eecs.umich.edu } 6233170Sstever@eecs.umich.edu 6242644Sstever@eecs.umich.edu delete pkt->req; 6252644Sstever@eecs.umich.edu delete pkt; 6262644Sstever@eecs.umich.edu 6273184Srdreslin@umich.edu postExecute(); 6283227Sktlim@umich.edu 6293201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 6303201Shsul@eecs.umich.edu advancePC(fault); 6313201Shsul@eecs.umich.edu completeDrain(); 6323201Shsul@eecs.umich.edu 6333201Shsul@eecs.umich.edu return; 6343201Shsul@eecs.umich.edu } 6353201Shsul@eecs.umich.edu 6362644Sstever@eecs.umich.edu advanceInst(fault); 6372623SN/A} 6382623SN/A 6392623SN/A 6402798Sktlim@umich.eduvoid 6412839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 6422798Sktlim@umich.edu{ 6432839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 6442901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 6452839Sktlim@umich.edu drainEvent->process(); 6462798Sktlim@umich.edu} 6472623SN/A 6482623SN/Abool 6493349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 6502623SN/A{ 6513310Srdreslin@umich.edu if (pkt->isResponse()) { 6523310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 6533495Sktlim@umich.edu Tick mem_time = pkt->req->getTime(); 6543495Sktlim@umich.edu Tick next_tick = cpu->nextCycle(mem_time); 6552948Ssaidi@eecs.umich.edu 6563495Sktlim@umich.edu if (next_tick == curTick) 6573310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 6583310Srdreslin@umich.edu else 6593495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 6602948Ssaidi@eecs.umich.edu 6613310Srdreslin@umich.edu return true; 6623310Srdreslin@umich.edu } 6633310Srdreslin@umich.edu else { 6643310Srdreslin@umich.edu //Snooping a coherence req, do nothing 6653310Srdreslin@umich.edu return true; 6663310Srdreslin@umich.edu } 6672948Ssaidi@eecs.umich.edu} 6682948Ssaidi@eecs.umich.edu 6692948Ssaidi@eecs.umich.eduvoid 6702948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 6712948Ssaidi@eecs.umich.edu{ 6722630SN/A cpu->completeDataAccess(pkt); 6732623SN/A} 6742623SN/A 6752657Ssaidi@eecs.umich.eduvoid 6762623SN/ATimingSimpleCPU::DcachePort::recvRetry() 6772623SN/A{ 6782623SN/A // we shouldn't get a retry unless we have a packet that we're 6792623SN/A // waiting to transmit 6802623SN/A assert(cpu->dcache_pkt != NULL); 6812623SN/A assert(cpu->_status == DcacheRetry); 6823349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 6832657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 6842657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 6853170Sstever@eecs.umich.edu // memory system takes ownership of packet 6862657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 6872657Ssaidi@eecs.umich.edu } 6882623SN/A} 6892623SN/A 6902623SN/A 6912623SN/A//////////////////////////////////////////////////////////////////////// 6922623SN/A// 6932623SN/A// TimingSimpleCPU Simulation Object 6942623SN/A// 6952623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6962623SN/A 6972623SN/A Param<Counter> max_insts_any_thread; 6982623SN/A Param<Counter> max_insts_all_threads; 6992623SN/A Param<Counter> max_loads_any_thread; 7002623SN/A Param<Counter> max_loads_all_threads; 7013119Sktlim@umich.edu Param<Tick> progress_interval; 7022901Ssaidi@eecs.umich.edu SimObjectParam<System *> system; 7033170Sstever@eecs.umich.edu Param<int> cpu_id; 7042623SN/A 7052623SN/A#if FULL_SYSTEM 7063453Sgblack@eecs.umich.edu SimObjectParam<TheISA::ITB *> itb; 7073453Sgblack@eecs.umich.edu SimObjectParam<TheISA::DTB *> dtb; 7082623SN/A Param<Tick> profile; 7093617Sbinkertn@umich.edu 7103617Sbinkertn@umich.edu Param<bool> do_quiesce; 7113617Sbinkertn@umich.edu Param<bool> do_checkpoint_insts; 7123617Sbinkertn@umich.edu Param<bool> do_statistics_insts; 7132623SN/A#else 7142623SN/A SimObjectParam<Process *> workload; 7152623SN/A#endif // FULL_SYSTEM 7162623SN/A 7172623SN/A Param<int> clock; 7183661Srdreslin@umich.edu Param<int> phase; 7192623SN/A 7202623SN/A Param<bool> defer_registration; 7212623SN/A Param<int> width; 7222623SN/A Param<bool> function_trace; 7232623SN/A Param<Tick> function_trace_start; 7242623SN/A Param<bool> simulate_stalls; 7252623SN/A 7262623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 7272623SN/A 7282623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 7292623SN/A 7302623SN/A INIT_PARAM(max_insts_any_thread, 7312623SN/A "terminate when any thread reaches this inst count"), 7322623SN/A INIT_PARAM(max_insts_all_threads, 7332623SN/A "terminate when all threads have reached this inst count"), 7342623SN/A INIT_PARAM(max_loads_any_thread, 7352623SN/A "terminate when any thread reaches this load count"), 7362623SN/A INIT_PARAM(max_loads_all_threads, 7372623SN/A "terminate when all threads have reached this load count"), 7383119Sktlim@umich.edu INIT_PARAM(progress_interval, "Progress interval"), 7392901Ssaidi@eecs.umich.edu INIT_PARAM(system, "system object"), 7403170Sstever@eecs.umich.edu INIT_PARAM(cpu_id, "processor ID"), 7412623SN/A 7422623SN/A#if FULL_SYSTEM 7432623SN/A INIT_PARAM(itb, "Instruction TLB"), 7442623SN/A INIT_PARAM(dtb, "Data TLB"), 7452623SN/A INIT_PARAM(profile, ""), 7463617Sbinkertn@umich.edu INIT_PARAM(do_quiesce, ""), 7473617Sbinkertn@umich.edu INIT_PARAM(do_checkpoint_insts, ""), 7483617Sbinkertn@umich.edu INIT_PARAM(do_statistics_insts, ""), 7492623SN/A#else 7502623SN/A INIT_PARAM(workload, "processes to run"), 7512623SN/A#endif // FULL_SYSTEM 7522623SN/A 7532623SN/A INIT_PARAM(clock, "clock speed"), 7543661Srdreslin@umich.edu INIT_PARAM_DFLT(phase, "clock phase", 0), 7552623SN/A INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 7562623SN/A INIT_PARAM(width, "cpu width"), 7572623SN/A INIT_PARAM(function_trace, "Enable function trace"), 7582623SN/A INIT_PARAM(function_trace_start, "Cycle to start function trace"), 7592623SN/A INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 7602623SN/A 7612623SN/AEND_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 7622623SN/A 7632623SN/A 7642623SN/ACREATE_SIM_OBJECT(TimingSimpleCPU) 7652623SN/A{ 7662623SN/A TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 7672623SN/A params->name = getInstanceName(); 7682623SN/A params->numberOfThreads = 1; 7692623SN/A params->max_insts_any_thread = max_insts_any_thread; 7702623SN/A params->max_insts_all_threads = max_insts_all_threads; 7712623SN/A params->max_loads_any_thread = max_loads_any_thread; 7722623SN/A params->max_loads_all_threads = max_loads_all_threads; 7733119Sktlim@umich.edu params->progress_interval = progress_interval; 7742623SN/A params->deferRegistration = defer_registration; 7752623SN/A params->clock = clock; 7763661Srdreslin@umich.edu params->phase = phase; 7772623SN/A params->functionTrace = function_trace; 7782623SN/A params->functionTraceStart = function_trace_start; 7792901Ssaidi@eecs.umich.edu params->system = system; 7803170Sstever@eecs.umich.edu params->cpu_id = cpu_id; 7812623SN/A 7822623SN/A#if FULL_SYSTEM 7832623SN/A params->itb = itb; 7842623SN/A params->dtb = dtb; 7852623SN/A params->profile = profile; 7863617Sbinkertn@umich.edu params->do_quiesce = do_quiesce; 7873617Sbinkertn@umich.edu params->do_checkpoint_insts = do_checkpoint_insts; 7883617Sbinkertn@umich.edu params->do_statistics_insts = do_statistics_insts; 7892623SN/A#else 7902623SN/A params->process = workload; 7912623SN/A#endif 7922623SN/A 7932623SN/A TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 7942623SN/A return cpu; 7952623SN/A} 7962623SN/A 7972623SN/AREGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 7982623SN/A 799