timing.cc revision 3647
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 322623SN/A#include "arch/utility.hh" 332623SN/A#include "cpu/exetrace.hh" 342623SN/A#include "cpu/simple/timing.hh" 353348Sbinkertn@umich.edu#include "mem/packet.hh" 363348Sbinkertn@umich.edu#include "mem/packet_access.hh" 372623SN/A#include "sim/builder.hh" 382901Ssaidi@eecs.umich.edu#include "sim/system.hh" 392623SN/A 402623SN/Ausing namespace std; 412623SN/Ausing namespace TheISA; 422623SN/A 432856Srdreslin@umich.eduPort * 442856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 452856Srdreslin@umich.edu{ 462856Srdreslin@umich.edu if (if_name == "dcache_port") 472856Srdreslin@umich.edu return &dcachePort; 482856Srdreslin@umich.edu else if (if_name == "icache_port") 492856Srdreslin@umich.edu return &icachePort; 502856Srdreslin@umich.edu else 512856Srdreslin@umich.edu panic("No Such Port\n"); 522856Srdreslin@umich.edu} 532623SN/A 542623SN/Avoid 552623SN/ATimingSimpleCPU::init() 562623SN/A{ 572623SN/A BaseCPU::init(); 582623SN/A#if FULL_SYSTEM 592680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 602680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 612623SN/A 622623SN/A // initialize CPU, including PC 632680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 642623SN/A } 652623SN/A#endif 662623SN/A} 672623SN/A 682623SN/ATick 693349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 702623SN/A{ 712623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 722623SN/A return curTick; 732623SN/A} 742623SN/A 752623SN/Avoid 763349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 772623SN/A{ 783184Srdreslin@umich.edu //No internal storage to update, jusst return 793184Srdreslin@umich.edu return; 802623SN/A} 812623SN/A 822623SN/Avoid 832623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 842623SN/A{ 853647Srdreslin@umich.edu if (status == RangeChange) { 863647Srdreslin@umich.edu if (!snoopRangeSent) { 873647Srdreslin@umich.edu snoopRangeSent = true; 883647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 893647Srdreslin@umich.edu } 902631SN/A return; 913647Srdreslin@umich.edu } 922631SN/A 932623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 942623SN/A} 952623SN/A 962948Ssaidi@eecs.umich.edu 972948Ssaidi@eecs.umich.eduvoid 983349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 992948Ssaidi@eecs.umich.edu{ 1002948Ssaidi@eecs.umich.edu pkt = _pkt; 1012948Ssaidi@eecs.umich.edu Event::schedule(t); 1022948Ssaidi@eecs.umich.edu} 1032948Ssaidi@eecs.umich.edu 1042623SN/ATimingSimpleCPU::TimingSimpleCPU(Params *p) 1053170Sstever@eecs.umich.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), 1063170Sstever@eecs.umich.edu cpu_id(p->cpu_id) 1072623SN/A{ 1082623SN/A _status = Idle; 1093647Srdreslin@umich.edu 1103647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1113647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1123647Srdreslin@umich.edu 1132623SN/A ifetch_pkt = dcache_pkt = NULL; 1142839Sktlim@umich.edu drainEvent = NULL; 1152867Sktlim@umich.edu fetchEvent = NULL; 1163222Sktlim@umich.edu previousTick = 0; 1172901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1182623SN/A} 1192623SN/A 1202623SN/A 1212623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1222623SN/A{ 1232623SN/A} 1242623SN/A 1252623SN/Avoid 1262623SN/ATimingSimpleCPU::serialize(ostream &os) 1272623SN/A{ 1282915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1292915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1302623SN/A BaseSimpleCPU::serialize(os); 1312623SN/A} 1322623SN/A 1332623SN/Avoid 1342623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1352623SN/A{ 1362915Sktlim@umich.edu SimObject::State so_state; 1372915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1382623SN/A BaseSimpleCPU::unserialize(cp, section); 1392798Sktlim@umich.edu} 1402798Sktlim@umich.edu 1412901Ssaidi@eecs.umich.eduunsigned int 1422839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1432798Sktlim@umich.edu{ 1442839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1452798Sktlim@umich.edu // an access to complete. 1462798Sktlim@umich.edu if (status() == Idle || status() == Running || status() == SwitchedOut) { 1472901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1482901Ssaidi@eecs.umich.edu return 0; 1492798Sktlim@umich.edu } else { 1502839Sktlim@umich.edu changeState(SimObject::Draining); 1512839Sktlim@umich.edu drainEvent = drain_event; 1522901Ssaidi@eecs.umich.edu return 1; 1532798Sktlim@umich.edu } 1542623SN/A} 1552623SN/A 1562623SN/Avoid 1572798Sktlim@umich.eduTimingSimpleCPU::resume() 1582623SN/A{ 1592798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1603201Shsul@eecs.umich.edu assert(system->getMemoryMode() == System::Timing); 1613201Shsul@eecs.umich.edu 1622867Sktlim@umich.edu // Delete the old event if it existed. 1632867Sktlim@umich.edu if (fetchEvent) { 1642915Sktlim@umich.edu if (fetchEvent->scheduled()) 1652915Sktlim@umich.edu fetchEvent->deschedule(); 1662915Sktlim@umich.edu 1672867Sktlim@umich.edu delete fetchEvent; 1682867Sktlim@umich.edu } 1692867Sktlim@umich.edu 1702867Sktlim@umich.edu fetchEvent = 1712867Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 1722867Sktlim@umich.edu fetchEvent->schedule(curTick); 1732623SN/A } 1742798Sktlim@umich.edu 1752901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1763222Sktlim@umich.edu previousTick = curTick; 1772798Sktlim@umich.edu} 1782798Sktlim@umich.edu 1792798Sktlim@umich.eduvoid 1802798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1812798Sktlim@umich.edu{ 1822798Sktlim@umich.edu assert(status() == Running || status() == Idle); 1832798Sktlim@umich.edu _status = SwitchedOut; 1843222Sktlim@umich.edu numCycles += curTick - previousTick; 1852867Sktlim@umich.edu 1862867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1872867Sktlim@umich.edu // we'll need to cancel it. 1882867Sktlim@umich.edu if (fetchEvent && fetchEvent->scheduled()) 1892867Sktlim@umich.edu fetchEvent->deschedule(); 1902623SN/A} 1912623SN/A 1922623SN/A 1932623SN/Avoid 1942623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1952623SN/A{ 1962623SN/A BaseCPU::takeOverFrom(oldCPU); 1972623SN/A 1982680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1992623SN/A // running and schedule its tick event. 2002680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2012680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2022680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2032623SN/A _status = Running; 2042623SN/A break; 2052623SN/A } 2062623SN/A } 2073201Shsul@eecs.umich.edu 2083201Shsul@eecs.umich.edu if (_status != Running) { 2093201Shsul@eecs.umich.edu _status = Idle; 2103201Shsul@eecs.umich.edu } 2113227Sktlim@umich.edu 2123222Sktlim@umich.edu Port *peer; 2133222Sktlim@umich.edu if (icachePort.getPeer() == NULL) { 2143227Sktlim@umich.edu peer = oldCPU->getPort("icache_port")->getPeer(); 2153222Sktlim@umich.edu icachePort.setPeer(peer); 2163222Sktlim@umich.edu } else { 2173222Sktlim@umich.edu peer = icachePort.getPeer(); 2183222Sktlim@umich.edu } 2193222Sktlim@umich.edu peer->setPeer(&icachePort); 2203222Sktlim@umich.edu 2213222Sktlim@umich.edu if (dcachePort.getPeer() == NULL) { 2223227Sktlim@umich.edu peer = oldCPU->getPort("dcache_port")->getPeer(); 2233222Sktlim@umich.edu dcachePort.setPeer(peer); 2243222Sktlim@umich.edu } else { 2253222Sktlim@umich.edu peer = dcachePort.getPeer(); 2263222Sktlim@umich.edu } 2273222Sktlim@umich.edu peer->setPeer(&dcachePort); 2282623SN/A} 2292623SN/A 2302623SN/A 2312623SN/Avoid 2322623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2332623SN/A{ 2342623SN/A assert(thread_num == 0); 2352683Sktlim@umich.edu assert(thread); 2362623SN/A 2372623SN/A assert(_status == Idle); 2382623SN/A 2392623SN/A notIdleFraction++; 2402623SN/A _status = Running; 2412623SN/A // kick things off by initiating the fetch of the next instruction 2422867Sktlim@umich.edu fetchEvent = 2432867Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 2442867Sktlim@umich.edu fetchEvent->schedule(curTick + cycles(delay)); 2452623SN/A} 2462623SN/A 2472623SN/A 2482623SN/Avoid 2492623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2502623SN/A{ 2512623SN/A assert(thread_num == 0); 2522683Sktlim@umich.edu assert(thread); 2532623SN/A 2542644Sstever@eecs.umich.edu assert(_status == Running); 2552623SN/A 2562644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2572644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2582623SN/A 2592623SN/A notIdleFraction--; 2602623SN/A _status = Idle; 2612623SN/A} 2622623SN/A 2632623SN/A 2642623SN/Atemplate <class T> 2652623SN/AFault 2662623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2672623SN/A{ 2683169Sstever@eecs.umich.edu Request *req = 2693169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 2703170Sstever@eecs.umich.edu cpu_id, /* thread ID */ 0); 2712623SN/A 2722623SN/A if (traceData) { 2733169Sstever@eecs.umich.edu traceData->setAddr(req->getVaddr()); 2742623SN/A } 2752623SN/A 2762623SN/A // translate to physical address 2773169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2782623SN/A 2792623SN/A // Now do the access. 2802623SN/A if (fault == NoFault) { 2813349Sbinkertn@umich.edu PacketPtr pkt = 2823169Sstever@eecs.umich.edu new Packet(req, Packet::ReadReq, Packet::Broadcast); 2833169Sstever@eecs.umich.edu pkt->dataDynamic<T>(new T); 2842623SN/A 2853169Sstever@eecs.umich.edu if (!dcachePort.sendTiming(pkt)) { 2862623SN/A _status = DcacheRetry; 2873169Sstever@eecs.umich.edu dcache_pkt = pkt; 2882623SN/A } else { 2892623SN/A _status = DcacheWaitResponse; 2903169Sstever@eecs.umich.edu // memory system takes ownership of packet 2912623SN/A dcache_pkt = NULL; 2922623SN/A } 2932623SN/A } 2942623SN/A 2952623SN/A // This will need a new way to tell if it has a dcache attached. 2963172Sstever@eecs.umich.edu if (req->isUncacheable()) 2972623SN/A recordEvent("Uncached Read"); 2982623SN/A 2992623SN/A return fault; 3002623SN/A} 3012623SN/A 3022623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3032623SN/A 3042623SN/Atemplate 3052623SN/AFault 3062623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 3072623SN/A 3082623SN/Atemplate 3092623SN/AFault 3102623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3112623SN/A 3122623SN/Atemplate 3132623SN/AFault 3142623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 3152623SN/A 3162623SN/Atemplate 3172623SN/AFault 3182623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3192623SN/A 3202623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3212623SN/A 3222623SN/Atemplate<> 3232623SN/AFault 3242623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 3252623SN/A{ 3262623SN/A return read(addr, *(uint64_t*)&data, flags); 3272623SN/A} 3282623SN/A 3292623SN/Atemplate<> 3302623SN/AFault 3312623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 3322623SN/A{ 3332623SN/A return read(addr, *(uint32_t*)&data, flags); 3342623SN/A} 3352623SN/A 3362623SN/A 3372623SN/Atemplate<> 3382623SN/AFault 3392623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3402623SN/A{ 3412623SN/A return read(addr, (uint32_t&)data, flags); 3422623SN/A} 3432623SN/A 3442623SN/A 3452623SN/Atemplate <class T> 3462623SN/AFault 3472623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3482623SN/A{ 3493169Sstever@eecs.umich.edu Request *req = 3503169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 3513170Sstever@eecs.umich.edu cpu_id, /* thread ID */ 0); 3522623SN/A 3532623SN/A // translate to physical address 3543169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3553169Sstever@eecs.umich.edu 3562623SN/A // Now do the access. 3572623SN/A if (fault == NoFault) { 3583169Sstever@eecs.umich.edu assert(dcache_pkt == NULL); 3593169Sstever@eecs.umich.edu dcache_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 3603169Sstever@eecs.umich.edu dcache_pkt->allocate(); 3613169Sstever@eecs.umich.edu dcache_pkt->set(data); 3622623SN/A 3633170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3643170Sstever@eecs.umich.edu 3653170Sstever@eecs.umich.edu if (req->isLocked()) { 3663170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3673170Sstever@eecs.umich.edu } 3683170Sstever@eecs.umich.edu 3693170Sstever@eecs.umich.edu if (do_access) { 3703170Sstever@eecs.umich.edu if (!dcachePort.sendTiming(dcache_pkt)) { 3713170Sstever@eecs.umich.edu _status = DcacheRetry; 3723170Sstever@eecs.umich.edu } else { 3733170Sstever@eecs.umich.edu _status = DcacheWaitResponse; 3743170Sstever@eecs.umich.edu // memory system takes ownership of packet 3753170Sstever@eecs.umich.edu dcache_pkt = NULL; 3763170Sstever@eecs.umich.edu } 3772623SN/A } 3782623SN/A } 3792623SN/A 3802623SN/A // This will need a new way to tell if it's hooked up to a cache or not. 3813172Sstever@eecs.umich.edu if (req->isUncacheable()) 3822623SN/A recordEvent("Uncached Write"); 3832623SN/A 3842623SN/A // If the write needs to have a fault on the access, consider calling 3852623SN/A // changeStatus() and changing it to "bad addr write" or something. 3862623SN/A return fault; 3872623SN/A} 3882623SN/A 3892623SN/A 3902623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3912623SN/Atemplate 3922623SN/AFault 3932623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 3942623SN/A unsigned flags, uint64_t *res); 3952623SN/A 3962623SN/Atemplate 3972623SN/AFault 3982623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 3992623SN/A unsigned flags, uint64_t *res); 4002623SN/A 4012623SN/Atemplate 4022623SN/AFault 4032623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 4042623SN/A unsigned flags, uint64_t *res); 4052623SN/A 4062623SN/Atemplate 4072623SN/AFault 4082623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 4092623SN/A unsigned flags, uint64_t *res); 4102623SN/A 4112623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4122623SN/A 4132623SN/Atemplate<> 4142623SN/AFault 4152623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 4162623SN/A{ 4172623SN/A return write(*(uint64_t*)&data, addr, flags, res); 4182623SN/A} 4192623SN/A 4202623SN/Atemplate<> 4212623SN/AFault 4222623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 4232623SN/A{ 4242623SN/A return write(*(uint32_t*)&data, addr, flags, res); 4252623SN/A} 4262623SN/A 4272623SN/A 4282623SN/Atemplate<> 4292623SN/AFault 4302623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 4312623SN/A{ 4322623SN/A return write((uint32_t)data, addr, flags, res); 4332623SN/A} 4342623SN/A 4352623SN/A 4362623SN/Avoid 4372623SN/ATimingSimpleCPU::fetch() 4382623SN/A{ 4393387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 4403387Sgblack@eecs.umich.edu checkForInterrupts(); 4412631SN/A 4422663Sstever@eecs.umich.edu Request *ifetch_req = new Request(); 4433170Sstever@eecs.umich.edu ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0); 4442662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 4452623SN/A 4462641Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 4472623SN/A ifetch_pkt->dataStatic(&inst); 4482623SN/A 4492623SN/A if (fault == NoFault) { 4502630SN/A if (!icachePort.sendTiming(ifetch_pkt)) { 4512623SN/A // Need to wait for retry 4522623SN/A _status = IcacheRetry; 4532623SN/A } else { 4542623SN/A // Need to wait for cache to respond 4552623SN/A _status = IcacheWaitResponse; 4562623SN/A // ownership of packet transferred to memory system 4572623SN/A ifetch_pkt = NULL; 4582623SN/A } 4592623SN/A } else { 4602644Sstever@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 4612644Sstever@eecs.umich.edu advanceInst(fault); 4622623SN/A } 4633222Sktlim@umich.edu 4643222Sktlim@umich.edu numCycles += curTick - previousTick; 4653222Sktlim@umich.edu previousTick = curTick; 4662623SN/A} 4672623SN/A 4682623SN/A 4692623SN/Avoid 4702644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 4712623SN/A{ 4722623SN/A advancePC(fault); 4732623SN/A 4742631SN/A if (_status == Running) { 4752631SN/A // kick off fetch of next instruction... callback from icache 4762631SN/A // response will cause that instruction to be executed, 4772631SN/A // keeping the CPU running. 4782631SN/A fetch(); 4792631SN/A } 4802623SN/A} 4812623SN/A 4822623SN/A 4832623SN/Avoid 4843349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 4852623SN/A{ 4862623SN/A // received a response from the icache: execute the received 4872623SN/A // instruction 4882644Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 4892623SN/A assert(_status == IcacheWaitResponse); 4902798Sktlim@umich.edu 4912623SN/A _status = Running; 4922644Sstever@eecs.umich.edu 4932644Sstever@eecs.umich.edu delete pkt->req; 4942644Sstever@eecs.umich.edu delete pkt; 4952644Sstever@eecs.umich.edu 4963222Sktlim@umich.edu numCycles += curTick - previousTick; 4973222Sktlim@umich.edu previousTick = curTick; 4983222Sktlim@umich.edu 4992839Sktlim@umich.edu if (getState() == SimObject::Draining) { 5002839Sktlim@umich.edu completeDrain(); 5012798Sktlim@umich.edu return; 5022798Sktlim@umich.edu } 5032798Sktlim@umich.edu 5042623SN/A preExecute(); 5052644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 5062623SN/A // load or store: just send to dcache 5072623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 5083170Sstever@eecs.umich.edu if (_status != Running) { 5093170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 5103170Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DcacheRetry); 5113170Sstever@eecs.umich.edu assert(fault == NoFault); 5122644Sstever@eecs.umich.edu } else { 5133170Sstever@eecs.umich.edu if (fault == NoFault) { 5143170Sstever@eecs.umich.edu // early fail on store conditional: complete now 5153170Sstever@eecs.umich.edu assert(dcache_pkt != NULL); 5163170Sstever@eecs.umich.edu fault = curStaticInst->completeAcc(dcache_pkt, this, 5173170Sstever@eecs.umich.edu traceData); 5183170Sstever@eecs.umich.edu delete dcache_pkt->req; 5193170Sstever@eecs.umich.edu delete dcache_pkt; 5203170Sstever@eecs.umich.edu dcache_pkt = NULL; 5213170Sstever@eecs.umich.edu } 5222644Sstever@eecs.umich.edu postExecute(); 5232644Sstever@eecs.umich.edu advanceInst(fault); 5242644Sstever@eecs.umich.edu } 5252623SN/A } else { 5262623SN/A // non-memory instruction: execute completely now 5272623SN/A Fault fault = curStaticInst->execute(this, traceData); 5282644Sstever@eecs.umich.edu postExecute(); 5292644Sstever@eecs.umich.edu advanceInst(fault); 5302623SN/A } 5312623SN/A} 5322623SN/A 5332948Ssaidi@eecs.umich.eduvoid 5342948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 5352948Ssaidi@eecs.umich.edu{ 5362948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 5372948Ssaidi@eecs.umich.edu} 5382623SN/A 5392623SN/Abool 5403349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 5412623SN/A{ 5423310Srdreslin@umich.edu if (pkt->isResponse()) { 5433310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 5443495Sktlim@umich.edu Tick mem_time = pkt->req->getTime(); 5453495Sktlim@umich.edu Tick next_tick = cpu->nextCycle(mem_time); 5462948Ssaidi@eecs.umich.edu 5473495Sktlim@umich.edu if (next_tick == curTick) 5483310Srdreslin@umich.edu cpu->completeIfetch(pkt); 5493310Srdreslin@umich.edu else 5503495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 5512948Ssaidi@eecs.umich.edu 5523310Srdreslin@umich.edu return true; 5533310Srdreslin@umich.edu } 5543310Srdreslin@umich.edu else { 5553310Srdreslin@umich.edu //Snooping a Coherence Request, do nothing 5563310Srdreslin@umich.edu return true; 5573310Srdreslin@umich.edu } 5582623SN/A} 5592623SN/A 5602657Ssaidi@eecs.umich.eduvoid 5612623SN/ATimingSimpleCPU::IcachePort::recvRetry() 5622623SN/A{ 5632623SN/A // we shouldn't get a retry unless we have a packet that we're 5642623SN/A // waiting to transmit 5652623SN/A assert(cpu->ifetch_pkt != NULL); 5662623SN/A assert(cpu->_status == IcacheRetry); 5673349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 5682657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 5692657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 5702657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 5712657Ssaidi@eecs.umich.edu } 5722623SN/A} 5732623SN/A 5742623SN/Avoid 5753349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 5762623SN/A{ 5772623SN/A // received a response from the dcache: complete the load or store 5782623SN/A // instruction 5792641Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 5802623SN/A assert(_status == DcacheWaitResponse); 5812623SN/A _status = Running; 5822623SN/A 5833222Sktlim@umich.edu numCycles += curTick - previousTick; 5843222Sktlim@umich.edu previousTick = curTick; 5853184Srdreslin@umich.edu 5862623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 5872623SN/A 5883170Sstever@eecs.umich.edu if (pkt->isRead() && pkt->req->isLocked()) { 5893170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 5903170Sstever@eecs.umich.edu } 5913170Sstever@eecs.umich.edu 5922644Sstever@eecs.umich.edu delete pkt->req; 5932644Sstever@eecs.umich.edu delete pkt; 5942644Sstever@eecs.umich.edu 5953184Srdreslin@umich.edu postExecute(); 5963227Sktlim@umich.edu 5973201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 5983201Shsul@eecs.umich.edu advancePC(fault); 5993201Shsul@eecs.umich.edu completeDrain(); 6003201Shsul@eecs.umich.edu 6013201Shsul@eecs.umich.edu return; 6023201Shsul@eecs.umich.edu } 6033201Shsul@eecs.umich.edu 6042644Sstever@eecs.umich.edu advanceInst(fault); 6052623SN/A} 6062623SN/A 6072623SN/A 6082798Sktlim@umich.eduvoid 6092839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 6102798Sktlim@umich.edu{ 6112839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 6122901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 6132839Sktlim@umich.edu drainEvent->process(); 6142798Sktlim@umich.edu} 6152623SN/A 6162623SN/Abool 6173349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 6182623SN/A{ 6193310Srdreslin@umich.edu if (pkt->isResponse()) { 6203310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 6213495Sktlim@umich.edu Tick mem_time = pkt->req->getTime(); 6223495Sktlim@umich.edu Tick next_tick = cpu->nextCycle(mem_time); 6232948Ssaidi@eecs.umich.edu 6243495Sktlim@umich.edu if (next_tick == curTick) 6253310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 6263310Srdreslin@umich.edu else 6273495Sktlim@umich.edu tickEvent.schedule(pkt, next_tick); 6282948Ssaidi@eecs.umich.edu 6293310Srdreslin@umich.edu return true; 6303310Srdreslin@umich.edu } 6313310Srdreslin@umich.edu else { 6323310Srdreslin@umich.edu //Snooping a coherence req, do nothing 6333310Srdreslin@umich.edu return true; 6343310Srdreslin@umich.edu } 6352948Ssaidi@eecs.umich.edu} 6362948Ssaidi@eecs.umich.edu 6372948Ssaidi@eecs.umich.eduvoid 6382948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 6392948Ssaidi@eecs.umich.edu{ 6402630SN/A cpu->completeDataAccess(pkt); 6412623SN/A} 6422623SN/A 6432657Ssaidi@eecs.umich.eduvoid 6442623SN/ATimingSimpleCPU::DcachePort::recvRetry() 6452623SN/A{ 6462623SN/A // we shouldn't get a retry unless we have a packet that we're 6472623SN/A // waiting to transmit 6482623SN/A assert(cpu->dcache_pkt != NULL); 6492623SN/A assert(cpu->_status == DcacheRetry); 6503349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 6512657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 6522657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 6533170Sstever@eecs.umich.edu // memory system takes ownership of packet 6542657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 6552657Ssaidi@eecs.umich.edu } 6562623SN/A} 6572623SN/A 6582623SN/A 6592623SN/A//////////////////////////////////////////////////////////////////////// 6602623SN/A// 6612623SN/A// TimingSimpleCPU Simulation Object 6622623SN/A// 6632623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6642623SN/A 6652623SN/A Param<Counter> max_insts_any_thread; 6662623SN/A Param<Counter> max_insts_all_threads; 6672623SN/A Param<Counter> max_loads_any_thread; 6682623SN/A Param<Counter> max_loads_all_threads; 6693119Sktlim@umich.edu Param<Tick> progress_interval; 6702901Ssaidi@eecs.umich.edu SimObjectParam<System *> system; 6713170Sstever@eecs.umich.edu Param<int> cpu_id; 6722623SN/A 6732623SN/A#if FULL_SYSTEM 6743453Sgblack@eecs.umich.edu SimObjectParam<TheISA::ITB *> itb; 6753453Sgblack@eecs.umich.edu SimObjectParam<TheISA::DTB *> dtb; 6762623SN/A Param<Tick> profile; 6773617Sbinkertn@umich.edu 6783617Sbinkertn@umich.edu Param<bool> do_quiesce; 6793617Sbinkertn@umich.edu Param<bool> do_checkpoint_insts; 6803617Sbinkertn@umich.edu Param<bool> do_statistics_insts; 6812623SN/A#else 6822623SN/A SimObjectParam<Process *> workload; 6832623SN/A#endif // FULL_SYSTEM 6842623SN/A 6852623SN/A Param<int> clock; 6862623SN/A 6872623SN/A Param<bool> defer_registration; 6882623SN/A Param<int> width; 6892623SN/A Param<bool> function_trace; 6902623SN/A Param<Tick> function_trace_start; 6912623SN/A Param<bool> simulate_stalls; 6922623SN/A 6932623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6942623SN/A 6952623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6962623SN/A 6972623SN/A INIT_PARAM(max_insts_any_thread, 6982623SN/A "terminate when any thread reaches this inst count"), 6992623SN/A INIT_PARAM(max_insts_all_threads, 7002623SN/A "terminate when all threads have reached this inst count"), 7012623SN/A INIT_PARAM(max_loads_any_thread, 7022623SN/A "terminate when any thread reaches this load count"), 7032623SN/A INIT_PARAM(max_loads_all_threads, 7042623SN/A "terminate when all threads have reached this load count"), 7053119Sktlim@umich.edu INIT_PARAM(progress_interval, "Progress interval"), 7062901Ssaidi@eecs.umich.edu INIT_PARAM(system, "system object"), 7073170Sstever@eecs.umich.edu INIT_PARAM(cpu_id, "processor ID"), 7082623SN/A 7092623SN/A#if FULL_SYSTEM 7102623SN/A INIT_PARAM(itb, "Instruction TLB"), 7112623SN/A INIT_PARAM(dtb, "Data TLB"), 7122623SN/A INIT_PARAM(profile, ""), 7133617Sbinkertn@umich.edu INIT_PARAM(do_quiesce, ""), 7143617Sbinkertn@umich.edu INIT_PARAM(do_checkpoint_insts, ""), 7153617Sbinkertn@umich.edu INIT_PARAM(do_statistics_insts, ""), 7162623SN/A#else 7172623SN/A INIT_PARAM(workload, "processes to run"), 7182623SN/A#endif // FULL_SYSTEM 7192623SN/A 7202623SN/A INIT_PARAM(clock, "clock speed"), 7212623SN/A INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 7222623SN/A INIT_PARAM(width, "cpu width"), 7232623SN/A INIT_PARAM(function_trace, "Enable function trace"), 7242623SN/A INIT_PARAM(function_trace_start, "Cycle to start function trace"), 7252623SN/A INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 7262623SN/A 7272623SN/AEND_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 7282623SN/A 7292623SN/A 7302623SN/ACREATE_SIM_OBJECT(TimingSimpleCPU) 7312623SN/A{ 7322623SN/A TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 7332623SN/A params->name = getInstanceName(); 7342623SN/A params->numberOfThreads = 1; 7352623SN/A params->max_insts_any_thread = max_insts_any_thread; 7362623SN/A params->max_insts_all_threads = max_insts_all_threads; 7372623SN/A params->max_loads_any_thread = max_loads_any_thread; 7382623SN/A params->max_loads_all_threads = max_loads_all_threads; 7393119Sktlim@umich.edu params->progress_interval = progress_interval; 7402623SN/A params->deferRegistration = defer_registration; 7412623SN/A params->clock = clock; 7422623SN/A params->functionTrace = function_trace; 7432623SN/A params->functionTraceStart = function_trace_start; 7442901Ssaidi@eecs.umich.edu params->system = system; 7453170Sstever@eecs.umich.edu params->cpu_id = cpu_id; 7462623SN/A 7472623SN/A#if FULL_SYSTEM 7482623SN/A params->itb = itb; 7492623SN/A params->dtb = dtb; 7502623SN/A params->profile = profile; 7513617Sbinkertn@umich.edu params->do_quiesce = do_quiesce; 7523617Sbinkertn@umich.edu params->do_checkpoint_insts = do_checkpoint_insts; 7533617Sbinkertn@umich.edu params->do_statistics_insts = do_statistics_insts; 7542623SN/A#else 7552623SN/A params->process = workload; 7562623SN/A#endif 7572623SN/A 7582623SN/A TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 7592623SN/A return cpu; 7602623SN/A} 7612623SN/A 7622623SN/AREGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 7632623SN/A 764