timing.cc revision 3387
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 322623SN/A#include "arch/utility.hh" 332623SN/A#include "cpu/exetrace.hh" 342623SN/A#include "cpu/simple/timing.hh" 353348Sbinkertn@umich.edu#include "mem/packet.hh" 363348Sbinkertn@umich.edu#include "mem/packet_access.hh" 372623SN/A#include "sim/builder.hh" 382901Ssaidi@eecs.umich.edu#include "sim/system.hh" 392623SN/A 402623SN/Ausing namespace std; 412623SN/Ausing namespace TheISA; 422623SN/A 432856Srdreslin@umich.eduPort * 442856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 452856Srdreslin@umich.edu{ 462856Srdreslin@umich.edu if (if_name == "dcache_port") 472856Srdreslin@umich.edu return &dcachePort; 482856Srdreslin@umich.edu else if (if_name == "icache_port") 492856Srdreslin@umich.edu return &icachePort; 502856Srdreslin@umich.edu else 512856Srdreslin@umich.edu panic("No Such Port\n"); 522856Srdreslin@umich.edu} 532623SN/A 542623SN/Avoid 552623SN/ATimingSimpleCPU::init() 562623SN/A{ 572623SN/A BaseCPU::init(); 582623SN/A#if FULL_SYSTEM 592680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 602680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 612623SN/A 622623SN/A // initialize CPU, including PC 632680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 642623SN/A } 652623SN/A#endif 662623SN/A} 672623SN/A 682623SN/ATick 693349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 702623SN/A{ 712623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 722623SN/A return curTick; 732623SN/A} 742623SN/A 752623SN/Avoid 763349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 772623SN/A{ 783184Srdreslin@umich.edu //No internal storage to update, jusst return 793184Srdreslin@umich.edu return; 802623SN/A} 812623SN/A 822623SN/Avoid 832623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 842623SN/A{ 852631SN/A if (status == RangeChange) 862631SN/A return; 872631SN/A 882623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 892623SN/A} 902623SN/A 912948Ssaidi@eecs.umich.edu 922948Ssaidi@eecs.umich.eduvoid 933349Sbinkertn@umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 942948Ssaidi@eecs.umich.edu{ 952948Ssaidi@eecs.umich.edu pkt = _pkt; 962948Ssaidi@eecs.umich.edu Event::schedule(t); 972948Ssaidi@eecs.umich.edu} 982948Ssaidi@eecs.umich.edu 992623SN/ATimingSimpleCPU::TimingSimpleCPU(Params *p) 1003170Sstever@eecs.umich.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), 1013170Sstever@eecs.umich.edu cpu_id(p->cpu_id) 1022623SN/A{ 1032623SN/A _status = Idle; 1042623SN/A ifetch_pkt = dcache_pkt = NULL; 1052839Sktlim@umich.edu drainEvent = NULL; 1062867Sktlim@umich.edu fetchEvent = NULL; 1073222Sktlim@umich.edu previousTick = 0; 1082901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1092623SN/A} 1102623SN/A 1112623SN/A 1122623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1132623SN/A{ 1142623SN/A} 1152623SN/A 1162623SN/Avoid 1172623SN/ATimingSimpleCPU::serialize(ostream &os) 1182623SN/A{ 1192915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1202915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1212623SN/A BaseSimpleCPU::serialize(os); 1222623SN/A} 1232623SN/A 1242623SN/Avoid 1252623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1262623SN/A{ 1272915Sktlim@umich.edu SimObject::State so_state; 1282915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1292623SN/A BaseSimpleCPU::unserialize(cp, section); 1302798Sktlim@umich.edu} 1312798Sktlim@umich.edu 1322901Ssaidi@eecs.umich.eduunsigned int 1332839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1342798Sktlim@umich.edu{ 1352839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1362798Sktlim@umich.edu // an access to complete. 1372798Sktlim@umich.edu if (status() == Idle || status() == Running || status() == SwitchedOut) { 1382901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1392901Ssaidi@eecs.umich.edu return 0; 1402798Sktlim@umich.edu } else { 1412839Sktlim@umich.edu changeState(SimObject::Draining); 1422839Sktlim@umich.edu drainEvent = drain_event; 1432901Ssaidi@eecs.umich.edu return 1; 1442798Sktlim@umich.edu } 1452623SN/A} 1462623SN/A 1472623SN/Avoid 1482798Sktlim@umich.eduTimingSimpleCPU::resume() 1492623SN/A{ 1502798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1513201Shsul@eecs.umich.edu assert(system->getMemoryMode() == System::Timing); 1523201Shsul@eecs.umich.edu 1532867Sktlim@umich.edu // Delete the old event if it existed. 1542867Sktlim@umich.edu if (fetchEvent) { 1552915Sktlim@umich.edu if (fetchEvent->scheduled()) 1562915Sktlim@umich.edu fetchEvent->deschedule(); 1572915Sktlim@umich.edu 1582867Sktlim@umich.edu delete fetchEvent; 1592867Sktlim@umich.edu } 1602867Sktlim@umich.edu 1612867Sktlim@umich.edu fetchEvent = 1622867Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 1632867Sktlim@umich.edu fetchEvent->schedule(curTick); 1642623SN/A } 1652798Sktlim@umich.edu 1662901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1673222Sktlim@umich.edu previousTick = curTick; 1682798Sktlim@umich.edu} 1692798Sktlim@umich.edu 1702798Sktlim@umich.eduvoid 1712798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1722798Sktlim@umich.edu{ 1732798Sktlim@umich.edu assert(status() == Running || status() == Idle); 1742798Sktlim@umich.edu _status = SwitchedOut; 1753222Sktlim@umich.edu numCycles += curTick - previousTick; 1762867Sktlim@umich.edu 1772867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1782867Sktlim@umich.edu // we'll need to cancel it. 1792867Sktlim@umich.edu if (fetchEvent && fetchEvent->scheduled()) 1802867Sktlim@umich.edu fetchEvent->deschedule(); 1812623SN/A} 1822623SN/A 1832623SN/A 1842623SN/Avoid 1852623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1862623SN/A{ 1872623SN/A BaseCPU::takeOverFrom(oldCPU); 1882623SN/A 1892680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1902623SN/A // running and schedule its tick event. 1912680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1922680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1932680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 1942623SN/A _status = Running; 1952623SN/A break; 1962623SN/A } 1972623SN/A } 1983201Shsul@eecs.umich.edu 1993201Shsul@eecs.umich.edu if (_status != Running) { 2003201Shsul@eecs.umich.edu _status = Idle; 2013201Shsul@eecs.umich.edu } 2023227Sktlim@umich.edu 2033222Sktlim@umich.edu Port *peer; 2043222Sktlim@umich.edu if (icachePort.getPeer() == NULL) { 2053227Sktlim@umich.edu peer = oldCPU->getPort("icache_port")->getPeer(); 2063222Sktlim@umich.edu icachePort.setPeer(peer); 2073222Sktlim@umich.edu } else { 2083222Sktlim@umich.edu peer = icachePort.getPeer(); 2093222Sktlim@umich.edu } 2103222Sktlim@umich.edu peer->setPeer(&icachePort); 2113222Sktlim@umich.edu 2123222Sktlim@umich.edu if (dcachePort.getPeer() == NULL) { 2133227Sktlim@umich.edu peer = oldCPU->getPort("dcache_port")->getPeer(); 2143222Sktlim@umich.edu dcachePort.setPeer(peer); 2153222Sktlim@umich.edu } else { 2163222Sktlim@umich.edu peer = dcachePort.getPeer(); 2173222Sktlim@umich.edu } 2183222Sktlim@umich.edu peer->setPeer(&dcachePort); 2192623SN/A} 2202623SN/A 2212623SN/A 2222623SN/Avoid 2232623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2242623SN/A{ 2252623SN/A assert(thread_num == 0); 2262683Sktlim@umich.edu assert(thread); 2272623SN/A 2282623SN/A assert(_status == Idle); 2292623SN/A 2302623SN/A notIdleFraction++; 2312623SN/A _status = Running; 2322623SN/A // kick things off by initiating the fetch of the next instruction 2332867Sktlim@umich.edu fetchEvent = 2342867Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 2352867Sktlim@umich.edu fetchEvent->schedule(curTick + cycles(delay)); 2362623SN/A} 2372623SN/A 2382623SN/A 2392623SN/Avoid 2402623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2412623SN/A{ 2422623SN/A assert(thread_num == 0); 2432683Sktlim@umich.edu assert(thread); 2442623SN/A 2452644Sstever@eecs.umich.edu assert(_status == Running); 2462623SN/A 2472644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2482644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2492623SN/A 2502623SN/A notIdleFraction--; 2512623SN/A _status = Idle; 2522623SN/A} 2532623SN/A 2542623SN/A 2552623SN/Atemplate <class T> 2562623SN/AFault 2572623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2582623SN/A{ 2593169Sstever@eecs.umich.edu Request *req = 2603169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 2613170Sstever@eecs.umich.edu cpu_id, /* thread ID */ 0); 2622623SN/A 2632623SN/A if (traceData) { 2643169Sstever@eecs.umich.edu traceData->setAddr(req->getVaddr()); 2652623SN/A } 2662623SN/A 2672623SN/A // translate to physical address 2683169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2692623SN/A 2702623SN/A // Now do the access. 2712623SN/A if (fault == NoFault) { 2723349Sbinkertn@umich.edu PacketPtr pkt = 2733169Sstever@eecs.umich.edu new Packet(req, Packet::ReadReq, Packet::Broadcast); 2743169Sstever@eecs.umich.edu pkt->dataDynamic<T>(new T); 2752623SN/A 2763169Sstever@eecs.umich.edu if (!dcachePort.sendTiming(pkt)) { 2772623SN/A _status = DcacheRetry; 2783169Sstever@eecs.umich.edu dcache_pkt = pkt; 2792623SN/A } else { 2802623SN/A _status = DcacheWaitResponse; 2813169Sstever@eecs.umich.edu // memory system takes ownership of packet 2822623SN/A dcache_pkt = NULL; 2832623SN/A } 2842623SN/A } 2852623SN/A 2862623SN/A // This will need a new way to tell if it has a dcache attached. 2873172Sstever@eecs.umich.edu if (req->isUncacheable()) 2882623SN/A recordEvent("Uncached Read"); 2892623SN/A 2902623SN/A return fault; 2912623SN/A} 2922623SN/A 2932623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 2942623SN/A 2952623SN/Atemplate 2962623SN/AFault 2972623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 2982623SN/A 2992623SN/Atemplate 3002623SN/AFault 3012623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3022623SN/A 3032623SN/Atemplate 3042623SN/AFault 3052623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 3062623SN/A 3072623SN/Atemplate 3082623SN/AFault 3092623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3102623SN/A 3112623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3122623SN/A 3132623SN/Atemplate<> 3142623SN/AFault 3152623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 3162623SN/A{ 3172623SN/A return read(addr, *(uint64_t*)&data, flags); 3182623SN/A} 3192623SN/A 3202623SN/Atemplate<> 3212623SN/AFault 3222623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 3232623SN/A{ 3242623SN/A return read(addr, *(uint32_t*)&data, flags); 3252623SN/A} 3262623SN/A 3272623SN/A 3282623SN/Atemplate<> 3292623SN/AFault 3302623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3312623SN/A{ 3322623SN/A return read(addr, (uint32_t&)data, flags); 3332623SN/A} 3342623SN/A 3352623SN/A 3362623SN/Atemplate <class T> 3372623SN/AFault 3382623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3392623SN/A{ 3403169Sstever@eecs.umich.edu Request *req = 3413169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 3423170Sstever@eecs.umich.edu cpu_id, /* thread ID */ 0); 3432623SN/A 3442623SN/A // translate to physical address 3453169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3463169Sstever@eecs.umich.edu 3472623SN/A // Now do the access. 3482623SN/A if (fault == NoFault) { 3493169Sstever@eecs.umich.edu assert(dcache_pkt == NULL); 3503169Sstever@eecs.umich.edu dcache_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 3513169Sstever@eecs.umich.edu dcache_pkt->allocate(); 3523169Sstever@eecs.umich.edu dcache_pkt->set(data); 3532623SN/A 3543170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3553170Sstever@eecs.umich.edu 3563170Sstever@eecs.umich.edu if (req->isLocked()) { 3573170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3583170Sstever@eecs.umich.edu } 3593170Sstever@eecs.umich.edu 3603170Sstever@eecs.umich.edu if (do_access) { 3613170Sstever@eecs.umich.edu if (!dcachePort.sendTiming(dcache_pkt)) { 3623170Sstever@eecs.umich.edu _status = DcacheRetry; 3633170Sstever@eecs.umich.edu } else { 3643170Sstever@eecs.umich.edu _status = DcacheWaitResponse; 3653170Sstever@eecs.umich.edu // memory system takes ownership of packet 3663170Sstever@eecs.umich.edu dcache_pkt = NULL; 3673170Sstever@eecs.umich.edu } 3682623SN/A } 3692623SN/A } 3702623SN/A 3712623SN/A // This will need a new way to tell if it's hooked up to a cache or not. 3723172Sstever@eecs.umich.edu if (req->isUncacheable()) 3732623SN/A recordEvent("Uncached Write"); 3742623SN/A 3752623SN/A // If the write needs to have a fault on the access, consider calling 3762623SN/A // changeStatus() and changing it to "bad addr write" or something. 3772623SN/A return fault; 3782623SN/A} 3792623SN/A 3802623SN/A 3812623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3822623SN/Atemplate 3832623SN/AFault 3842623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 3852623SN/A unsigned flags, uint64_t *res); 3862623SN/A 3872623SN/Atemplate 3882623SN/AFault 3892623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 3902623SN/A unsigned flags, uint64_t *res); 3912623SN/A 3922623SN/Atemplate 3932623SN/AFault 3942623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 3952623SN/A unsigned flags, uint64_t *res); 3962623SN/A 3972623SN/Atemplate 3982623SN/AFault 3992623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 4002623SN/A unsigned flags, uint64_t *res); 4012623SN/A 4022623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4032623SN/A 4042623SN/Atemplate<> 4052623SN/AFault 4062623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 4072623SN/A{ 4082623SN/A return write(*(uint64_t*)&data, addr, flags, res); 4092623SN/A} 4102623SN/A 4112623SN/Atemplate<> 4122623SN/AFault 4132623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 4142623SN/A{ 4152623SN/A return write(*(uint32_t*)&data, addr, flags, res); 4162623SN/A} 4172623SN/A 4182623SN/A 4192623SN/Atemplate<> 4202623SN/AFault 4212623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 4222623SN/A{ 4232623SN/A return write((uint32_t)data, addr, flags, res); 4242623SN/A} 4252623SN/A 4262623SN/A 4272623SN/Avoid 4282623SN/ATimingSimpleCPU::fetch() 4292623SN/A{ 4303387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 4313387Sgblack@eecs.umich.edu checkForInterrupts(); 4322631SN/A 4332663Sstever@eecs.umich.edu Request *ifetch_req = new Request(); 4343170Sstever@eecs.umich.edu ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0); 4352662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 4362623SN/A 4372641Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 4382623SN/A ifetch_pkt->dataStatic(&inst); 4392623SN/A 4402623SN/A if (fault == NoFault) { 4412630SN/A if (!icachePort.sendTiming(ifetch_pkt)) { 4422623SN/A // Need to wait for retry 4432623SN/A _status = IcacheRetry; 4442623SN/A } else { 4452623SN/A // Need to wait for cache to respond 4462623SN/A _status = IcacheWaitResponse; 4472623SN/A // ownership of packet transferred to memory system 4482623SN/A ifetch_pkt = NULL; 4492623SN/A } 4502623SN/A } else { 4512644Sstever@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 4522644Sstever@eecs.umich.edu advanceInst(fault); 4532623SN/A } 4543222Sktlim@umich.edu 4553222Sktlim@umich.edu numCycles += curTick - previousTick; 4563222Sktlim@umich.edu previousTick = curTick; 4572623SN/A} 4582623SN/A 4592623SN/A 4602623SN/Avoid 4612644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 4622623SN/A{ 4632623SN/A advancePC(fault); 4642623SN/A 4652631SN/A if (_status == Running) { 4662631SN/A // kick off fetch of next instruction... callback from icache 4672631SN/A // response will cause that instruction to be executed, 4682631SN/A // keeping the CPU running. 4692631SN/A fetch(); 4702631SN/A } 4712623SN/A} 4722623SN/A 4732623SN/A 4742623SN/Avoid 4753349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 4762623SN/A{ 4772623SN/A // received a response from the icache: execute the received 4782623SN/A // instruction 4792644Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 4802623SN/A assert(_status == IcacheWaitResponse); 4812798Sktlim@umich.edu 4822623SN/A _status = Running; 4832644Sstever@eecs.umich.edu 4842644Sstever@eecs.umich.edu delete pkt->req; 4852644Sstever@eecs.umich.edu delete pkt; 4862644Sstever@eecs.umich.edu 4873222Sktlim@umich.edu numCycles += curTick - previousTick; 4883222Sktlim@umich.edu previousTick = curTick; 4893222Sktlim@umich.edu 4902839Sktlim@umich.edu if (getState() == SimObject::Draining) { 4912839Sktlim@umich.edu completeDrain(); 4922798Sktlim@umich.edu return; 4932798Sktlim@umich.edu } 4942798Sktlim@umich.edu 4952623SN/A preExecute(); 4962644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 4972623SN/A // load or store: just send to dcache 4982623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 4993170Sstever@eecs.umich.edu if (_status != Running) { 5003170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 5013170Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DcacheRetry); 5023170Sstever@eecs.umich.edu assert(fault == NoFault); 5032644Sstever@eecs.umich.edu } else { 5043170Sstever@eecs.umich.edu if (fault == NoFault) { 5053170Sstever@eecs.umich.edu // early fail on store conditional: complete now 5063170Sstever@eecs.umich.edu assert(dcache_pkt != NULL); 5073170Sstever@eecs.umich.edu fault = curStaticInst->completeAcc(dcache_pkt, this, 5083170Sstever@eecs.umich.edu traceData); 5093170Sstever@eecs.umich.edu delete dcache_pkt->req; 5103170Sstever@eecs.umich.edu delete dcache_pkt; 5113170Sstever@eecs.umich.edu dcache_pkt = NULL; 5123170Sstever@eecs.umich.edu } 5132644Sstever@eecs.umich.edu postExecute(); 5142644Sstever@eecs.umich.edu advanceInst(fault); 5152644Sstever@eecs.umich.edu } 5162623SN/A } else { 5172623SN/A // non-memory instruction: execute completely now 5182623SN/A Fault fault = curStaticInst->execute(this, traceData); 5192644Sstever@eecs.umich.edu postExecute(); 5202644Sstever@eecs.umich.edu advanceInst(fault); 5212623SN/A } 5222623SN/A} 5232623SN/A 5242948Ssaidi@eecs.umich.eduvoid 5252948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 5262948Ssaidi@eecs.umich.edu{ 5272948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 5282948Ssaidi@eecs.umich.edu} 5292623SN/A 5302623SN/Abool 5313349Sbinkertn@umich.eduTimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 5322623SN/A{ 5333310Srdreslin@umich.edu if (pkt->isResponse()) { 5343310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 5353310Srdreslin@umich.edu Tick time = pkt->req->getTime(); 5363310Srdreslin@umich.edu while (time < curTick) 5373310Srdreslin@umich.edu time += lat; 5382948Ssaidi@eecs.umich.edu 5393310Srdreslin@umich.edu if (time == curTick) 5403310Srdreslin@umich.edu cpu->completeIfetch(pkt); 5413310Srdreslin@umich.edu else 5423310Srdreslin@umich.edu tickEvent.schedule(pkt, time); 5432948Ssaidi@eecs.umich.edu 5443310Srdreslin@umich.edu return true; 5453310Srdreslin@umich.edu } 5463310Srdreslin@umich.edu else { 5473310Srdreslin@umich.edu //Snooping a Coherence Request, do nothing 5483310Srdreslin@umich.edu return true; 5493310Srdreslin@umich.edu } 5502623SN/A} 5512623SN/A 5522657Ssaidi@eecs.umich.eduvoid 5532623SN/ATimingSimpleCPU::IcachePort::recvRetry() 5542623SN/A{ 5552623SN/A // we shouldn't get a retry unless we have a packet that we're 5562623SN/A // waiting to transmit 5572623SN/A assert(cpu->ifetch_pkt != NULL); 5582623SN/A assert(cpu->_status == IcacheRetry); 5593349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 5602657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 5612657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 5622657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 5632657Ssaidi@eecs.umich.edu } 5642623SN/A} 5652623SN/A 5662623SN/Avoid 5673349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 5682623SN/A{ 5692623SN/A // received a response from the dcache: complete the load or store 5702623SN/A // instruction 5712641Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 5722623SN/A assert(_status == DcacheWaitResponse); 5732623SN/A _status = Running; 5742623SN/A 5753222Sktlim@umich.edu numCycles += curTick - previousTick; 5763222Sktlim@umich.edu previousTick = curTick; 5773184Srdreslin@umich.edu 5782623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 5792623SN/A 5803170Sstever@eecs.umich.edu if (pkt->isRead() && pkt->req->isLocked()) { 5813170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 5823170Sstever@eecs.umich.edu } 5833170Sstever@eecs.umich.edu 5842644Sstever@eecs.umich.edu delete pkt->req; 5852644Sstever@eecs.umich.edu delete pkt; 5862644Sstever@eecs.umich.edu 5873184Srdreslin@umich.edu postExecute(); 5883227Sktlim@umich.edu 5893201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 5903201Shsul@eecs.umich.edu advancePC(fault); 5913201Shsul@eecs.umich.edu completeDrain(); 5923201Shsul@eecs.umich.edu 5933201Shsul@eecs.umich.edu return; 5943201Shsul@eecs.umich.edu } 5953201Shsul@eecs.umich.edu 5962644Sstever@eecs.umich.edu advanceInst(fault); 5972623SN/A} 5982623SN/A 5992623SN/A 6002798Sktlim@umich.eduvoid 6012839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 6022798Sktlim@umich.edu{ 6032839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 6042901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 6052839Sktlim@umich.edu drainEvent->process(); 6062798Sktlim@umich.edu} 6072623SN/A 6082623SN/Abool 6093349Sbinkertn@umich.eduTimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 6102623SN/A{ 6113310Srdreslin@umich.edu if (pkt->isResponse()) { 6123310Srdreslin@umich.edu // delay processing of returned data until next CPU clock edge 6133310Srdreslin@umich.edu Tick time = pkt->req->getTime(); 6143310Srdreslin@umich.edu while (time < curTick) 6153310Srdreslin@umich.edu time += lat; 6162948Ssaidi@eecs.umich.edu 6173310Srdreslin@umich.edu if (time == curTick) 6183310Srdreslin@umich.edu cpu->completeDataAccess(pkt); 6193310Srdreslin@umich.edu else 6203310Srdreslin@umich.edu tickEvent.schedule(pkt, time); 6212948Ssaidi@eecs.umich.edu 6223310Srdreslin@umich.edu return true; 6233310Srdreslin@umich.edu } 6243310Srdreslin@umich.edu else { 6253310Srdreslin@umich.edu //Snooping a coherence req, do nothing 6263310Srdreslin@umich.edu return true; 6273310Srdreslin@umich.edu } 6282948Ssaidi@eecs.umich.edu} 6292948Ssaidi@eecs.umich.edu 6302948Ssaidi@eecs.umich.eduvoid 6312948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 6322948Ssaidi@eecs.umich.edu{ 6332630SN/A cpu->completeDataAccess(pkt); 6342623SN/A} 6352623SN/A 6362657Ssaidi@eecs.umich.eduvoid 6372623SN/ATimingSimpleCPU::DcachePort::recvRetry() 6382623SN/A{ 6392623SN/A // we shouldn't get a retry unless we have a packet that we're 6402623SN/A // waiting to transmit 6412623SN/A assert(cpu->dcache_pkt != NULL); 6422623SN/A assert(cpu->_status == DcacheRetry); 6433349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 6442657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 6452657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 6463170Sstever@eecs.umich.edu // memory system takes ownership of packet 6472657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 6482657Ssaidi@eecs.umich.edu } 6492623SN/A} 6502623SN/A 6512623SN/A 6522623SN/A//////////////////////////////////////////////////////////////////////// 6532623SN/A// 6542623SN/A// TimingSimpleCPU Simulation Object 6552623SN/A// 6562623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6572623SN/A 6582623SN/A Param<Counter> max_insts_any_thread; 6592623SN/A Param<Counter> max_insts_all_threads; 6602623SN/A Param<Counter> max_loads_any_thread; 6612623SN/A Param<Counter> max_loads_all_threads; 6623119Sktlim@umich.edu Param<Tick> progress_interval; 6632623SN/A SimObjectParam<MemObject *> mem; 6642901Ssaidi@eecs.umich.edu SimObjectParam<System *> system; 6653170Sstever@eecs.umich.edu Param<int> cpu_id; 6662623SN/A 6672623SN/A#if FULL_SYSTEM 6682623SN/A SimObjectParam<AlphaITB *> itb; 6692623SN/A SimObjectParam<AlphaDTB *> dtb; 6702623SN/A Param<Tick> profile; 6712623SN/A#else 6722623SN/A SimObjectParam<Process *> workload; 6732623SN/A#endif // FULL_SYSTEM 6742623SN/A 6752623SN/A Param<int> clock; 6762623SN/A 6772623SN/A Param<bool> defer_registration; 6782623SN/A Param<int> width; 6792623SN/A Param<bool> function_trace; 6802623SN/A Param<Tick> function_trace_start; 6812623SN/A Param<bool> simulate_stalls; 6822623SN/A 6832623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6842623SN/A 6852623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6862623SN/A 6872623SN/A INIT_PARAM(max_insts_any_thread, 6882623SN/A "terminate when any thread reaches this inst count"), 6892623SN/A INIT_PARAM(max_insts_all_threads, 6902623SN/A "terminate when all threads have reached this inst count"), 6912623SN/A INIT_PARAM(max_loads_any_thread, 6922623SN/A "terminate when any thread reaches this load count"), 6932623SN/A INIT_PARAM(max_loads_all_threads, 6942623SN/A "terminate when all threads have reached this load count"), 6953119Sktlim@umich.edu INIT_PARAM(progress_interval, "Progress interval"), 6962623SN/A INIT_PARAM(mem, "memory"), 6972901Ssaidi@eecs.umich.edu INIT_PARAM(system, "system object"), 6983170Sstever@eecs.umich.edu INIT_PARAM(cpu_id, "processor ID"), 6992623SN/A 7002623SN/A#if FULL_SYSTEM 7012623SN/A INIT_PARAM(itb, "Instruction TLB"), 7022623SN/A INIT_PARAM(dtb, "Data TLB"), 7032623SN/A INIT_PARAM(profile, ""), 7042623SN/A#else 7052623SN/A INIT_PARAM(workload, "processes to run"), 7062623SN/A#endif // FULL_SYSTEM 7072623SN/A 7082623SN/A INIT_PARAM(clock, "clock speed"), 7092623SN/A INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 7102623SN/A INIT_PARAM(width, "cpu width"), 7112623SN/A INIT_PARAM(function_trace, "Enable function trace"), 7122623SN/A INIT_PARAM(function_trace_start, "Cycle to start function trace"), 7132623SN/A INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 7142623SN/A 7152623SN/AEND_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 7162623SN/A 7172623SN/A 7182623SN/ACREATE_SIM_OBJECT(TimingSimpleCPU) 7192623SN/A{ 7202623SN/A TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 7212623SN/A params->name = getInstanceName(); 7222623SN/A params->numberOfThreads = 1; 7232623SN/A params->max_insts_any_thread = max_insts_any_thread; 7242623SN/A params->max_insts_all_threads = max_insts_all_threads; 7252623SN/A params->max_loads_any_thread = max_loads_any_thread; 7262623SN/A params->max_loads_all_threads = max_loads_all_threads; 7273119Sktlim@umich.edu params->progress_interval = progress_interval; 7282623SN/A params->deferRegistration = defer_registration; 7292623SN/A params->clock = clock; 7302623SN/A params->functionTrace = function_trace; 7312623SN/A params->functionTraceStart = function_trace_start; 7322623SN/A params->mem = mem; 7332901Ssaidi@eecs.umich.edu params->system = system; 7343170Sstever@eecs.umich.edu params->cpu_id = cpu_id; 7352623SN/A 7362623SN/A#if FULL_SYSTEM 7372623SN/A params->itb = itb; 7382623SN/A params->dtb = dtb; 7392623SN/A params->profile = profile; 7402623SN/A#else 7412623SN/A params->process = workload; 7422623SN/A#endif 7432623SN/A 7442623SN/A TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 7452623SN/A return cpu; 7462623SN/A} 7472623SN/A 7482623SN/AREGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 7492623SN/A 750