timing.cc revision 3222
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 312623SN/A#include "arch/utility.hh" 322623SN/A#include "cpu/exetrace.hh" 332623SN/A#include "cpu/simple/timing.hh" 342623SN/A#include "mem/packet_impl.hh" 352623SN/A#include "sim/builder.hh" 362901Ssaidi@eecs.umich.edu#include "sim/system.hh" 372623SN/A 382623SN/Ausing namespace std; 392623SN/Ausing namespace TheISA; 402623SN/A 412856Srdreslin@umich.eduPort * 422856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 432856Srdreslin@umich.edu{ 442856Srdreslin@umich.edu if (if_name == "dcache_port") 452856Srdreslin@umich.edu return &dcachePort; 462856Srdreslin@umich.edu else if (if_name == "icache_port") 472856Srdreslin@umich.edu return &icachePort; 482856Srdreslin@umich.edu else 492856Srdreslin@umich.edu panic("No Such Port\n"); 502856Srdreslin@umich.edu} 512623SN/A 522623SN/Avoid 532623SN/ATimingSimpleCPU::init() 542623SN/A{ 552623SN/A BaseCPU::init(); 562623SN/A#if FULL_SYSTEM 572680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 582680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 592623SN/A 602623SN/A // initialize CPU, including PC 612680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 622623SN/A } 632623SN/A#endif 642623SN/A} 652623SN/A 662623SN/ATick 672630SN/ATimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt) 682623SN/A{ 692623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 702623SN/A return curTick; 712623SN/A} 722623SN/A 732623SN/Avoid 742630SN/ATimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt) 752623SN/A{ 762623SN/A panic("TimingSimpleCPU doesn't expect recvFunctional callback!"); 772623SN/A} 782623SN/A 792623SN/Avoid 802623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 812623SN/A{ 822631SN/A if (status == RangeChange) 832631SN/A return; 842631SN/A 852623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 862623SN/A} 872623SN/A 882948Ssaidi@eecs.umich.edu 892948Ssaidi@eecs.umich.eduvoid 902948Ssaidi@eecs.umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t) 912948Ssaidi@eecs.umich.edu{ 922948Ssaidi@eecs.umich.edu pkt = _pkt; 932948Ssaidi@eecs.umich.edu Event::schedule(t); 942948Ssaidi@eecs.umich.edu} 952948Ssaidi@eecs.umich.edu 962623SN/ATimingSimpleCPU::TimingSimpleCPU(Params *p) 972948Ssaidi@eecs.umich.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock) 982623SN/A{ 992623SN/A _status = Idle; 1002623SN/A ifetch_pkt = dcache_pkt = NULL; 1012839Sktlim@umich.edu drainEvent = NULL; 1022867Sktlim@umich.edu fetchEvent = NULL; 1033222Sktlim@umich.edu previousTick = 0; 1042901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1052623SN/A} 1062623SN/A 1072623SN/A 1082623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1092623SN/A{ 1102623SN/A} 1112623SN/A 1122623SN/Avoid 1132623SN/ATimingSimpleCPU::serialize(ostream &os) 1142623SN/A{ 1152915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1162915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1172623SN/A BaseSimpleCPU::serialize(os); 1182623SN/A} 1192623SN/A 1202623SN/Avoid 1212623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1222623SN/A{ 1232915Sktlim@umich.edu SimObject::State so_state; 1242915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1252623SN/A BaseSimpleCPU::unserialize(cp, section); 1262798Sktlim@umich.edu} 1272798Sktlim@umich.edu 1282901Ssaidi@eecs.umich.eduunsigned int 1292839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1302798Sktlim@umich.edu{ 1312839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1322798Sktlim@umich.edu // an access to complete. 1332798Sktlim@umich.edu if (status() == Idle || status() == Running || status() == SwitchedOut) { 1342901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1352901Ssaidi@eecs.umich.edu return 0; 1362798Sktlim@umich.edu } else { 1372839Sktlim@umich.edu changeState(SimObject::Draining); 1382839Sktlim@umich.edu drainEvent = drain_event; 1392901Ssaidi@eecs.umich.edu return 1; 1402798Sktlim@umich.edu } 1412623SN/A} 1422623SN/A 1432623SN/Avoid 1442798Sktlim@umich.eduTimingSimpleCPU::resume() 1452623SN/A{ 1462798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1472867Sktlim@umich.edu // Delete the old event if it existed. 1482867Sktlim@umich.edu if (fetchEvent) { 1492915Sktlim@umich.edu if (fetchEvent->scheduled()) 1502915Sktlim@umich.edu fetchEvent->deschedule(); 1512915Sktlim@umich.edu 1522867Sktlim@umich.edu delete fetchEvent; 1532867Sktlim@umich.edu } 1542867Sktlim@umich.edu 1552867Sktlim@umich.edu fetchEvent = 1562867Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 1572867Sktlim@umich.edu fetchEvent->schedule(curTick); 1582623SN/A } 1592798Sktlim@umich.edu 1602901Ssaidi@eecs.umich.edu assert(system->getMemoryMode() == System::Timing); 1612901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1623222Sktlim@umich.edu previousTick = curTick; 1632798Sktlim@umich.edu} 1642798Sktlim@umich.edu 1652798Sktlim@umich.eduvoid 1662798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1672798Sktlim@umich.edu{ 1682798Sktlim@umich.edu assert(status() == Running || status() == Idle); 1692798Sktlim@umich.edu _status = SwitchedOut; 1703222Sktlim@umich.edu numCycles += curTick - previousTick; 1712867Sktlim@umich.edu 1722867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1732867Sktlim@umich.edu // we'll need to cancel it. 1742867Sktlim@umich.edu if (fetchEvent && fetchEvent->scheduled()) 1752867Sktlim@umich.edu fetchEvent->deschedule(); 1762623SN/A} 1772623SN/A 1782623SN/A 1792623SN/Avoid 1802623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1812623SN/A{ 1822623SN/A BaseCPU::takeOverFrom(oldCPU); 1832623SN/A 1842680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1852623SN/A // running and schedule its tick event. 1862680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1872680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1882680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 1892623SN/A _status = Running; 1902623SN/A break; 1912623SN/A } 1922623SN/A } 1933222Sktlim@umich.edu 1943222Sktlim@umich.edu Port *peer; 1953222Sktlim@umich.edu if (icachePort.getPeer() == NULL) { 1963222Sktlim@umich.edu peer = oldCPU->getPort("icachePort")->getPeer(); 1973222Sktlim@umich.edu icachePort.setPeer(peer); 1983222Sktlim@umich.edu } else { 1993222Sktlim@umich.edu peer = icachePort.getPeer(); 2003222Sktlim@umich.edu } 2013222Sktlim@umich.edu peer->setPeer(&icachePort); 2023222Sktlim@umich.edu 2033222Sktlim@umich.edu if (dcachePort.getPeer() == NULL) { 2043222Sktlim@umich.edu peer = oldCPU->getPort("dcachePort")->getPeer(); 2053222Sktlim@umich.edu dcachePort.setPeer(peer); 2063222Sktlim@umich.edu } else { 2073222Sktlim@umich.edu peer = dcachePort.getPeer(); 2083222Sktlim@umich.edu } 2093222Sktlim@umich.edu peer->setPeer(&dcachePort); 2102623SN/A} 2112623SN/A 2122623SN/A 2132623SN/Avoid 2142623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2152623SN/A{ 2162623SN/A assert(thread_num == 0); 2172683Sktlim@umich.edu assert(thread); 2182623SN/A 2192623SN/A assert(_status == Idle); 2202623SN/A 2212623SN/A notIdleFraction++; 2222623SN/A _status = Running; 2232623SN/A // kick things off by initiating the fetch of the next instruction 2242867Sktlim@umich.edu fetchEvent = 2252867Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 2262867Sktlim@umich.edu fetchEvent->schedule(curTick + cycles(delay)); 2272623SN/A} 2282623SN/A 2292623SN/A 2302623SN/Avoid 2312623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2322623SN/A{ 2332623SN/A assert(thread_num == 0); 2342683Sktlim@umich.edu assert(thread); 2352623SN/A 2362644Sstever@eecs.umich.edu assert(_status == Running); 2372623SN/A 2382644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2392644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2402623SN/A 2412623SN/A notIdleFraction--; 2422623SN/A _status = Idle; 2432623SN/A} 2442623SN/A 2452623SN/A 2462623SN/Atemplate <class T> 2472623SN/AFault 2482623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2492623SN/A{ 2502663Sstever@eecs.umich.edu // need to fill in CPU & thread IDs here 2512663Sstever@eecs.umich.edu Request *data_read_req = new Request(); 2522835Srdreslin@umich.edu data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 2532683Sktlim@umich.edu data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 2542623SN/A 2552623SN/A if (traceData) { 2562623SN/A traceData->setAddr(data_read_req->getVaddr()); 2572623SN/A } 2582623SN/A 2592623SN/A // translate to physical address 2602683Sktlim@umich.edu Fault fault = thread->translateDataReadReq(data_read_req); 2612623SN/A 2622623SN/A // Now do the access. 2632623SN/A if (fault == NoFault) { 2642641Sstever@eecs.umich.edu Packet *data_read_pkt = 2652641Sstever@eecs.umich.edu new Packet(data_read_req, Packet::ReadReq, Packet::Broadcast); 2662623SN/A data_read_pkt->dataDynamic<T>(new T); 2672623SN/A 2682630SN/A if (!dcachePort.sendTiming(data_read_pkt)) { 2692623SN/A _status = DcacheRetry; 2702623SN/A dcache_pkt = data_read_pkt; 2712623SN/A } else { 2722623SN/A _status = DcacheWaitResponse; 2732623SN/A dcache_pkt = NULL; 2742623SN/A } 2752623SN/A } 2762623SN/A 2772623SN/A // This will need a new way to tell if it has a dcache attached. 2782623SN/A if (data_read_req->getFlags() & UNCACHEABLE) 2792623SN/A recordEvent("Uncached Read"); 2802623SN/A 2812623SN/A return fault; 2822623SN/A} 2832623SN/A 2842623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 2852623SN/A 2862623SN/Atemplate 2872623SN/AFault 2882623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 2892623SN/A 2902623SN/Atemplate 2912623SN/AFault 2922623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 2932623SN/A 2942623SN/Atemplate 2952623SN/AFault 2962623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 2972623SN/A 2982623SN/Atemplate 2992623SN/AFault 3002623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3012623SN/A 3022623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3032623SN/A 3042623SN/Atemplate<> 3052623SN/AFault 3062623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 3072623SN/A{ 3082623SN/A return read(addr, *(uint64_t*)&data, flags); 3092623SN/A} 3102623SN/A 3112623SN/Atemplate<> 3122623SN/AFault 3132623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 3142623SN/A{ 3152623SN/A return read(addr, *(uint32_t*)&data, flags); 3162623SN/A} 3172623SN/A 3182623SN/A 3192623SN/Atemplate<> 3202623SN/AFault 3212623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3222623SN/A{ 3232623SN/A return read(addr, (uint32_t&)data, flags); 3242623SN/A} 3252623SN/A 3262623SN/A 3272623SN/Atemplate <class T> 3282623SN/AFault 3292623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3302623SN/A{ 3312663Sstever@eecs.umich.edu // need to fill in CPU & thread IDs here 3322663Sstever@eecs.umich.edu Request *data_write_req = new Request(); 3332835Srdreslin@umich.edu data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 3342683Sktlim@umich.edu data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 3352623SN/A 3362623SN/A // translate to physical address 3372683Sktlim@umich.edu Fault fault = thread->translateDataWriteReq(data_write_req); 3382623SN/A // Now do the access. 3392623SN/A if (fault == NoFault) { 3402641Sstever@eecs.umich.edu Packet *data_write_pkt = 3412641Sstever@eecs.umich.edu new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast); 3422623SN/A data_write_pkt->allocate(); 3432623SN/A data_write_pkt->set(data); 3442623SN/A 3452630SN/A if (!dcachePort.sendTiming(data_write_pkt)) { 3462623SN/A _status = DcacheRetry; 3472623SN/A dcache_pkt = data_write_pkt; 3482623SN/A } else { 3492623SN/A _status = DcacheWaitResponse; 3502623SN/A dcache_pkt = NULL; 3512623SN/A } 3522623SN/A } 3532623SN/A 3542623SN/A // This will need a new way to tell if it's hooked up to a cache or not. 3552623SN/A if (data_write_req->getFlags() & UNCACHEABLE) 3562623SN/A recordEvent("Uncached Write"); 3572623SN/A 3582623SN/A // If the write needs to have a fault on the access, consider calling 3592623SN/A // changeStatus() and changing it to "bad addr write" or something. 3602623SN/A return fault; 3612623SN/A} 3622623SN/A 3632623SN/A 3642623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3652623SN/Atemplate 3662623SN/AFault 3672623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 3682623SN/A unsigned flags, uint64_t *res); 3692623SN/A 3702623SN/Atemplate 3712623SN/AFault 3722623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 3732623SN/A unsigned flags, uint64_t *res); 3742623SN/A 3752623SN/Atemplate 3762623SN/AFault 3772623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 3782623SN/A unsigned flags, uint64_t *res); 3792623SN/A 3802623SN/Atemplate 3812623SN/AFault 3822623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 3832623SN/A unsigned flags, uint64_t *res); 3842623SN/A 3852623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3862623SN/A 3872623SN/Atemplate<> 3882623SN/AFault 3892623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 3902623SN/A{ 3912623SN/A return write(*(uint64_t*)&data, addr, flags, res); 3922623SN/A} 3932623SN/A 3942623SN/Atemplate<> 3952623SN/AFault 3962623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 3972623SN/A{ 3982623SN/A return write(*(uint32_t*)&data, addr, flags, res); 3992623SN/A} 4002623SN/A 4012623SN/A 4022623SN/Atemplate<> 4032623SN/AFault 4042623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 4052623SN/A{ 4062623SN/A return write((uint32_t)data, addr, flags, res); 4072623SN/A} 4082623SN/A 4092623SN/A 4102623SN/Avoid 4112623SN/ATimingSimpleCPU::fetch() 4122623SN/A{ 4132631SN/A checkForInterrupts(); 4142631SN/A 4152663Sstever@eecs.umich.edu // need to fill in CPU & thread IDs here 4162663Sstever@eecs.umich.edu Request *ifetch_req = new Request(); 4172835Srdreslin@umich.edu ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 4182662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 4192623SN/A 4202641Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 4212623SN/A ifetch_pkt->dataStatic(&inst); 4222623SN/A 4232623SN/A if (fault == NoFault) { 4242630SN/A if (!icachePort.sendTiming(ifetch_pkt)) { 4252623SN/A // Need to wait for retry 4262623SN/A _status = IcacheRetry; 4272623SN/A } else { 4282623SN/A // Need to wait for cache to respond 4292623SN/A _status = IcacheWaitResponse; 4302623SN/A // ownership of packet transferred to memory system 4312623SN/A ifetch_pkt = NULL; 4322623SN/A } 4332623SN/A } else { 4342644Sstever@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 4352644Sstever@eecs.umich.edu advanceInst(fault); 4362623SN/A } 4373222Sktlim@umich.edu 4383222Sktlim@umich.edu numCycles += curTick - previousTick; 4393222Sktlim@umich.edu previousTick = curTick; 4402623SN/A} 4412623SN/A 4422623SN/A 4432623SN/Avoid 4442644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 4452623SN/A{ 4462623SN/A advancePC(fault); 4472623SN/A 4482631SN/A if (_status == Running) { 4492631SN/A // kick off fetch of next instruction... callback from icache 4502631SN/A // response will cause that instruction to be executed, 4512631SN/A // keeping the CPU running. 4522631SN/A fetch(); 4532631SN/A } 4542623SN/A} 4552623SN/A 4562623SN/A 4572623SN/Avoid 4582644Sstever@eecs.umich.eduTimingSimpleCPU::completeIfetch(Packet *pkt) 4592623SN/A{ 4602623SN/A // received a response from the icache: execute the received 4612623SN/A // instruction 4622644Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 4632623SN/A assert(_status == IcacheWaitResponse); 4642798Sktlim@umich.edu 4652623SN/A _status = Running; 4662644Sstever@eecs.umich.edu 4672644Sstever@eecs.umich.edu delete pkt->req; 4682644Sstever@eecs.umich.edu delete pkt; 4692644Sstever@eecs.umich.edu 4703222Sktlim@umich.edu numCycles += curTick - previousTick; 4713222Sktlim@umich.edu previousTick = curTick; 4723222Sktlim@umich.edu 4732839Sktlim@umich.edu if (getState() == SimObject::Draining) { 4742839Sktlim@umich.edu completeDrain(); 4752798Sktlim@umich.edu return; 4762798Sktlim@umich.edu } 4772798Sktlim@umich.edu 4782623SN/A preExecute(); 4792644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 4802623SN/A // load or store: just send to dcache 4812623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 4822644Sstever@eecs.umich.edu if (fault == NoFault) { 4832644Sstever@eecs.umich.edu // successfully initiated access: instruction will 4842644Sstever@eecs.umich.edu // complete in dcache response callback 4852644Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse); 4862644Sstever@eecs.umich.edu } else { 4872644Sstever@eecs.umich.edu // fault: complete now to invoke fault handler 4882644Sstever@eecs.umich.edu postExecute(); 4892644Sstever@eecs.umich.edu advanceInst(fault); 4902644Sstever@eecs.umich.edu } 4912623SN/A } else { 4922623SN/A // non-memory instruction: execute completely now 4932623SN/A Fault fault = curStaticInst->execute(this, traceData); 4942644Sstever@eecs.umich.edu postExecute(); 4952644Sstever@eecs.umich.edu advanceInst(fault); 4962623SN/A } 4972623SN/A} 4982623SN/A 4992948Ssaidi@eecs.umich.eduvoid 5002948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 5012948Ssaidi@eecs.umich.edu{ 5022948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 5032948Ssaidi@eecs.umich.edu} 5042623SN/A 5052623SN/Abool 5062630SN/ATimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) 5072623SN/A{ 5082948Ssaidi@eecs.umich.edu // These next few lines could be replaced with something faster 5092948Ssaidi@eecs.umich.edu // who knows what though 5102948Ssaidi@eecs.umich.edu Tick time = pkt->req->getTime(); 5112948Ssaidi@eecs.umich.edu while (time < curTick) 5122948Ssaidi@eecs.umich.edu time += lat; 5132948Ssaidi@eecs.umich.edu 5142948Ssaidi@eecs.umich.edu if (time == curTick) 5152948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 5162948Ssaidi@eecs.umich.edu else 5172948Ssaidi@eecs.umich.edu tickEvent.schedule(pkt, time); 5182948Ssaidi@eecs.umich.edu 5192623SN/A return true; 5202623SN/A} 5212623SN/A 5222657Ssaidi@eecs.umich.eduvoid 5232623SN/ATimingSimpleCPU::IcachePort::recvRetry() 5242623SN/A{ 5252623SN/A // we shouldn't get a retry unless we have a packet that we're 5262623SN/A // waiting to transmit 5272623SN/A assert(cpu->ifetch_pkt != NULL); 5282623SN/A assert(cpu->_status == IcacheRetry); 5292623SN/A Packet *tmp = cpu->ifetch_pkt; 5302657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 5312657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 5322657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 5332657Ssaidi@eecs.umich.edu } 5342623SN/A} 5352623SN/A 5362623SN/Avoid 5372623SN/ATimingSimpleCPU::completeDataAccess(Packet *pkt) 5382623SN/A{ 5392623SN/A // received a response from the dcache: complete the load or store 5402623SN/A // instruction 5412641Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 5422623SN/A assert(_status == DcacheWaitResponse); 5432623SN/A _status = Running; 5442623SN/A 5453222Sktlim@umich.edu numCycles += curTick - previousTick; 5463222Sktlim@umich.edu previousTick = curTick; 5473222Sktlim@umich.edu 5482839Sktlim@umich.edu if (getState() == SimObject::Draining) { 5492839Sktlim@umich.edu completeDrain(); 5502798Sktlim@umich.edu 5512798Sktlim@umich.edu delete pkt->req; 5522798Sktlim@umich.edu delete pkt; 5532798Sktlim@umich.edu 5542798Sktlim@umich.edu return; 5552798Sktlim@umich.edu } 5562798Sktlim@umich.edu 5572623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 5582623SN/A 5592644Sstever@eecs.umich.edu delete pkt->req; 5602644Sstever@eecs.umich.edu delete pkt; 5612644Sstever@eecs.umich.edu 5622644Sstever@eecs.umich.edu postExecute(); 5632644Sstever@eecs.umich.edu advanceInst(fault); 5642623SN/A} 5652623SN/A 5662623SN/A 5672798Sktlim@umich.eduvoid 5682839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 5692798Sktlim@umich.edu{ 5702839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 5712901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 5722839Sktlim@umich.edu drainEvent->process(); 5732798Sktlim@umich.edu} 5742623SN/A 5752623SN/Abool 5762630SN/ATimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) 5772623SN/A{ 5782948Ssaidi@eecs.umich.edu Tick time = pkt->req->getTime(); 5792948Ssaidi@eecs.umich.edu while (time < curTick) 5802948Ssaidi@eecs.umich.edu time += lat; 5812948Ssaidi@eecs.umich.edu 5822948Ssaidi@eecs.umich.edu if (time == curTick) 5832948Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 5842948Ssaidi@eecs.umich.edu else 5852948Ssaidi@eecs.umich.edu tickEvent.schedule(pkt, time); 5862948Ssaidi@eecs.umich.edu 5872948Ssaidi@eecs.umich.edu return true; 5882948Ssaidi@eecs.umich.edu} 5892948Ssaidi@eecs.umich.edu 5902948Ssaidi@eecs.umich.eduvoid 5912948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 5922948Ssaidi@eecs.umich.edu{ 5932630SN/A cpu->completeDataAccess(pkt); 5942623SN/A} 5952623SN/A 5962657Ssaidi@eecs.umich.eduvoid 5972623SN/ATimingSimpleCPU::DcachePort::recvRetry() 5982623SN/A{ 5992623SN/A // we shouldn't get a retry unless we have a packet that we're 6002623SN/A // waiting to transmit 6012623SN/A assert(cpu->dcache_pkt != NULL); 6022623SN/A assert(cpu->_status == DcacheRetry); 6032623SN/A Packet *tmp = cpu->dcache_pkt; 6042657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 6052657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 6062657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 6072657Ssaidi@eecs.umich.edu } 6082623SN/A} 6092623SN/A 6102623SN/A 6112623SN/A//////////////////////////////////////////////////////////////////////// 6122623SN/A// 6132623SN/A// TimingSimpleCPU Simulation Object 6142623SN/A// 6152623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6162623SN/A 6172623SN/A Param<Counter> max_insts_any_thread; 6182623SN/A Param<Counter> max_insts_all_threads; 6192623SN/A Param<Counter> max_loads_any_thread; 6202623SN/A Param<Counter> max_loads_all_threads; 6213119Sktlim@umich.edu Param<Tick> progress_interval; 6222623SN/A SimObjectParam<MemObject *> mem; 6232901Ssaidi@eecs.umich.edu SimObjectParam<System *> system; 6242623SN/A 6252623SN/A#if FULL_SYSTEM 6262623SN/A SimObjectParam<AlphaITB *> itb; 6272623SN/A SimObjectParam<AlphaDTB *> dtb; 6282623SN/A Param<int> cpu_id; 6292623SN/A Param<Tick> profile; 6302623SN/A#else 6312623SN/A SimObjectParam<Process *> workload; 6322623SN/A#endif // FULL_SYSTEM 6332623SN/A 6342623SN/A Param<int> clock; 6352623SN/A 6362623SN/A Param<bool> defer_registration; 6372623SN/A Param<int> width; 6382623SN/A Param<bool> function_trace; 6392623SN/A Param<Tick> function_trace_start; 6402623SN/A Param<bool> simulate_stalls; 6412623SN/A 6422623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6432623SN/A 6442623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6452623SN/A 6462623SN/A INIT_PARAM(max_insts_any_thread, 6472623SN/A "terminate when any thread reaches this inst count"), 6482623SN/A INIT_PARAM(max_insts_all_threads, 6492623SN/A "terminate when all threads have reached this inst count"), 6502623SN/A INIT_PARAM(max_loads_any_thread, 6512623SN/A "terminate when any thread reaches this load count"), 6522623SN/A INIT_PARAM(max_loads_all_threads, 6532623SN/A "terminate when all threads have reached this load count"), 6543119Sktlim@umich.edu INIT_PARAM(progress_interval, "Progress interval"), 6552623SN/A INIT_PARAM(mem, "memory"), 6562901Ssaidi@eecs.umich.edu INIT_PARAM(system, "system object"), 6572623SN/A 6582623SN/A#if FULL_SYSTEM 6592623SN/A INIT_PARAM(itb, "Instruction TLB"), 6602623SN/A INIT_PARAM(dtb, "Data TLB"), 6612623SN/A INIT_PARAM(cpu_id, "processor ID"), 6622623SN/A INIT_PARAM(profile, ""), 6632623SN/A#else 6642623SN/A INIT_PARAM(workload, "processes to run"), 6652623SN/A#endif // FULL_SYSTEM 6662623SN/A 6672623SN/A INIT_PARAM(clock, "clock speed"), 6682623SN/A INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 6692623SN/A INIT_PARAM(width, "cpu width"), 6702623SN/A INIT_PARAM(function_trace, "Enable function trace"), 6712623SN/A INIT_PARAM(function_trace_start, "Cycle to start function trace"), 6722623SN/A INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 6732623SN/A 6742623SN/AEND_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6752623SN/A 6762623SN/A 6772623SN/ACREATE_SIM_OBJECT(TimingSimpleCPU) 6782623SN/A{ 6792623SN/A TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 6802623SN/A params->name = getInstanceName(); 6812623SN/A params->numberOfThreads = 1; 6822623SN/A params->max_insts_any_thread = max_insts_any_thread; 6832623SN/A params->max_insts_all_threads = max_insts_all_threads; 6842623SN/A params->max_loads_any_thread = max_loads_any_thread; 6852623SN/A params->max_loads_all_threads = max_loads_all_threads; 6863119Sktlim@umich.edu params->progress_interval = progress_interval; 6872623SN/A params->deferRegistration = defer_registration; 6882623SN/A params->clock = clock; 6892623SN/A params->functionTrace = function_trace; 6902623SN/A params->functionTraceStart = function_trace_start; 6912623SN/A params->mem = mem; 6922901Ssaidi@eecs.umich.edu params->system = system; 6932623SN/A 6942623SN/A#if FULL_SYSTEM 6952623SN/A params->itb = itb; 6962623SN/A params->dtb = dtb; 6972623SN/A params->cpu_id = cpu_id; 6982623SN/A params->profile = profile; 6992623SN/A#else 7002623SN/A params->process = workload; 7012623SN/A#endif 7022623SN/A 7032623SN/A TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 7042623SN/A return cpu; 7052623SN/A} 7062623SN/A 7072623SN/AREGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 7082623SN/A 709