timing.cc revision 2901
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 312623SN/A#include "arch/utility.hh" 322623SN/A#include "cpu/exetrace.hh" 332623SN/A#include "cpu/simple/timing.hh" 342623SN/A#include "mem/packet_impl.hh" 352623SN/A#include "sim/builder.hh" 362901Ssaidi@eecs.umich.edu#include "sim/system.hh" 372623SN/A 382623SN/Ausing namespace std; 392623SN/Ausing namespace TheISA; 402623SN/A 412856Srdreslin@umich.eduPort * 422856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 432856Srdreslin@umich.edu{ 442856Srdreslin@umich.edu if (if_name == "dcache_port") 452856Srdreslin@umich.edu return &dcachePort; 462856Srdreslin@umich.edu else if (if_name == "icache_port") 472856Srdreslin@umich.edu return &icachePort; 482856Srdreslin@umich.edu else 492856Srdreslin@umich.edu panic("No Such Port\n"); 502856Srdreslin@umich.edu} 512623SN/A 522623SN/Avoid 532623SN/ATimingSimpleCPU::init() 542623SN/A{ 552623SN/A BaseCPU::init(); 562623SN/A#if FULL_SYSTEM 572680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 582680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 592623SN/A 602623SN/A // initialize CPU, including PC 612680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 622623SN/A } 632623SN/A#endif 642623SN/A} 652623SN/A 662623SN/ATick 672630SN/ATimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt) 682623SN/A{ 692623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 702623SN/A return curTick; 712623SN/A} 722623SN/A 732623SN/Avoid 742630SN/ATimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt) 752623SN/A{ 762623SN/A panic("TimingSimpleCPU doesn't expect recvFunctional callback!"); 772623SN/A} 782623SN/A 792623SN/Avoid 802623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 812623SN/A{ 822631SN/A if (status == RangeChange) 832631SN/A return; 842631SN/A 852623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 862623SN/A} 872623SN/A 882623SN/ATimingSimpleCPU::TimingSimpleCPU(Params *p) 892623SN/A : BaseSimpleCPU(p), icachePort(this), dcachePort(this) 902623SN/A{ 912623SN/A _status = Idle; 922623SN/A ifetch_pkt = dcache_pkt = NULL; 932839Sktlim@umich.edu drainEvent = NULL; 942867Sktlim@umich.edu fetchEvent = NULL; 952901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 962623SN/A} 972623SN/A 982623SN/A 992623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1002623SN/A{ 1012623SN/A} 1022623SN/A 1032623SN/Avoid 1042623SN/ATimingSimpleCPU::serialize(ostream &os) 1052623SN/A{ 1062798Sktlim@umich.edu SERIALIZE_ENUM(_status); 1072623SN/A BaseSimpleCPU::serialize(os); 1082623SN/A} 1092623SN/A 1102623SN/Avoid 1112623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1122623SN/A{ 1132798Sktlim@umich.edu UNSERIALIZE_ENUM(_status); 1142623SN/A BaseSimpleCPU::unserialize(cp, section); 1152798Sktlim@umich.edu} 1162798Sktlim@umich.edu 1172901Ssaidi@eecs.umich.eduunsigned int 1182839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1192798Sktlim@umich.edu{ 1202839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1212798Sktlim@umich.edu // an access to complete. 1222798Sktlim@umich.edu if (status() == Idle || status() == Running || status() == SwitchedOut) { 1232901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1242901Ssaidi@eecs.umich.edu return 0; 1252798Sktlim@umich.edu } else { 1262839Sktlim@umich.edu changeState(SimObject::Draining); 1272839Sktlim@umich.edu drainEvent = drain_event; 1282901Ssaidi@eecs.umich.edu return 1; 1292798Sktlim@umich.edu } 1302623SN/A} 1312623SN/A 1322623SN/Avoid 1332798Sktlim@umich.eduTimingSimpleCPU::resume() 1342623SN/A{ 1352798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1362867Sktlim@umich.edu // Delete the old event if it existed. 1372867Sktlim@umich.edu if (fetchEvent) { 1382867Sktlim@umich.edu assert(!fetchEvent->scheduled()); 1392867Sktlim@umich.edu delete fetchEvent; 1402867Sktlim@umich.edu } 1412867Sktlim@umich.edu 1422867Sktlim@umich.edu fetchEvent = 1432867Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 1442867Sktlim@umich.edu fetchEvent->schedule(curTick); 1452623SN/A } 1462798Sktlim@umich.edu 1472901Ssaidi@eecs.umich.edu assert(system->getMemoryMode() == System::Timing); 1482901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1492798Sktlim@umich.edu} 1502798Sktlim@umich.edu 1512798Sktlim@umich.eduvoid 1522798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1532798Sktlim@umich.edu{ 1542798Sktlim@umich.edu assert(status() == Running || status() == Idle); 1552798Sktlim@umich.edu _status = SwitchedOut; 1562867Sktlim@umich.edu 1572867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1582867Sktlim@umich.edu // we'll need to cancel it. 1592867Sktlim@umich.edu if (fetchEvent && fetchEvent->scheduled()) 1602867Sktlim@umich.edu fetchEvent->deschedule(); 1612623SN/A} 1622623SN/A 1632623SN/A 1642623SN/Avoid 1652623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1662623SN/A{ 1672623SN/A BaseCPU::takeOverFrom(oldCPU); 1682623SN/A 1692680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1702623SN/A // running and schedule its tick event. 1712680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1722680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1732680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 1742623SN/A _status = Running; 1752623SN/A break; 1762623SN/A } 1772623SN/A } 1782623SN/A} 1792623SN/A 1802623SN/A 1812623SN/Avoid 1822623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 1832623SN/A{ 1842623SN/A assert(thread_num == 0); 1852683Sktlim@umich.edu assert(thread); 1862623SN/A 1872623SN/A assert(_status == Idle); 1882623SN/A 1892623SN/A notIdleFraction++; 1902623SN/A _status = Running; 1912623SN/A // kick things off by initiating the fetch of the next instruction 1922867Sktlim@umich.edu fetchEvent = 1932867Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 1942867Sktlim@umich.edu fetchEvent->schedule(curTick + cycles(delay)); 1952623SN/A} 1962623SN/A 1972623SN/A 1982623SN/Avoid 1992623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2002623SN/A{ 2012623SN/A assert(thread_num == 0); 2022683Sktlim@umich.edu assert(thread); 2032623SN/A 2042644Sstever@eecs.umich.edu assert(_status == Running); 2052623SN/A 2062644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2072644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2082623SN/A 2092623SN/A notIdleFraction--; 2102623SN/A _status = Idle; 2112623SN/A} 2122623SN/A 2132623SN/A 2142623SN/Atemplate <class T> 2152623SN/AFault 2162623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2172623SN/A{ 2182663Sstever@eecs.umich.edu // need to fill in CPU & thread IDs here 2192663Sstever@eecs.umich.edu Request *data_read_req = new Request(); 2202835Srdreslin@umich.edu data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 2212683Sktlim@umich.edu data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 2222623SN/A 2232623SN/A if (traceData) { 2242623SN/A traceData->setAddr(data_read_req->getVaddr()); 2252623SN/A } 2262623SN/A 2272623SN/A // translate to physical address 2282683Sktlim@umich.edu Fault fault = thread->translateDataReadReq(data_read_req); 2292623SN/A 2302623SN/A // Now do the access. 2312623SN/A if (fault == NoFault) { 2322641Sstever@eecs.umich.edu Packet *data_read_pkt = 2332641Sstever@eecs.umich.edu new Packet(data_read_req, Packet::ReadReq, Packet::Broadcast); 2342623SN/A data_read_pkt->dataDynamic<T>(new T); 2352623SN/A 2362630SN/A if (!dcachePort.sendTiming(data_read_pkt)) { 2372623SN/A _status = DcacheRetry; 2382623SN/A dcache_pkt = data_read_pkt; 2392623SN/A } else { 2402623SN/A _status = DcacheWaitResponse; 2412623SN/A dcache_pkt = NULL; 2422623SN/A } 2432623SN/A } 2442623SN/A 2452623SN/A // This will need a new way to tell if it has a dcache attached. 2462623SN/A if (data_read_req->getFlags() & UNCACHEABLE) 2472623SN/A recordEvent("Uncached Read"); 2482623SN/A 2492623SN/A return fault; 2502623SN/A} 2512623SN/A 2522623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 2532623SN/A 2542623SN/Atemplate 2552623SN/AFault 2562623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 2572623SN/A 2582623SN/Atemplate 2592623SN/AFault 2602623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 2612623SN/A 2622623SN/Atemplate 2632623SN/AFault 2642623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 2652623SN/A 2662623SN/Atemplate 2672623SN/AFault 2682623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 2692623SN/A 2702623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 2712623SN/A 2722623SN/Atemplate<> 2732623SN/AFault 2742623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 2752623SN/A{ 2762623SN/A return read(addr, *(uint64_t*)&data, flags); 2772623SN/A} 2782623SN/A 2792623SN/Atemplate<> 2802623SN/AFault 2812623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 2822623SN/A{ 2832623SN/A return read(addr, *(uint32_t*)&data, flags); 2842623SN/A} 2852623SN/A 2862623SN/A 2872623SN/Atemplate<> 2882623SN/AFault 2892623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 2902623SN/A{ 2912623SN/A return read(addr, (uint32_t&)data, flags); 2922623SN/A} 2932623SN/A 2942623SN/A 2952623SN/Atemplate <class T> 2962623SN/AFault 2972623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 2982623SN/A{ 2992663Sstever@eecs.umich.edu // need to fill in CPU & thread IDs here 3002663Sstever@eecs.umich.edu Request *data_write_req = new Request(); 3012835Srdreslin@umich.edu data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 3022683Sktlim@umich.edu data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 3032623SN/A 3042623SN/A // translate to physical address 3052683Sktlim@umich.edu Fault fault = thread->translateDataWriteReq(data_write_req); 3062623SN/A // Now do the access. 3072623SN/A if (fault == NoFault) { 3082641Sstever@eecs.umich.edu Packet *data_write_pkt = 3092641Sstever@eecs.umich.edu new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast); 3102623SN/A data_write_pkt->allocate(); 3112623SN/A data_write_pkt->set(data); 3122623SN/A 3132630SN/A if (!dcachePort.sendTiming(data_write_pkt)) { 3142623SN/A _status = DcacheRetry; 3152623SN/A dcache_pkt = data_write_pkt; 3162623SN/A } else { 3172623SN/A _status = DcacheWaitResponse; 3182623SN/A dcache_pkt = NULL; 3192623SN/A } 3202623SN/A } 3212623SN/A 3222623SN/A // This will need a new way to tell if it's hooked up to a cache or not. 3232623SN/A if (data_write_req->getFlags() & UNCACHEABLE) 3242623SN/A recordEvent("Uncached Write"); 3252623SN/A 3262623SN/A // If the write needs to have a fault on the access, consider calling 3272623SN/A // changeStatus() and changing it to "bad addr write" or something. 3282623SN/A return fault; 3292623SN/A} 3302623SN/A 3312623SN/A 3322623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3332623SN/Atemplate 3342623SN/AFault 3352623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 3362623SN/A unsigned flags, uint64_t *res); 3372623SN/A 3382623SN/Atemplate 3392623SN/AFault 3402623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 3412623SN/A unsigned flags, uint64_t *res); 3422623SN/A 3432623SN/Atemplate 3442623SN/AFault 3452623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 3462623SN/A unsigned flags, uint64_t *res); 3472623SN/A 3482623SN/Atemplate 3492623SN/AFault 3502623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 3512623SN/A unsigned flags, uint64_t *res); 3522623SN/A 3532623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3542623SN/A 3552623SN/Atemplate<> 3562623SN/AFault 3572623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 3582623SN/A{ 3592623SN/A return write(*(uint64_t*)&data, addr, flags, res); 3602623SN/A} 3612623SN/A 3622623SN/Atemplate<> 3632623SN/AFault 3642623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 3652623SN/A{ 3662623SN/A return write(*(uint32_t*)&data, addr, flags, res); 3672623SN/A} 3682623SN/A 3692623SN/A 3702623SN/Atemplate<> 3712623SN/AFault 3722623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 3732623SN/A{ 3742623SN/A return write((uint32_t)data, addr, flags, res); 3752623SN/A} 3762623SN/A 3772623SN/A 3782623SN/Avoid 3792623SN/ATimingSimpleCPU::fetch() 3802623SN/A{ 3812631SN/A checkForInterrupts(); 3822631SN/A 3832663Sstever@eecs.umich.edu // need to fill in CPU & thread IDs here 3842663Sstever@eecs.umich.edu Request *ifetch_req = new Request(); 3852835Srdreslin@umich.edu ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 3862662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 3872623SN/A 3882641Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 3892623SN/A ifetch_pkt->dataStatic(&inst); 3902623SN/A 3912623SN/A if (fault == NoFault) { 3922630SN/A if (!icachePort.sendTiming(ifetch_pkt)) { 3932623SN/A // Need to wait for retry 3942623SN/A _status = IcacheRetry; 3952623SN/A } else { 3962623SN/A // Need to wait for cache to respond 3972623SN/A _status = IcacheWaitResponse; 3982623SN/A // ownership of packet transferred to memory system 3992623SN/A ifetch_pkt = NULL; 4002623SN/A } 4012623SN/A } else { 4022644Sstever@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 4032644Sstever@eecs.umich.edu advanceInst(fault); 4042623SN/A } 4052623SN/A} 4062623SN/A 4072623SN/A 4082623SN/Avoid 4092644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 4102623SN/A{ 4112623SN/A advancePC(fault); 4122623SN/A 4132631SN/A if (_status == Running) { 4142631SN/A // kick off fetch of next instruction... callback from icache 4152631SN/A // response will cause that instruction to be executed, 4162631SN/A // keeping the CPU running. 4172631SN/A fetch(); 4182631SN/A } 4192623SN/A} 4202623SN/A 4212623SN/A 4222623SN/Avoid 4232644Sstever@eecs.umich.eduTimingSimpleCPU::completeIfetch(Packet *pkt) 4242623SN/A{ 4252623SN/A // received a response from the icache: execute the received 4262623SN/A // instruction 4272644Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 4282623SN/A assert(_status == IcacheWaitResponse); 4292798Sktlim@umich.edu 4302623SN/A _status = Running; 4312644Sstever@eecs.umich.edu 4322644Sstever@eecs.umich.edu delete pkt->req; 4332644Sstever@eecs.umich.edu delete pkt; 4342644Sstever@eecs.umich.edu 4352839Sktlim@umich.edu if (getState() == SimObject::Draining) { 4362839Sktlim@umich.edu completeDrain(); 4372798Sktlim@umich.edu return; 4382798Sktlim@umich.edu } 4392798Sktlim@umich.edu 4402623SN/A preExecute(); 4412644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 4422623SN/A // load or store: just send to dcache 4432623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 4442644Sstever@eecs.umich.edu if (fault == NoFault) { 4452644Sstever@eecs.umich.edu // successfully initiated access: instruction will 4462644Sstever@eecs.umich.edu // complete in dcache response callback 4472644Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse); 4482644Sstever@eecs.umich.edu } else { 4492644Sstever@eecs.umich.edu // fault: complete now to invoke fault handler 4502644Sstever@eecs.umich.edu postExecute(); 4512644Sstever@eecs.umich.edu advanceInst(fault); 4522644Sstever@eecs.umich.edu } 4532623SN/A } else { 4542623SN/A // non-memory instruction: execute completely now 4552623SN/A Fault fault = curStaticInst->execute(this, traceData); 4562644Sstever@eecs.umich.edu postExecute(); 4572644Sstever@eecs.umich.edu advanceInst(fault); 4582623SN/A } 4592623SN/A} 4602623SN/A 4612623SN/A 4622623SN/Abool 4632630SN/ATimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) 4642623SN/A{ 4652857Srdreslin@umich.edu cpu->completeIfetch(pkt); 4662623SN/A return true; 4672623SN/A} 4682623SN/A 4692657Ssaidi@eecs.umich.eduvoid 4702623SN/ATimingSimpleCPU::IcachePort::recvRetry() 4712623SN/A{ 4722623SN/A // we shouldn't get a retry unless we have a packet that we're 4732623SN/A // waiting to transmit 4742623SN/A assert(cpu->ifetch_pkt != NULL); 4752623SN/A assert(cpu->_status == IcacheRetry); 4762623SN/A Packet *tmp = cpu->ifetch_pkt; 4772657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 4782657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 4792657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 4802657Ssaidi@eecs.umich.edu } 4812623SN/A} 4822623SN/A 4832623SN/Avoid 4842623SN/ATimingSimpleCPU::completeDataAccess(Packet *pkt) 4852623SN/A{ 4862623SN/A // received a response from the dcache: complete the load or store 4872623SN/A // instruction 4882641Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 4892623SN/A assert(_status == DcacheWaitResponse); 4902623SN/A _status = Running; 4912623SN/A 4922839Sktlim@umich.edu if (getState() == SimObject::Draining) { 4932839Sktlim@umich.edu completeDrain(); 4942798Sktlim@umich.edu 4952798Sktlim@umich.edu delete pkt->req; 4962798Sktlim@umich.edu delete pkt; 4972798Sktlim@umich.edu 4982798Sktlim@umich.edu return; 4992798Sktlim@umich.edu } 5002798Sktlim@umich.edu 5012623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 5022623SN/A 5032644Sstever@eecs.umich.edu delete pkt->req; 5042644Sstever@eecs.umich.edu delete pkt; 5052644Sstever@eecs.umich.edu 5062644Sstever@eecs.umich.edu postExecute(); 5072644Sstever@eecs.umich.edu advanceInst(fault); 5082623SN/A} 5092623SN/A 5102623SN/A 5112798Sktlim@umich.eduvoid 5122839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 5132798Sktlim@umich.edu{ 5142839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 5152901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 5162839Sktlim@umich.edu drainEvent->process(); 5172798Sktlim@umich.edu} 5182623SN/A 5192623SN/Abool 5202630SN/ATimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) 5212623SN/A{ 5222630SN/A cpu->completeDataAccess(pkt); 5232623SN/A return true; 5242623SN/A} 5252623SN/A 5262657Ssaidi@eecs.umich.eduvoid 5272623SN/ATimingSimpleCPU::DcachePort::recvRetry() 5282623SN/A{ 5292623SN/A // we shouldn't get a retry unless we have a packet that we're 5302623SN/A // waiting to transmit 5312623SN/A assert(cpu->dcache_pkt != NULL); 5322623SN/A assert(cpu->_status == DcacheRetry); 5332623SN/A Packet *tmp = cpu->dcache_pkt; 5342657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 5352657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 5362657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 5372657Ssaidi@eecs.umich.edu } 5382623SN/A} 5392623SN/A 5402623SN/A 5412623SN/A//////////////////////////////////////////////////////////////////////// 5422623SN/A// 5432623SN/A// TimingSimpleCPU Simulation Object 5442623SN/A// 5452623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 5462623SN/A 5472623SN/A Param<Counter> max_insts_any_thread; 5482623SN/A Param<Counter> max_insts_all_threads; 5492623SN/A Param<Counter> max_loads_any_thread; 5502623SN/A Param<Counter> max_loads_all_threads; 5512623SN/A SimObjectParam<MemObject *> mem; 5522901Ssaidi@eecs.umich.edu SimObjectParam<System *> system; 5532623SN/A 5542623SN/A#if FULL_SYSTEM 5552623SN/A SimObjectParam<AlphaITB *> itb; 5562623SN/A SimObjectParam<AlphaDTB *> dtb; 5572623SN/A Param<int> cpu_id; 5582623SN/A Param<Tick> profile; 5592623SN/A#else 5602623SN/A SimObjectParam<Process *> workload; 5612623SN/A#endif // FULL_SYSTEM 5622623SN/A 5632623SN/A Param<int> clock; 5642623SN/A 5652623SN/A Param<bool> defer_registration; 5662623SN/A Param<int> width; 5672623SN/A Param<bool> function_trace; 5682623SN/A Param<Tick> function_trace_start; 5692623SN/A Param<bool> simulate_stalls; 5702623SN/A 5712623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 5722623SN/A 5732623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 5742623SN/A 5752623SN/A INIT_PARAM(max_insts_any_thread, 5762623SN/A "terminate when any thread reaches this inst count"), 5772623SN/A INIT_PARAM(max_insts_all_threads, 5782623SN/A "terminate when all threads have reached this inst count"), 5792623SN/A INIT_PARAM(max_loads_any_thread, 5802623SN/A "terminate when any thread reaches this load count"), 5812623SN/A INIT_PARAM(max_loads_all_threads, 5822623SN/A "terminate when all threads have reached this load count"), 5832623SN/A INIT_PARAM(mem, "memory"), 5842901Ssaidi@eecs.umich.edu INIT_PARAM(system, "system object"), 5852623SN/A 5862623SN/A#if FULL_SYSTEM 5872623SN/A INIT_PARAM(itb, "Instruction TLB"), 5882623SN/A INIT_PARAM(dtb, "Data TLB"), 5892623SN/A INIT_PARAM(cpu_id, "processor ID"), 5902623SN/A INIT_PARAM(profile, ""), 5912623SN/A#else 5922623SN/A INIT_PARAM(workload, "processes to run"), 5932623SN/A#endif // FULL_SYSTEM 5942623SN/A 5952623SN/A INIT_PARAM(clock, "clock speed"), 5962623SN/A INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 5972623SN/A INIT_PARAM(width, "cpu width"), 5982623SN/A INIT_PARAM(function_trace, "Enable function trace"), 5992623SN/A INIT_PARAM(function_trace_start, "Cycle to start function trace"), 6002623SN/A INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 6012623SN/A 6022623SN/AEND_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6032623SN/A 6042623SN/A 6052623SN/ACREATE_SIM_OBJECT(TimingSimpleCPU) 6062623SN/A{ 6072623SN/A TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 6082623SN/A params->name = getInstanceName(); 6092623SN/A params->numberOfThreads = 1; 6102623SN/A params->max_insts_any_thread = max_insts_any_thread; 6112623SN/A params->max_insts_all_threads = max_insts_all_threads; 6122623SN/A params->max_loads_any_thread = max_loads_any_thread; 6132623SN/A params->max_loads_all_threads = max_loads_all_threads; 6142623SN/A params->deferRegistration = defer_registration; 6152623SN/A params->clock = clock; 6162623SN/A params->functionTrace = function_trace; 6172623SN/A params->functionTraceStart = function_trace_start; 6182623SN/A params->mem = mem; 6192901Ssaidi@eecs.umich.edu params->system = system; 6202623SN/A 6212623SN/A#if FULL_SYSTEM 6222623SN/A params->itb = itb; 6232623SN/A params->dtb = dtb; 6242623SN/A params->cpu_id = cpu_id; 6252623SN/A params->profile = profile; 6262623SN/A#else 6272623SN/A params->process = workload; 6282623SN/A#endif 6292623SN/A 6302623SN/A TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 6312623SN/A return cpu; 6322623SN/A} 6332623SN/A 6342623SN/AREGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 6352623SN/A 636