timing.cc revision 2856
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 312623SN/A#include "arch/utility.hh" 322623SN/A#include "cpu/exetrace.hh" 332623SN/A#include "cpu/simple/timing.hh" 342623SN/A#include "mem/packet_impl.hh" 352623SN/A#include "sim/builder.hh" 362623SN/A 372623SN/Ausing namespace std; 382623SN/Ausing namespace TheISA; 392623SN/A 402856Srdreslin@umich.eduPort * 412856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 422856Srdreslin@umich.edu{ 432856Srdreslin@umich.edu if (if_name == "dcache_port") 442856Srdreslin@umich.edu return &dcachePort; 452856Srdreslin@umich.edu else if (if_name == "icache_port") 462856Srdreslin@umich.edu return &icachePort; 472856Srdreslin@umich.edu else 482856Srdreslin@umich.edu panic("No Such Port\n"); 492856Srdreslin@umich.edu} 502623SN/A 512623SN/Avoid 522623SN/ATimingSimpleCPU::init() 532623SN/A{ 542623SN/A BaseCPU::init(); 552623SN/A#if FULL_SYSTEM 562680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 572680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 582623SN/A 592623SN/A // initialize CPU, including PC 602680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 612623SN/A } 622623SN/A#endif 632623SN/A} 642623SN/A 652623SN/ATick 662630SN/ATimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt) 672623SN/A{ 682623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 692623SN/A return curTick; 702623SN/A} 712623SN/A 722623SN/Avoid 732630SN/ATimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt) 742623SN/A{ 752623SN/A panic("TimingSimpleCPU doesn't expect recvFunctional callback!"); 762623SN/A} 772623SN/A 782623SN/Avoid 792623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 802623SN/A{ 812631SN/A if (status == RangeChange) 822631SN/A return; 832631SN/A 842623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 852623SN/A} 862623SN/A 872623SN/ATimingSimpleCPU::TimingSimpleCPU(Params *p) 882623SN/A : BaseSimpleCPU(p), icachePort(this), dcachePort(this) 892623SN/A{ 902623SN/A _status = Idle; 912623SN/A ifetch_pkt = dcache_pkt = NULL; 922839Sktlim@umich.edu drainEvent = NULL; 932798Sktlim@umich.edu state = SimObject::Timing; 942623SN/A} 952623SN/A 962623SN/A 972623SN/ATimingSimpleCPU::~TimingSimpleCPU() 982623SN/A{ 992623SN/A} 1002623SN/A 1012623SN/Avoid 1022623SN/ATimingSimpleCPU::serialize(ostream &os) 1032623SN/A{ 1042798Sktlim@umich.edu SERIALIZE_ENUM(_status); 1052623SN/A BaseSimpleCPU::serialize(os); 1062623SN/A} 1072623SN/A 1082623SN/Avoid 1092623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1102623SN/A{ 1112798Sktlim@umich.edu UNSERIALIZE_ENUM(_status); 1122623SN/A BaseSimpleCPU::unserialize(cp, section); 1132798Sktlim@umich.edu} 1142798Sktlim@umich.edu 1152798Sktlim@umich.edubool 1162839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1172798Sktlim@umich.edu{ 1182839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1192798Sktlim@umich.edu // an access to complete. 1202798Sktlim@umich.edu if (status() == Idle || status() == Running || status() == SwitchedOut) { 1212839Sktlim@umich.edu changeState(SimObject::DrainedTiming); 1222798Sktlim@umich.edu return false; 1232798Sktlim@umich.edu } else { 1242839Sktlim@umich.edu changeState(SimObject::Draining); 1252839Sktlim@umich.edu drainEvent = drain_event; 1262798Sktlim@umich.edu return true; 1272798Sktlim@umich.edu } 1282623SN/A} 1292623SN/A 1302623SN/Avoid 1312798Sktlim@umich.eduTimingSimpleCPU::resume() 1322623SN/A{ 1332798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1342798Sktlim@umich.edu Event *e = 1352798Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, true); 1362798Sktlim@umich.edu e->schedule(curTick); 1372623SN/A } 1382798Sktlim@umich.edu} 1392798Sktlim@umich.edu 1402798Sktlim@umich.eduvoid 1412798Sktlim@umich.eduTimingSimpleCPU::setMemoryMode(State new_mode) 1422798Sktlim@umich.edu{ 1432798Sktlim@umich.edu assert(new_mode == SimObject::Timing); 1442798Sktlim@umich.edu} 1452798Sktlim@umich.edu 1462798Sktlim@umich.eduvoid 1472798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1482798Sktlim@umich.edu{ 1492798Sktlim@umich.edu assert(status() == Running || status() == Idle); 1502798Sktlim@umich.edu _status = SwitchedOut; 1512623SN/A} 1522623SN/A 1532623SN/A 1542623SN/Avoid 1552623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1562623SN/A{ 1572623SN/A BaseCPU::takeOverFrom(oldCPU); 1582623SN/A 1592680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1602623SN/A // running and schedule its tick event. 1612680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1622680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1632680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 1642623SN/A _status = Running; 1652623SN/A break; 1662623SN/A } 1672623SN/A } 1682623SN/A} 1692623SN/A 1702623SN/A 1712623SN/Avoid 1722623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 1732623SN/A{ 1742623SN/A assert(thread_num == 0); 1752683Sktlim@umich.edu assert(thread); 1762623SN/A 1772623SN/A assert(_status == Idle); 1782623SN/A 1792623SN/A notIdleFraction++; 1802623SN/A _status = Running; 1812623SN/A // kick things off by initiating the fetch of the next instruction 1822623SN/A Event *e = 1832623SN/A new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, true); 1842623SN/A e->schedule(curTick + cycles(delay)); 1852623SN/A} 1862623SN/A 1872623SN/A 1882623SN/Avoid 1892623SN/ATimingSimpleCPU::suspendContext(int thread_num) 1902623SN/A{ 1912623SN/A assert(thread_num == 0); 1922683Sktlim@umich.edu assert(thread); 1932623SN/A 1942644Sstever@eecs.umich.edu assert(_status == Running); 1952623SN/A 1962644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 1972644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 1982623SN/A 1992623SN/A notIdleFraction--; 2002623SN/A _status = Idle; 2012623SN/A} 2022623SN/A 2032623SN/A 2042623SN/Atemplate <class T> 2052623SN/AFault 2062623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2072623SN/A{ 2082663Sstever@eecs.umich.edu // need to fill in CPU & thread IDs here 2092663Sstever@eecs.umich.edu Request *data_read_req = new Request(); 2102835Srdreslin@umich.edu data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 2112683Sktlim@umich.edu data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 2122623SN/A 2132623SN/A if (traceData) { 2142623SN/A traceData->setAddr(data_read_req->getVaddr()); 2152623SN/A } 2162623SN/A 2172623SN/A // translate to physical address 2182683Sktlim@umich.edu Fault fault = thread->translateDataReadReq(data_read_req); 2192623SN/A 2202623SN/A // Now do the access. 2212623SN/A if (fault == NoFault) { 2222641Sstever@eecs.umich.edu Packet *data_read_pkt = 2232641Sstever@eecs.umich.edu new Packet(data_read_req, Packet::ReadReq, Packet::Broadcast); 2242623SN/A data_read_pkt->dataDynamic<T>(new T); 2252623SN/A 2262630SN/A if (!dcachePort.sendTiming(data_read_pkt)) { 2272623SN/A _status = DcacheRetry; 2282623SN/A dcache_pkt = data_read_pkt; 2292623SN/A } else { 2302623SN/A _status = DcacheWaitResponse; 2312623SN/A dcache_pkt = NULL; 2322623SN/A } 2332623SN/A } 2342623SN/A 2352623SN/A // This will need a new way to tell if it has a dcache attached. 2362623SN/A if (data_read_req->getFlags() & UNCACHEABLE) 2372623SN/A recordEvent("Uncached Read"); 2382623SN/A 2392623SN/A return fault; 2402623SN/A} 2412623SN/A 2422623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 2432623SN/A 2442623SN/Atemplate 2452623SN/AFault 2462623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 2472623SN/A 2482623SN/Atemplate 2492623SN/AFault 2502623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 2512623SN/A 2522623SN/Atemplate 2532623SN/AFault 2542623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 2552623SN/A 2562623SN/Atemplate 2572623SN/AFault 2582623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 2592623SN/A 2602623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 2612623SN/A 2622623SN/Atemplate<> 2632623SN/AFault 2642623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 2652623SN/A{ 2662623SN/A return read(addr, *(uint64_t*)&data, flags); 2672623SN/A} 2682623SN/A 2692623SN/Atemplate<> 2702623SN/AFault 2712623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 2722623SN/A{ 2732623SN/A return read(addr, *(uint32_t*)&data, flags); 2742623SN/A} 2752623SN/A 2762623SN/A 2772623SN/Atemplate<> 2782623SN/AFault 2792623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 2802623SN/A{ 2812623SN/A return read(addr, (uint32_t&)data, flags); 2822623SN/A} 2832623SN/A 2842623SN/A 2852623SN/Atemplate <class T> 2862623SN/AFault 2872623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 2882623SN/A{ 2892663Sstever@eecs.umich.edu // need to fill in CPU & thread IDs here 2902663Sstever@eecs.umich.edu Request *data_write_req = new Request(); 2912835Srdreslin@umich.edu data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 2922683Sktlim@umich.edu data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 2932623SN/A 2942623SN/A // translate to physical address 2952683Sktlim@umich.edu Fault fault = thread->translateDataWriteReq(data_write_req); 2962623SN/A // Now do the access. 2972623SN/A if (fault == NoFault) { 2982641Sstever@eecs.umich.edu Packet *data_write_pkt = 2992641Sstever@eecs.umich.edu new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast); 3002623SN/A data_write_pkt->allocate(); 3012623SN/A data_write_pkt->set(data); 3022623SN/A 3032630SN/A if (!dcachePort.sendTiming(data_write_pkt)) { 3042623SN/A _status = DcacheRetry; 3052623SN/A dcache_pkt = data_write_pkt; 3062623SN/A } else { 3072623SN/A _status = DcacheWaitResponse; 3082623SN/A dcache_pkt = NULL; 3092623SN/A } 3102623SN/A } 3112623SN/A 3122623SN/A // This will need a new way to tell if it's hooked up to a cache or not. 3132623SN/A if (data_write_req->getFlags() & UNCACHEABLE) 3142623SN/A recordEvent("Uncached Write"); 3152623SN/A 3162623SN/A // If the write needs to have a fault on the access, consider calling 3172623SN/A // changeStatus() and changing it to "bad addr write" or something. 3182623SN/A return fault; 3192623SN/A} 3202623SN/A 3212623SN/A 3222623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3232623SN/Atemplate 3242623SN/AFault 3252623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 3262623SN/A unsigned flags, uint64_t *res); 3272623SN/A 3282623SN/Atemplate 3292623SN/AFault 3302623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 3312623SN/A unsigned flags, uint64_t *res); 3322623SN/A 3332623SN/Atemplate 3342623SN/AFault 3352623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 3362623SN/A unsigned flags, uint64_t *res); 3372623SN/A 3382623SN/Atemplate 3392623SN/AFault 3402623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 3412623SN/A unsigned flags, uint64_t *res); 3422623SN/A 3432623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3442623SN/A 3452623SN/Atemplate<> 3462623SN/AFault 3472623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 3482623SN/A{ 3492623SN/A return write(*(uint64_t*)&data, addr, flags, res); 3502623SN/A} 3512623SN/A 3522623SN/Atemplate<> 3532623SN/AFault 3542623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 3552623SN/A{ 3562623SN/A return write(*(uint32_t*)&data, addr, flags, res); 3572623SN/A} 3582623SN/A 3592623SN/A 3602623SN/Atemplate<> 3612623SN/AFault 3622623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 3632623SN/A{ 3642623SN/A return write((uint32_t)data, addr, flags, res); 3652623SN/A} 3662623SN/A 3672623SN/A 3682623SN/Avoid 3692623SN/ATimingSimpleCPU::fetch() 3702623SN/A{ 3712631SN/A checkForInterrupts(); 3722631SN/A 3732663Sstever@eecs.umich.edu // need to fill in CPU & thread IDs here 3742663Sstever@eecs.umich.edu Request *ifetch_req = new Request(); 3752835Srdreslin@umich.edu ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 3762662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 3772623SN/A 3782641Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 3792623SN/A ifetch_pkt->dataStatic(&inst); 3802623SN/A 3812623SN/A if (fault == NoFault) { 3822630SN/A if (!icachePort.sendTiming(ifetch_pkt)) { 3832623SN/A // Need to wait for retry 3842623SN/A _status = IcacheRetry; 3852623SN/A } else { 3862623SN/A // Need to wait for cache to respond 3872623SN/A _status = IcacheWaitResponse; 3882623SN/A // ownership of packet transferred to memory system 3892623SN/A ifetch_pkt = NULL; 3902623SN/A } 3912623SN/A } else { 3922644Sstever@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 3932644Sstever@eecs.umich.edu advanceInst(fault); 3942623SN/A } 3952623SN/A} 3962623SN/A 3972623SN/A 3982623SN/Avoid 3992644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 4002623SN/A{ 4012623SN/A advancePC(fault); 4022623SN/A 4032631SN/A if (_status == Running) { 4042631SN/A // kick off fetch of next instruction... callback from icache 4052631SN/A // response will cause that instruction to be executed, 4062631SN/A // keeping the CPU running. 4072631SN/A fetch(); 4082631SN/A } 4092623SN/A} 4102623SN/A 4112623SN/A 4122623SN/Avoid 4132644Sstever@eecs.umich.eduTimingSimpleCPU::completeIfetch(Packet *pkt) 4142623SN/A{ 4152623SN/A // received a response from the icache: execute the received 4162623SN/A // instruction 4172644Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 4182623SN/A assert(_status == IcacheWaitResponse); 4192798Sktlim@umich.edu 4202623SN/A _status = Running; 4212644Sstever@eecs.umich.edu 4222644Sstever@eecs.umich.edu delete pkt->req; 4232644Sstever@eecs.umich.edu delete pkt; 4242644Sstever@eecs.umich.edu 4252839Sktlim@umich.edu if (getState() == SimObject::Draining) { 4262839Sktlim@umich.edu completeDrain(); 4272798Sktlim@umich.edu return; 4282798Sktlim@umich.edu } 4292798Sktlim@umich.edu 4302623SN/A preExecute(); 4312644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 4322623SN/A // load or store: just send to dcache 4332623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 4342644Sstever@eecs.umich.edu if (fault == NoFault) { 4352644Sstever@eecs.umich.edu // successfully initiated access: instruction will 4362644Sstever@eecs.umich.edu // complete in dcache response callback 4372644Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse); 4382644Sstever@eecs.umich.edu } else { 4392644Sstever@eecs.umich.edu // fault: complete now to invoke fault handler 4402644Sstever@eecs.umich.edu postExecute(); 4412644Sstever@eecs.umich.edu advanceInst(fault); 4422644Sstever@eecs.umich.edu } 4432623SN/A } else { 4442623SN/A // non-memory instruction: execute completely now 4452623SN/A Fault fault = curStaticInst->execute(this, traceData); 4462644Sstever@eecs.umich.edu postExecute(); 4472644Sstever@eecs.umich.edu advanceInst(fault); 4482623SN/A } 4492623SN/A} 4502623SN/A 4512623SN/A 4522623SN/Abool 4532630SN/ATimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) 4542623SN/A{ 4552855Srdreslin@umich.edu if (cpu->_status == DcacheWaitResponse) 4562855Srdreslin@umich.edu cpu->completeDataAccess(pkt); 4572855Srdreslin@umich.edu else if (cpu->_status == IcacheWaitResponse) 4582855Srdreslin@umich.edu cpu->completeIfetch(pkt); 4592855Srdreslin@umich.edu else 4602855Srdreslin@umich.edu assert("OOPS" && 0); 4612623SN/A return true; 4622623SN/A} 4632623SN/A 4642657Ssaidi@eecs.umich.eduvoid 4652623SN/ATimingSimpleCPU::IcachePort::recvRetry() 4662623SN/A{ 4672623SN/A // we shouldn't get a retry unless we have a packet that we're 4682623SN/A // waiting to transmit 4692623SN/A assert(cpu->ifetch_pkt != NULL); 4702623SN/A assert(cpu->_status == IcacheRetry); 4712623SN/A Packet *tmp = cpu->ifetch_pkt; 4722657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 4732657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 4742657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 4752657Ssaidi@eecs.umich.edu } 4762623SN/A} 4772623SN/A 4782623SN/Avoid 4792623SN/ATimingSimpleCPU::completeDataAccess(Packet *pkt) 4802623SN/A{ 4812623SN/A // received a response from the dcache: complete the load or store 4822623SN/A // instruction 4832641Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 4842623SN/A assert(_status == DcacheWaitResponse); 4852623SN/A _status = Running; 4862623SN/A 4872839Sktlim@umich.edu if (getState() == SimObject::Draining) { 4882839Sktlim@umich.edu completeDrain(); 4892798Sktlim@umich.edu 4902798Sktlim@umich.edu delete pkt->req; 4912798Sktlim@umich.edu delete pkt; 4922798Sktlim@umich.edu 4932798Sktlim@umich.edu return; 4942798Sktlim@umich.edu } 4952798Sktlim@umich.edu 4962623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 4972623SN/A 4982644Sstever@eecs.umich.edu delete pkt->req; 4992644Sstever@eecs.umich.edu delete pkt; 5002644Sstever@eecs.umich.edu 5012644Sstever@eecs.umich.edu postExecute(); 5022644Sstever@eecs.umich.edu advanceInst(fault); 5032623SN/A} 5042623SN/A 5052623SN/A 5062798Sktlim@umich.eduvoid 5072839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 5082798Sktlim@umich.edu{ 5092839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 5102839Sktlim@umich.edu changeState(SimObject::DrainedTiming); 5112839Sktlim@umich.edu drainEvent->process(); 5122798Sktlim@umich.edu} 5132623SN/A 5142623SN/Abool 5152630SN/ATimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) 5162623SN/A{ 5172630SN/A cpu->completeDataAccess(pkt); 5182623SN/A return true; 5192623SN/A} 5202623SN/A 5212657Ssaidi@eecs.umich.eduvoid 5222623SN/ATimingSimpleCPU::DcachePort::recvRetry() 5232623SN/A{ 5242623SN/A // we shouldn't get a retry unless we have a packet that we're 5252623SN/A // waiting to transmit 5262623SN/A assert(cpu->dcache_pkt != NULL); 5272623SN/A assert(cpu->_status == DcacheRetry); 5282623SN/A Packet *tmp = cpu->dcache_pkt; 5292657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 5302657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 5312657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 5322657Ssaidi@eecs.umich.edu } 5332623SN/A} 5342623SN/A 5352623SN/A 5362623SN/A//////////////////////////////////////////////////////////////////////// 5372623SN/A// 5382623SN/A// TimingSimpleCPU Simulation Object 5392623SN/A// 5402623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 5412623SN/A 5422623SN/A Param<Counter> max_insts_any_thread; 5432623SN/A Param<Counter> max_insts_all_threads; 5442623SN/A Param<Counter> max_loads_any_thread; 5452623SN/A Param<Counter> max_loads_all_threads; 5462623SN/A SimObjectParam<MemObject *> mem; 5472623SN/A 5482623SN/A#if FULL_SYSTEM 5492623SN/A SimObjectParam<AlphaITB *> itb; 5502623SN/A SimObjectParam<AlphaDTB *> dtb; 5512623SN/A SimObjectParam<System *> system; 5522623SN/A Param<int> cpu_id; 5532623SN/A Param<Tick> profile; 5542623SN/A#else 5552623SN/A SimObjectParam<Process *> workload; 5562623SN/A#endif // FULL_SYSTEM 5572623SN/A 5582623SN/A Param<int> clock; 5592623SN/A 5602623SN/A Param<bool> defer_registration; 5612623SN/A Param<int> width; 5622623SN/A Param<bool> function_trace; 5632623SN/A Param<Tick> function_trace_start; 5642623SN/A Param<bool> simulate_stalls; 5652623SN/A 5662623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 5672623SN/A 5682623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 5692623SN/A 5702623SN/A INIT_PARAM(max_insts_any_thread, 5712623SN/A "terminate when any thread reaches this inst count"), 5722623SN/A INIT_PARAM(max_insts_all_threads, 5732623SN/A "terminate when all threads have reached this inst count"), 5742623SN/A INIT_PARAM(max_loads_any_thread, 5752623SN/A "terminate when any thread reaches this load count"), 5762623SN/A INIT_PARAM(max_loads_all_threads, 5772623SN/A "terminate when all threads have reached this load count"), 5782623SN/A INIT_PARAM(mem, "memory"), 5792623SN/A 5802623SN/A#if FULL_SYSTEM 5812623SN/A INIT_PARAM(itb, "Instruction TLB"), 5822623SN/A INIT_PARAM(dtb, "Data TLB"), 5832623SN/A INIT_PARAM(system, "system object"), 5842623SN/A INIT_PARAM(cpu_id, "processor ID"), 5852623SN/A INIT_PARAM(profile, ""), 5862623SN/A#else 5872623SN/A INIT_PARAM(workload, "processes to run"), 5882623SN/A#endif // FULL_SYSTEM 5892623SN/A 5902623SN/A INIT_PARAM(clock, "clock speed"), 5912623SN/A INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 5922623SN/A INIT_PARAM(width, "cpu width"), 5932623SN/A INIT_PARAM(function_trace, "Enable function trace"), 5942623SN/A INIT_PARAM(function_trace_start, "Cycle to start function trace"), 5952623SN/A INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 5962623SN/A 5972623SN/AEND_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 5982623SN/A 5992623SN/A 6002623SN/ACREATE_SIM_OBJECT(TimingSimpleCPU) 6012623SN/A{ 6022623SN/A TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 6032623SN/A params->name = getInstanceName(); 6042623SN/A params->numberOfThreads = 1; 6052623SN/A params->max_insts_any_thread = max_insts_any_thread; 6062623SN/A params->max_insts_all_threads = max_insts_all_threads; 6072623SN/A params->max_loads_any_thread = max_loads_any_thread; 6082623SN/A params->max_loads_all_threads = max_loads_all_threads; 6092623SN/A params->deferRegistration = defer_registration; 6102623SN/A params->clock = clock; 6112623SN/A params->functionTrace = function_trace; 6122623SN/A params->functionTraceStart = function_trace_start; 6132623SN/A params->mem = mem; 6142623SN/A 6152623SN/A#if FULL_SYSTEM 6162623SN/A params->itb = itb; 6172623SN/A params->dtb = dtb; 6182623SN/A params->system = system; 6192623SN/A params->cpu_id = cpu_id; 6202623SN/A params->profile = profile; 6212623SN/A#else 6222623SN/A params->process = workload; 6232623SN/A#endif 6242623SN/A 6252623SN/A TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 6262623SN/A return cpu; 6272623SN/A} 6282623SN/A 6292623SN/AREGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 6302623SN/A 631