timing.cc revision 12085
12623SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 311147Smitch.hayenga@arm.com * Copyright (c) 2010-2013,2015 ARM Limited 47725SAli.Saidi@ARM.com * All rights reserved 57725SAli.Saidi@ARM.com * 67725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147725SAli.Saidi@ARM.com * 152623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162623SN/A * All rights reserved. 172623SN/A * 182623SN/A * Redistribution and use in source and binary forms, with or without 192623SN/A * modification, are permitted provided that the following conditions are 202623SN/A * met: redistributions of source code must retain the above copyright 212623SN/A * notice, this list of conditions and the following disclaimer; 222623SN/A * redistributions in binary form must reproduce the above copyright 232623SN/A * notice, this list of conditions and the following disclaimer in the 242623SN/A * documentation and/or other materials provided with the distribution; 252623SN/A * neither the name of the copyright holders nor the names of its 262623SN/A * contributors may be used to endorse or promote products derived from 272623SN/A * this software without specific prior written permission. 282623SN/A * 292623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422623SN/A */ 432623SN/A 4411793Sbrandon.potter@amd.com#include "cpu/simple/timing.hh" 4511793Sbrandon.potter@amd.com 463170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 478105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 482623SN/A#include "arch/utility.hh" 494040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 506658Snate@binkert.org#include "config/the_isa.hh" 512623SN/A#include "cpu/exetrace.hh" 528232Snate@binkert.org#include "debug/Config.hh" 539152Satgutier@umich.edu#include "debug/Drain.hh" 548232Snate@binkert.org#include "debug/ExecFaulting.hh" 5511793Sbrandon.potter@amd.com#include "debug/Mwait.hh" 568232Snate@binkert.org#include "debug/SimpleCPU.hh" 573348Sbinkertn@umich.edu#include "mem/packet.hh" 583348Sbinkertn@umich.edu#include "mem/packet_access.hh" 594762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 607678Sgblack@eecs.umich.edu#include "sim/faults.hh" 618779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 622901Ssaidi@eecs.umich.edu#include "sim/system.hh" 632623SN/A 642623SN/Ausing namespace std; 652623SN/Ausing namespace TheISA; 662623SN/A 672623SN/Avoid 682623SN/ATimingSimpleCPU::init() 692623SN/A{ 7011147Smitch.hayenga@arm.com BaseSimpleCPU::init(); 712623SN/A} 722623SN/A 732623SN/Avoid 748707Sandreas.hansson@arm.comTimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 752948Ssaidi@eecs.umich.edu{ 762948Ssaidi@eecs.umich.edu pkt = _pkt; 775606Snate@binkert.org cpu->schedule(this, t); 782948Ssaidi@eecs.umich.edu} 792948Ssaidi@eecs.umich.edu 805529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 818707Sandreas.hansson@arm.com : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 829179Sandreas.hansson@arm.com dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 8312085Sspwilson2@wisc.edu fetchEvent([this]{ fetch(); }, name()) 842623SN/A{ 852623SN/A _status = Idle; 862623SN/A} 872623SN/A 882623SN/A 8910030SAli.Saidi@ARM.com 902623SN/ATimingSimpleCPU::~TimingSimpleCPU() 912623SN/A{ 922623SN/A} 932623SN/A 9410913Sandreas.sandberg@arm.comDrainState 9510913Sandreas.sandberg@arm.comTimingSimpleCPU::drain() 962798Sktlim@umich.edu{ 979448SAndreas.Sandberg@ARM.com if (switchedOut()) 9810913Sandreas.sandberg@arm.com return DrainState::Drained; 999448SAndreas.Sandberg@ARM.com 1009342SAndreas.Sandberg@arm.com if (_status == Idle || 1019448SAndreas.Sandberg@ARM.com (_status == BaseSimpleCPU::Running && isDrained())) { 1029442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "No need to drain.\n"); 10311147Smitch.hayenga@arm.com activeThreads.clear(); 10410913Sandreas.sandberg@arm.com return DrainState::Drained; 1052798Sktlim@umich.edu } else { 10611147Smitch.hayenga@arm.com DPRINTF(Drain, "Requesting drain.\n"); 1079442SAndreas.Sandberg@ARM.com 1089442SAndreas.Sandberg@ARM.com // The fetch event can become descheduled if a drain didn't 1099442SAndreas.Sandberg@ARM.com // succeed on the first attempt. We need to reschedule it if 1109442SAndreas.Sandberg@ARM.com // the CPU is waiting for a microcode routine to complete. 1119448SAndreas.Sandberg@ARM.com if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 1129648Sdam.sunwoo@arm.com schedule(fetchEvent, clockEdge()); 1139442SAndreas.Sandberg@ARM.com 11410913Sandreas.sandberg@arm.com return DrainState::Draining; 1152798Sktlim@umich.edu } 1162623SN/A} 1172623SN/A 1182623SN/Avoid 1199342SAndreas.Sandberg@arm.comTimingSimpleCPU::drainResume() 1202623SN/A{ 1219442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1229448SAndreas.Sandberg@ARM.com if (switchedOut()) 1239448SAndreas.Sandberg@ARM.com return; 1249442SAndreas.Sandberg@ARM.com 1255221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1269523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1273201Shsul@eecs.umich.edu 1289448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1299448SAndreas.Sandberg@ARM.com 13011147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Idle; 13111147Smitch.hayenga@arm.com 13211147Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 13311147Smitch.hayenga@arm.com if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 13411147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 1; 13511147Smitch.hayenga@arm.com 13611147Smitch.hayenga@arm.com activeThreads.push_back(tid); 13711147Smitch.hayenga@arm.com 13811147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Running; 13911147Smitch.hayenga@arm.com 14011147Smitch.hayenga@arm.com // Fetch if any threads active 14111147Smitch.hayenga@arm.com if (!fetchEvent.scheduled()) { 14211147Smitch.hayenga@arm.com schedule(fetchEvent, nextCycle()); 14311147Smitch.hayenga@arm.com } 14411147Smitch.hayenga@arm.com } else { 14511147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 0; 14611147Smitch.hayenga@arm.com } 1472623SN/A } 14811147Smitch.hayenga@arm.com 14911147Smitch.hayenga@arm.com system->totalNumInsts = 0; 1509442SAndreas.Sandberg@ARM.com} 1512798Sktlim@umich.edu 1529442SAndreas.Sandberg@ARM.combool 1539442SAndreas.Sandberg@ARM.comTimingSimpleCPU::tryCompleteDrain() 1549442SAndreas.Sandberg@ARM.com{ 15510913Sandreas.sandberg@arm.com if (drainState() != DrainState::Draining) 1569442SAndreas.Sandberg@ARM.com return false; 1579442SAndreas.Sandberg@ARM.com 15811147Smitch.hayenga@arm.com DPRINTF(Drain, "tryCompleteDrain.\n"); 1599442SAndreas.Sandberg@ARM.com if (!isDrained()) 1609442SAndreas.Sandberg@ARM.com return false; 1619442SAndreas.Sandberg@ARM.com 1629442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 16310913Sandreas.sandberg@arm.com signalDrainDone(); 1649442SAndreas.Sandberg@ARM.com 1659442SAndreas.Sandberg@ARM.com return true; 1662798Sktlim@umich.edu} 1672798Sktlim@umich.edu 1682798Sktlim@umich.eduvoid 1692798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1702798Sktlim@umich.edu{ 17111147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 17211147Smitch.hayenga@arm.com M5_VAR_USED SimpleThread* thread = t_info.thread; 17311147Smitch.hayenga@arm.com 1749429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1759429SAndreas.Sandberg@ARM.com 1769442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1779342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 17811147Smitch.hayenga@arm.com assert(!t_info.stayAtPC); 17911147Smitch.hayenga@arm.com assert(thread->microPC() == 0); 1809442SAndreas.Sandberg@ARM.com 18110464SAndreas.Sandberg@ARM.com updateCycleCounts(); 1822623SN/A} 1832623SN/A 1842623SN/A 1852623SN/Avoid 1862623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1872623SN/A{ 1889429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 1892623SN/A 1909179Sandreas.hansson@arm.com previousCycle = curCycle(); 1912623SN/A} 1922623SN/A 1939523SAndreas.Sandberg@ARM.comvoid 1949523SAndreas.Sandberg@ARM.comTimingSimpleCPU::verifyMemoryMode() const 1959523SAndreas.Sandberg@ARM.com{ 1969524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 1979523SAndreas.Sandberg@ARM.com fatal("The timing CPU requires the memory system to be in " 1989523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 1999523SAndreas.Sandberg@ARM.com } 2009523SAndreas.Sandberg@ARM.com} 2012623SN/A 2022623SN/Avoid 20310407Smitch.hayenga@arm.comTimingSimpleCPU::activateContext(ThreadID thread_num) 2042623SN/A{ 20510407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2065221Ssaidi@eecs.umich.edu 20711147Smitch.hayenga@arm.com assert(thread_num < numThreads); 2082623SN/A 20911147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 1; 21011147Smitch.hayenga@arm.com if (_status == BaseSimpleCPU::Idle) 21111147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Running; 2123686Sktlim@umich.edu 2132623SN/A // kick things off by initiating the fetch of the next instruction 21411147Smitch.hayenga@arm.com if (!fetchEvent.scheduled()) 21511147Smitch.hayenga@arm.com schedule(fetchEvent, clockEdge(Cycles(0))); 21611147Smitch.hayenga@arm.com 21711147Smitch.hayenga@arm.com if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 21811147Smitch.hayenga@arm.com == activeThreads.end()) { 21911147Smitch.hayenga@arm.com activeThreads.push_back(thread_num); 22011147Smitch.hayenga@arm.com } 22111526Sdavid.guillen@arm.com 22211526Sdavid.guillen@arm.com BaseCPU::activateContext(thread_num); 2232623SN/A} 2242623SN/A 2252623SN/A 2262623SN/Avoid 2278737Skoansin.tan@gmail.comTimingSimpleCPU::suspendContext(ThreadID thread_num) 2282623SN/A{ 2295221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2305221Ssaidi@eecs.umich.edu 23111147Smitch.hayenga@arm.com assert(thread_num < numThreads); 23211147Smitch.hayenga@arm.com activeThreads.remove(thread_num); 2332623SN/A 2346043Sgblack@eecs.umich.edu if (_status == Idle) 2356043Sgblack@eecs.umich.edu return; 2366043Sgblack@eecs.umich.edu 2379342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2382623SN/A 23911147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 0; 2402623SN/A 24111147Smitch.hayenga@arm.com if (activeThreads.empty()) { 24211147Smitch.hayenga@arm.com _status = Idle; 24311147Smitch.hayenga@arm.com 24411147Smitch.hayenga@arm.com if (fetchEvent.scheduled()) { 24511147Smitch.hayenga@arm.com deschedule(fetchEvent); 24611147Smitch.hayenga@arm.com } 24711147Smitch.hayenga@arm.com } 24811526Sdavid.guillen@arm.com 24911526Sdavid.guillen@arm.com BaseCPU::suspendContext(thread_num); 2502623SN/A} 2512623SN/A 2525728Sgblack@eecs.umich.edubool 2535728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2545728Sgblack@eecs.umich.edu{ 25511147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 25611147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 25711147Smitch.hayenga@arm.com 2585728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 25910533Sali.saidi@arm.com 26010533Sali.saidi@arm.com // We're about the issues a locked load, so tell the monitor 26110533Sali.saidi@arm.com // to start caring about this address 26210533Sali.saidi@arm.com if (pkt->isRead() && pkt->req->isLLSC()) { 26310533Sali.saidi@arm.com TheISA::handleLockedRead(thread, pkt->req); 26410533Sali.saidi@arm.com } 2658105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2669180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 2679179Sandreas.hansson@arm.com new IprEvent(pkt, this, clockEdge(delay)); 2685728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2695728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2708975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(pkt)) { 2715728Sgblack@eecs.umich.edu _status = DcacheRetry; 2725728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2735728Sgblack@eecs.umich.edu } else { 2745728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2755728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2765728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2775728Sgblack@eecs.umich.edu } 2785728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2795728Sgblack@eecs.umich.edu} 2802623SN/A 2815894Sgblack@eecs.umich.eduvoid 2826973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2836973Stjones1@inf.ed.ac.uk bool read) 2845744Sgblack@eecs.umich.edu{ 28511147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 28611147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 28711147Smitch.hayenga@arm.com 28810653Sandreas.hansson@arm.com PacketPtr pkt = buildPacket(req, read); 28910566Sandreas.hansson@arm.com pkt->dataDynamic<uint8_t>(data); 2905894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2915894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2925894Sgblack@eecs.umich.edu pkt->makeResponse(); 2935894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2945894Sgblack@eecs.umich.edu } else if (read) { 2955894Sgblack@eecs.umich.edu handleReadPacket(pkt); 2965894Sgblack@eecs.umich.edu } else { 2975894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 2985894Sgblack@eecs.umich.edu 2996102Sgblack@eecs.umich.edu if (req->isLLSC()) { 30010030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 3015894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 3025894Sgblack@eecs.umich.edu assert(res); 3035894Sgblack@eecs.umich.edu req->setExtraData(*res); 3045894Sgblack@eecs.umich.edu } 3055894Sgblack@eecs.umich.edu 3065894Sgblack@eecs.umich.edu if (do_access) { 3075894Sgblack@eecs.umich.edu dcache_pkt = pkt; 3085894Sgblack@eecs.umich.edu handleWritePacket(); 30911148Smitch.hayenga@arm.com threadSnoop(pkt, curThread); 3105894Sgblack@eecs.umich.edu } else { 3115894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 3125894Sgblack@eecs.umich.edu completeDataAccess(pkt); 3135894Sgblack@eecs.umich.edu } 3145894Sgblack@eecs.umich.edu } 3155894Sgblack@eecs.umich.edu} 3165894Sgblack@eecs.umich.edu 3175894Sgblack@eecs.umich.eduvoid 3186973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 3196973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 3205894Sgblack@eecs.umich.edu{ 3215894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3225894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3235894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3245894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3255894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3265894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3275894Sgblack@eecs.umich.edu } else if (read) { 3287911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3297911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3305894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3315894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3327911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3337911Shestness@cs.utexas.edu pkt2->senderState); 3345894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3355894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3365894Sgblack@eecs.umich.edu } 3375894Sgblack@eecs.umich.edu } 3385894Sgblack@eecs.umich.edu } else { 3395894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3407911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3417911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3425894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3435894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3445894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3457911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3467911Shestness@cs.utexas.edu pkt2->senderState); 3475894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3485894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3495894Sgblack@eecs.umich.edu } 3505894Sgblack@eecs.umich.edu } 3515894Sgblack@eecs.umich.edu } 3525894Sgblack@eecs.umich.edu} 3535894Sgblack@eecs.umich.edu 3545894Sgblack@eecs.umich.eduvoid 35510379Sandreas.hansson@arm.comTimingSimpleCPU::translationFault(const Fault &fault) 3565894Sgblack@eecs.umich.edu{ 3576739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3586739Sgblack@eecs.umich.edu // for instance prefetches. 35910464SAndreas.Sandberg@ARM.com updateCycleCounts(); 3605894Sgblack@eecs.umich.edu 3615894Sgblack@eecs.umich.edu if (traceData) { 3625894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3635894Sgblack@eecs.umich.edu delete traceData; 3645894Sgblack@eecs.umich.edu traceData = NULL; 3655744Sgblack@eecs.umich.edu } 3665744Sgblack@eecs.umich.edu 3675894Sgblack@eecs.umich.edu postExecute(); 3685894Sgblack@eecs.umich.edu 3699442SAndreas.Sandberg@ARM.com advanceInst(fault); 3705894Sgblack@eecs.umich.edu} 3715894Sgblack@eecs.umich.edu 37210653Sandreas.hansson@arm.comPacketPtr 37310653Sandreas.hansson@arm.comTimingSimpleCPU::buildPacket(RequestPtr req, bool read) 3745894Sgblack@eecs.umich.edu{ 37510653Sandreas.hansson@arm.com return read ? Packet::createRead(req) : Packet::createWrite(req); 3765894Sgblack@eecs.umich.edu} 3775894Sgblack@eecs.umich.edu 3785894Sgblack@eecs.umich.eduvoid 3795894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3805894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 3815894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3825894Sgblack@eecs.umich.edu{ 3835894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3845894Sgblack@eecs.umich.edu 3858105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 3865744Sgblack@eecs.umich.edu 3875894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 38810653Sandreas.hansson@arm.com pkt1 = buildPacket(req, read); 3895894Sgblack@eecs.umich.edu return; 3905894Sgblack@eecs.umich.edu } 3915894Sgblack@eecs.umich.edu 39210653Sandreas.hansson@arm.com pkt1 = buildPacket(req1, read); 39310653Sandreas.hansson@arm.com pkt2 = buildPacket(req2, read); 3945894Sgblack@eecs.umich.edu 3958949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 3965744Sgblack@eecs.umich.edu 39710566Sandreas.hansson@arm.com pkt->dataDynamic<uint8_t>(data); 3985744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 3995744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 4005744Sgblack@eecs.umich.edu 4015744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 4025744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 4035744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 4045744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 4055744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 4065744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 4075744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 4085744Sgblack@eecs.umich.edu} 4095744Sgblack@eecs.umich.edu 4102623SN/AFault 4118444Sgblack@eecs.umich.eduTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 41211608Snikos.nikoleris@arm.com unsigned size, Request::Flags flags) 4132623SN/A{ 41411303Ssteve.reinhardt@amd.com panic("readMem() is for atomic accesses, and should " 41511303Ssteve.reinhardt@amd.com "never be called on TimingSimpleCPU.\n"); 41611303Ssteve.reinhardt@amd.com} 41711303Ssteve.reinhardt@amd.com 41811303Ssteve.reinhardt@amd.comFault 41911608Snikos.nikoleris@arm.comTimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, 42011608Snikos.nikoleris@arm.com Request::Flags flags) 42111303Ssteve.reinhardt@amd.com{ 42211147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 42311147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 42411147Smitch.hayenga@arm.com 4255728Sgblack@eecs.umich.edu Fault fault; 4265728Sgblack@eecs.umich.edu const int asid = 0; 4277720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4289814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 4296973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4302623SN/A 43110665SAli.Saidi@ARM.com if (traceData) 43210665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 4337045Ssteve.reinhardt@amd.com 43411435Smitch.hayenga@arm.com RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, 43511435Smitch.hayenga@arm.com thread->contextId()); 4365728Sgblack@eecs.umich.edu 43710024Sdam.sunwoo@arm.com req->taskId(taskId()); 43810024Sdam.sunwoo@arm.com 4397520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4405744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4415728Sgblack@eecs.umich.edu 4425894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4435744Sgblack@eecs.umich.edu if (split_addr > addr) { 4445894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4456102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4465894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4475894Sgblack@eecs.umich.edu 4486973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4497520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4506973Stjones1@inf.ed.ac.uk NULL, mode); 4518486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4528486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4538486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4548486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4556973Stjones1@inf.ed.ac.uk 45611147Smitch.hayenga@arm.com thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 45711147Smitch.hayenga@arm.com thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 4585744Sgblack@eecs.umich.edu } else { 4596973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4607520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4618486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4628486Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 46311147Smitch.hayenga@arm.com thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 4642623SN/A } 4652623SN/A 4665728Sgblack@eecs.umich.edu return NoFault; 4672623SN/A} 4682623SN/A 4695728Sgblack@eecs.umich.edubool 4705728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4715728Sgblack@eecs.umich.edu{ 47211147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 47311147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 47411147Smitch.hayenga@arm.com 4755728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4768105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4779180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4789179Sandreas.hansson@arm.com new IprEvent(dcache_pkt, this, clockEdge(delay)); 4795728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4805728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4818975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 4825728Sgblack@eecs.umich.edu _status = DcacheRetry; 4835728Sgblack@eecs.umich.edu } else { 4845728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4855728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4865728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4875728Sgblack@eecs.umich.edu } 4885728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4895728Sgblack@eecs.umich.edu} 4902623SN/A 4912623SN/AFault 4928444Sgblack@eecs.umich.eduTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 49311608Snikos.nikoleris@arm.com Addr addr, Request::Flags flags, uint64_t *res) 4942623SN/A{ 49511147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 49611147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 49711147Smitch.hayenga@arm.com 4988443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 4995728Sgblack@eecs.umich.edu const int asid = 0; 5007720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 5019814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 5026973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 5033169Sstever@eecs.umich.edu 50410031SAli.Saidi@ARM.com if (data == NULL) { 50510031SAli.Saidi@ARM.com assert(flags & Request::CACHE_BLOCK_ZERO); 50610031SAli.Saidi@ARM.com // This must be a cache block cleaning request 50710031SAli.Saidi@ARM.com memset(newData, 0, size); 50810031SAli.Saidi@ARM.com } else { 50910031SAli.Saidi@ARM.com memcpy(newData, data, size); 51010031SAli.Saidi@ARM.com } 51110031SAli.Saidi@ARM.com 51210665SAli.Saidi@ARM.com if (traceData) 51310665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 5147045Ssteve.reinhardt@amd.com 51511435Smitch.hayenga@arm.com RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, 51611435Smitch.hayenga@arm.com thread->contextId()); 5175728Sgblack@eecs.umich.edu 51810024Sdam.sunwoo@arm.com req->taskId(taskId()); 51910024Sdam.sunwoo@arm.com 5207520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 5215744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 5225728Sgblack@eecs.umich.edu 5235894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 5245744Sgblack@eecs.umich.edu if (split_addr > addr) { 5255894Sgblack@eecs.umich.edu RequestPtr req1, req2; 5266102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 5275894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5285894Sgblack@eecs.umich.edu 5296973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5308443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 5318486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 5328486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 5338486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 5348486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 5356973Stjones1@inf.ed.ac.uk 53611147Smitch.hayenga@arm.com thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode); 53711147Smitch.hayenga@arm.com thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode); 5385744Sgblack@eecs.umich.edu } else { 5396973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5408443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5418486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation = 5428486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state); 54311147Smitch.hayenga@arm.com thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 5442623SN/A } 5452623SN/A 5467045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5475728Sgblack@eecs.umich.edu return NoFault; 5482623SN/A} 5492623SN/A 55011148Smitch.hayenga@arm.comvoid 55111148Smitch.hayenga@arm.comTimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 55211148Smitch.hayenga@arm.com{ 55311148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 55411148Smitch.hayenga@arm.com if (tid != sender) { 55511321Ssteve.reinhardt@amd.com if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 55611151Smitch.hayenga@arm.com wakeup(tid); 55711148Smitch.hayenga@arm.com } 55811148Smitch.hayenga@arm.com TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt, 55911148Smitch.hayenga@arm.com dcachePort.cacheBlockMask); 56011148Smitch.hayenga@arm.com } 56111148Smitch.hayenga@arm.com } 56211148Smitch.hayenga@arm.com} 5632623SN/A 5642623SN/Avoid 5656973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5666973Stjones1@inf.ed.ac.uk{ 5679342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5686973Stjones1@inf.ed.ac.uk 5696973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 5706973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 5716973Stjones1@inf.ed.ac.uk state->setNoFault(); 5726973Stjones1@inf.ed.ac.uk } 5737691SAli.Saidi@ARM.com delete [] state->data; 5746973Stjones1@inf.ed.ac.uk state->deleteReqs(); 5756973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 5766973Stjones1@inf.ed.ac.uk } else { 5776973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 5786973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 5796973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 5806973Stjones1@inf.ed.ac.uk } else { 5816973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5826973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 5836973Stjones1@inf.ed.ac.uk } 5846973Stjones1@inf.ed.ac.uk } 5856973Stjones1@inf.ed.ac.uk 5866973Stjones1@inf.ed.ac.uk delete state; 5876973Stjones1@inf.ed.ac.uk} 5886973Stjones1@inf.ed.ac.uk 5896973Stjones1@inf.ed.ac.uk 5906973Stjones1@inf.ed.ac.ukvoid 5912623SN/ATimingSimpleCPU::fetch() 5922623SN/A{ 59311147Smitch.hayenga@arm.com // Change thread if multi-threaded 59411147Smitch.hayenga@arm.com swapActiveThread(); 59511147Smitch.hayenga@arm.com 59611147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 59711147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 59811147Smitch.hayenga@arm.com 5995221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 6005221Ssaidi@eecs.umich.edu 60110596Sgabeblack@google.com if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 6023387Sgblack@eecs.umich.edu checkForInterrupts(); 60310596Sgabeblack@google.com checkPcEventQueue(); 60410596Sgabeblack@google.com } 6055348Ssaidi@eecs.umich.edu 6068143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 6078143SAli.Saidi@ARM.com if (_status == Idle) 6088143SAli.Saidi@ARM.com return; 6098143SAli.Saidi@ARM.com 6107720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 61111147Smitch.hayenga@arm.com bool needToFetch = !isRomMicroPC(pcState.microPC()) && 61211147Smitch.hayenga@arm.com !curMacroStaticInst; 6132623SN/A 6147720Sgblack@eecs.umich.edu if (needToFetch) { 6159342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6165669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 61710024Sdam.sunwoo@arm.com ifetch_req->taskId(taskId()); 61811435Smitch.hayenga@arm.com ifetch_req->setContext(thread->contextId()); 6195894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 6208277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 62111147Smitch.hayenga@arm.com thread->itb->translateTiming(ifetch_req, thread->getTC(), 62211147Smitch.hayenga@arm.com &fetchTranslation, BaseTLB::Execute); 6232623SN/A } else { 6245669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6255669Sgblack@eecs.umich.edu completeIfetch(NULL); 6265894Sgblack@eecs.umich.edu 62710464SAndreas.Sandberg@ARM.com updateCycleCounts(); 6285894Sgblack@eecs.umich.edu } 6295894Sgblack@eecs.umich.edu} 6305894Sgblack@eecs.umich.edu 6315894Sgblack@eecs.umich.edu 6325894Sgblack@eecs.umich.eduvoid 63310379Sandreas.hansson@arm.comTimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, 63410379Sandreas.hansson@arm.com ThreadContext *tc) 6355894Sgblack@eecs.umich.edu{ 6365894Sgblack@eecs.umich.edu if (fault == NoFault) { 6378277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 6388277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 6398949Sandreas.hansson@arm.com ifetch_pkt = new Packet(req, MemCmd::ReadReq); 6405894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 6418277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 6425894Sgblack@eecs.umich.edu 6438975Sandreas.hansson@arm.com if (!icachePort.sendTimingReq(ifetch_pkt)) { 6445894Sgblack@eecs.umich.edu // Need to wait for retry 6455894Sgblack@eecs.umich.edu _status = IcacheRetry; 6465894Sgblack@eecs.umich.edu } else { 6475894Sgblack@eecs.umich.edu // Need to wait for cache to respond 6485894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6495894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 6505894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 6515894Sgblack@eecs.umich.edu } 6525894Sgblack@eecs.umich.edu } else { 6538277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 6545894Sgblack@eecs.umich.edu delete req; 6555894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 6569342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6575894Sgblack@eecs.umich.edu advanceInst(fault); 6582623SN/A } 6593222Sktlim@umich.edu 66010464SAndreas.Sandberg@ARM.com updateCycleCounts(); 6612623SN/A} 6622623SN/A 6632623SN/A 6642623SN/Avoid 66510379Sandreas.hansson@arm.comTimingSimpleCPU::advanceInst(const Fault &fault) 6662623SN/A{ 66711147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 66811147Smitch.hayenga@arm.com 6698276SAli.Saidi@ARM.com if (_status == Faulting) 6708276SAli.Saidi@ARM.com return; 6718276SAli.Saidi@ARM.com 6728276SAli.Saidi@ARM.com if (fault != NoFault) { 67311877Sbrandon.potter@amd.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 67411877Sbrandon.potter@amd.com 6758276SAli.Saidi@ARM.com advancePC(fault); 67611877Sbrandon.potter@amd.com 67711877Sbrandon.potter@amd.com Tick stall = dynamic_pointer_cast<SyscallRetryFault>(fault) ? 67811877Sbrandon.potter@amd.com clockEdge(syscallRetryLatency) : clockEdge(); 67911877Sbrandon.potter@amd.com 68011877Sbrandon.potter@amd.com reschedule(fetchEvent, stall, true); 68111877Sbrandon.potter@amd.com 6828276SAli.Saidi@ARM.com _status = Faulting; 6838276SAli.Saidi@ARM.com return; 6848276SAli.Saidi@ARM.com } 6858276SAli.Saidi@ARM.com 6868276SAli.Saidi@ARM.com 68711147Smitch.hayenga@arm.com if (!t_info.stayAtPC) 6885726Sgblack@eecs.umich.edu advancePC(fault); 6892623SN/A 6909442SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6919442SAndreas.Sandberg@ARM.com return; 6929442SAndreas.Sandberg@ARM.com 6939342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6942631SN/A // kick off fetch of next instruction... callback from icache 6952631SN/A // response will cause that instruction to be executed, 6962631SN/A // keeping the CPU running. 6972631SN/A fetch(); 6982631SN/A } 6992623SN/A} 7002623SN/A 7012623SN/A 7022623SN/Avoid 7033349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 7042623SN/A{ 70511147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 70611147Smitch.hayenga@arm.com 7078277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 7088277SAli.Saidi@ARM.com pkt->getAddr() : 0); 7098277SAli.Saidi@ARM.com 7102623SN/A // received a response from the icache: execute the received 7112623SN/A // instruction 7125669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 7132623SN/A assert(_status == IcacheWaitResponse); 7142798Sktlim@umich.edu 7159342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 7162644Sstever@eecs.umich.edu 71710464SAndreas.Sandberg@ARM.com updateCycleCounts(); 7183222Sktlim@umich.edu 71910020Smatt.horsnell@ARM.com if (pkt) 72010020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 72110020Smatt.horsnell@ARM.com 72210020Smatt.horsnell@ARM.com 7232623SN/A preExecute(); 7247725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 7252623SN/A // load or store: just send to dcache 72611147Smitch.hayenga@arm.com Fault fault = curStaticInst->initiateAcc(&t_info, traceData); 7277945SAli.Saidi@ARM.com 7287945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 7297945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 7307945SAli.Saidi@ARM.com // ifetch 7319342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 7325894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 7335001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7345001Sgblack@eecs.umich.edu delete traceData; 7355001Sgblack@eecs.umich.edu traceData = NULL; 7363170Sstever@eecs.umich.edu } 7374998Sgblack@eecs.umich.edu 7382644Sstever@eecs.umich.edu postExecute(); 7395103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7405103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7415103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7425103Ssaidi@eecs.umich.edu instCnt++; 7432644Sstever@eecs.umich.edu advanceInst(fault); 7442644Sstever@eecs.umich.edu } 7455726Sgblack@eecs.umich.edu } else if (curStaticInst) { 7462623SN/A // non-memory instruction: execute completely now 74711147Smitch.hayenga@arm.com Fault fault = curStaticInst->execute(&t_info, traceData); 7484998Sgblack@eecs.umich.edu 7494998Sgblack@eecs.umich.edu // keep an instruction count 7504998Sgblack@eecs.umich.edu if (fault == NoFault) 7514998Sgblack@eecs.umich.edu countInst(); 7527655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 7535001Sgblack@eecs.umich.edu delete traceData; 7545001Sgblack@eecs.umich.edu traceData = NULL; 7555001Sgblack@eecs.umich.edu } 7564998Sgblack@eecs.umich.edu 7572644Sstever@eecs.umich.edu postExecute(); 7585103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7595103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 76011147Smitch.hayenga@arm.com curStaticInst->isFirstMicroop())) 7615103Ssaidi@eecs.umich.edu instCnt++; 7622644Sstever@eecs.umich.edu advanceInst(fault); 7635726Sgblack@eecs.umich.edu } else { 7645726Sgblack@eecs.umich.edu advanceInst(NoFault); 7652623SN/A } 7663658Sktlim@umich.edu 7675669Sgblack@eecs.umich.edu if (pkt) { 7685669Sgblack@eecs.umich.edu delete pkt->req; 7695669Sgblack@eecs.umich.edu delete pkt; 7705669Sgblack@eecs.umich.edu } 7712623SN/A} 7722623SN/A 7732948Ssaidi@eecs.umich.eduvoid 7742948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7752948Ssaidi@eecs.umich.edu{ 7762948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7772948Ssaidi@eecs.umich.edu} 7782623SN/A 7792623SN/Abool 7808975Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 7812623SN/A{ 78210669Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr()); 78310669Sandreas.hansson@arm.com // we should only ever see one response per cycle since we only 78410669Sandreas.hansson@arm.com // issue a new request once this response is sunk 78510669Sandreas.hansson@arm.com assert(!tickEvent.scheduled()); 7869165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 78710669Sandreas.hansson@arm.com tickEvent.schedule(pkt, cpu->clockEdge()); 7888948Sandreas.hansson@arm.com 7894433Ssaidi@eecs.umich.edu return true; 7902623SN/A} 7912623SN/A 7922657Ssaidi@eecs.umich.eduvoid 79310713Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvReqRetry() 7942623SN/A{ 7952623SN/A // we shouldn't get a retry unless we have a packet that we're 7962623SN/A // waiting to transmit 7972623SN/A assert(cpu->ifetch_pkt != NULL); 7982623SN/A assert(cpu->_status == IcacheRetry); 7993349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 8008975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 8012657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 8022657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 8032657Ssaidi@eecs.umich.edu } 8042623SN/A} 8052623SN/A 8062623SN/Avoid 8073349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 8082623SN/A{ 8092623SN/A // received a response from the dcache: complete the load or store 8102623SN/A // instruction 8114870Sstever@eecs.umich.edu assert(!pkt->isError()); 8127516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 8137516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 8142623SN/A 81510020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 81610464SAndreas.Sandberg@ARM.com 81710464SAndreas.Sandberg@ARM.com updateCycleCounts(); 8183184Srdreslin@umich.edu 8195728Sgblack@eecs.umich.edu if (pkt->senderState) { 8205728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8215728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 8225728Sgblack@eecs.umich.edu assert(send_state); 8235728Sgblack@eecs.umich.edu delete pkt->req; 8245728Sgblack@eecs.umich.edu delete pkt; 8255728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8265728Sgblack@eecs.umich.edu delete send_state; 82711320Ssteve.reinhardt@amd.com 8285728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8295728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8305728Sgblack@eecs.umich.edu assert(main_send_state); 8315728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 8325728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 8335728Sgblack@eecs.umich.edu main_send_state->outstanding--; 8345728Sgblack@eecs.umich.edu 8355728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 8365728Sgblack@eecs.umich.edu return; 8375728Sgblack@eecs.umich.edu } else { 8385728Sgblack@eecs.umich.edu delete main_send_state; 8395728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 8405728Sgblack@eecs.umich.edu pkt = big_pkt; 8415728Sgblack@eecs.umich.edu } 8425728Sgblack@eecs.umich.edu } 8435728Sgblack@eecs.umich.edu 8449342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 8455728Sgblack@eecs.umich.edu 84611147Smitch.hayenga@arm.com Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread], 84711147Smitch.hayenga@arm.com traceData); 8482623SN/A 8494998Sgblack@eecs.umich.edu // keep an instruction count 8504998Sgblack@eecs.umich.edu if (fault == NoFault) 8514998Sgblack@eecs.umich.edu countInst(); 8525001Sgblack@eecs.umich.edu else if (traceData) { 8535001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 8545001Sgblack@eecs.umich.edu delete traceData; 8555001Sgblack@eecs.umich.edu traceData = NULL; 8565001Sgblack@eecs.umich.edu } 8574998Sgblack@eecs.umich.edu 8582644Sstever@eecs.umich.edu delete pkt->req; 8592644Sstever@eecs.umich.edu delete pkt; 8602644Sstever@eecs.umich.edu 8613184Srdreslin@umich.edu postExecute(); 8623227Sktlim@umich.edu 8632644Sstever@eecs.umich.edu advanceInst(fault); 8642623SN/A} 8652623SN/A 86610030SAli.Saidi@ARM.comvoid 86710464SAndreas.Sandberg@ARM.comTimingSimpleCPU::updateCycleCounts() 86810464SAndreas.Sandberg@ARM.com{ 86910464SAndreas.Sandberg@ARM.com const Cycles delta(curCycle() - previousCycle); 87010464SAndreas.Sandberg@ARM.com 87110464SAndreas.Sandberg@ARM.com numCycles += delta; 87210464SAndreas.Sandberg@ARM.com ppCycles->notify(delta); 87310464SAndreas.Sandberg@ARM.com 87410464SAndreas.Sandberg@ARM.com previousCycle = curCycle(); 87510464SAndreas.Sandberg@ARM.com} 87610464SAndreas.Sandberg@ARM.com 87710464SAndreas.Sandberg@ARM.comvoid 87810030SAli.Saidi@ARM.comTimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 87910030SAli.Saidi@ARM.com{ 88011148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 88111148Smitch.hayenga@arm.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 88211151Smitch.hayenga@arm.com cpu->wakeup(tid); 88311148Smitch.hayenga@arm.com } 88410529Smorr@cs.wisc.edu } 88511147Smitch.hayenga@arm.com 88611356Skrinat01@arm.com // Making it uniform across all CPUs: 88711356Skrinat01@arm.com // The CPUs need to be woken up only on an invalidation packet (when using caches) 88811356Skrinat01@arm.com // or on an incoming write packet (when not using caches) 88911356Skrinat01@arm.com // It is not necessary to wake up the processor on all incoming packets 89011356Skrinat01@arm.com if (pkt->isInvalidate() || pkt->isWrite()) { 89111356Skrinat01@arm.com for (auto &t_info : cpu->threadInfo) { 89211356Skrinat01@arm.com TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 89311356Skrinat01@arm.com } 89411147Smitch.hayenga@arm.com } 89510030SAli.Saidi@ARM.com} 89610030SAli.Saidi@ARM.com 89710529Smorr@cs.wisc.eduvoid 89810529Smorr@cs.wisc.eduTimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) 89910529Smorr@cs.wisc.edu{ 90011148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 90111321Ssteve.reinhardt@amd.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 90211151Smitch.hayenga@arm.com cpu->wakeup(tid); 90311148Smitch.hayenga@arm.com } 90410529Smorr@cs.wisc.edu } 90510529Smorr@cs.wisc.edu} 90610030SAli.Saidi@ARM.com 9072623SN/Abool 9088975Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 9092623SN/A{ 91010669Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr()); 9112948Ssaidi@eecs.umich.edu 91210669Sandreas.hansson@arm.com // The timing CPU is not really ticked, instead it relies on the 91310669Sandreas.hansson@arm.com // memory system (fetch and load/store) to set the pace. 91410669Sandreas.hansson@arm.com if (!tickEvent.scheduled()) { 91510669Sandreas.hansson@arm.com // Delay processing of returned data until next CPU clock edge 91610669Sandreas.hansson@arm.com tickEvent.schedule(pkt, cpu->clockEdge()); 91710669Sandreas.hansson@arm.com return true; 9189165Sandreas.hansson@arm.com } else { 91910669Sandreas.hansson@arm.com // In the case of a split transaction and a cache that is 92010669Sandreas.hansson@arm.com // faster than a CPU we could get two responses in the 92110669Sandreas.hansson@arm.com // same tick, delay the second one 92210713Sandreas.hansson@arm.com if (!retryRespEvent.scheduled()) 92310713Sandreas.hansson@arm.com cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1))); 92410669Sandreas.hansson@arm.com return false; 9253310Srdreslin@umich.edu } 9262948Ssaidi@eecs.umich.edu} 9272948Ssaidi@eecs.umich.edu 9282948Ssaidi@eecs.umich.eduvoid 9292948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 9302948Ssaidi@eecs.umich.edu{ 9312630SN/A cpu->completeDataAccess(pkt); 9322623SN/A} 9332623SN/A 9342657Ssaidi@eecs.umich.eduvoid 93510713Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvReqRetry() 9362623SN/A{ 9372623SN/A // we shouldn't get a retry unless we have a packet that we're 9382623SN/A // waiting to transmit 9392623SN/A assert(cpu->dcache_pkt != NULL); 9402623SN/A assert(cpu->_status == DcacheRetry); 9413349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 9425728Sgblack@eecs.umich.edu if (tmp->senderState) { 9435728Sgblack@eecs.umich.edu // This is a packet from a split access. 9445728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 9455728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 9465728Sgblack@eecs.umich.edu assert(send_state); 9475728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 94811320Ssteve.reinhardt@amd.com 9495728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 9505728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 9515728Sgblack@eecs.umich.edu assert(main_send_state); 9525728Sgblack@eecs.umich.edu 9538975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 9545728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 9555728Sgblack@eecs.umich.edu // and try sending the other fragment. 9565728Sgblack@eecs.umich.edu send_state->clearFromParent(); 9575728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 9585728Sgblack@eecs.umich.edu if (other_index > 0) { 9595728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 9605728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 9615728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 9625728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 9635728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 9645728Sgblack@eecs.umich.edu } 9655728Sgblack@eecs.umich.edu } else { 9665728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9675728Sgblack@eecs.umich.edu // memory system takes ownership of packet 9685728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 9695728Sgblack@eecs.umich.edu } 9705728Sgblack@eecs.umich.edu } 9718975Sandreas.hansson@arm.com } else if (sendTimingReq(tmp)) { 9722657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9733170Sstever@eecs.umich.edu // memory system takes ownership of packet 9742657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 9752657Ssaidi@eecs.umich.edu } 9762623SN/A} 9772623SN/A 9785606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 9795606Snate@binkert.org Tick t) 9805606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 9815103Ssaidi@eecs.umich.edu{ 9825606Snate@binkert.org cpu->schedule(this, t); 9835103Ssaidi@eecs.umich.edu} 9845103Ssaidi@eecs.umich.edu 9855103Ssaidi@eecs.umich.eduvoid 9865103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 9875103Ssaidi@eecs.umich.edu{ 9885103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 9895103Ssaidi@eecs.umich.edu} 9905103Ssaidi@eecs.umich.edu 9915103Ssaidi@eecs.umich.educonst char * 9925336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 9935103Ssaidi@eecs.umich.edu{ 9945103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 9955103Ssaidi@eecs.umich.edu} 9965103Ssaidi@eecs.umich.edu 9972623SN/A 9985315Sstever@gmail.comvoid 9995315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 10005315Sstever@gmail.com{ 10015315Sstever@gmail.com dcachePort.printAddr(a); 10025315Sstever@gmail.com} 10035315Sstever@gmail.com 10045315Sstever@gmail.com 10052623SN/A//////////////////////////////////////////////////////////////////////// 10062623SN/A// 10072623SN/A// TimingSimpleCPU Simulation Object 10082623SN/A// 10094762Snate@binkert.orgTimingSimpleCPU * 10104762Snate@binkert.orgTimingSimpleCPUParams::create() 10112623SN/A{ 10125529Snate@binkert.org return new TimingSimpleCPU(this); 10132623SN/A} 1014