timing.cc revision 10713
12623SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 310030SAli.Saidi@ARM.com * Copyright (c) 2010-2013 ARM Limited 47725SAli.Saidi@ARM.com * All rights reserved 57725SAli.Saidi@ARM.com * 67725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147725SAli.Saidi@ARM.com * 152623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162623SN/A * All rights reserved. 172623SN/A * 182623SN/A * Redistribution and use in source and binary forms, with or without 192623SN/A * modification, are permitted provided that the following conditions are 202623SN/A * met: redistributions of source code must retain the above copyright 212623SN/A * notice, this list of conditions and the following disclaimer; 222623SN/A * redistributions in binary form must reproduce the above copyright 232623SN/A * notice, this list of conditions and the following disclaimer in the 242623SN/A * documentation and/or other materials provided with the distribution; 252623SN/A * neither the name of the copyright holders nor the names of its 262623SN/A * contributors may be used to endorse or promote products derived from 272623SN/A * this software without specific prior written permission. 282623SN/A * 292623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422623SN/A */ 432623SN/A 443170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 458105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 462623SN/A#include "arch/utility.hh" 474040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 498229Snate@binkert.org#include "cpu/simple/timing.hh" 502623SN/A#include "cpu/exetrace.hh" 518232Snate@binkert.org#include "debug/Config.hh" 529152Satgutier@umich.edu#include "debug/Drain.hh" 538232Snate@binkert.org#include "debug/ExecFaulting.hh" 548232Snate@binkert.org#include "debug/SimpleCPU.hh" 553348Sbinkertn@umich.edu#include "mem/packet.hh" 563348Sbinkertn@umich.edu#include "mem/packet_access.hh" 574762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 587678Sgblack@eecs.umich.edu#include "sim/faults.hh" 598779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 602901Ssaidi@eecs.umich.edu#include "sim/system.hh" 612623SN/A 6210529Smorr@cs.wisc.edu#include "debug/Mwait.hh" 6310529Smorr@cs.wisc.edu 642623SN/Ausing namespace std; 652623SN/Ausing namespace TheISA; 662623SN/A 672623SN/Avoid 682623SN/ATimingSimpleCPU::init() 692623SN/A{ 702623SN/A BaseCPU::init(); 718921Sandreas.hansson@arm.com 728921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 738921Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 748921Sandreas.hansson@arm.com 759433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 768779Sgblack@eecs.umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 778779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 788779Sgblack@eecs.umich.edu // initialize CPU, including PC 798779Sgblack@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 808779Sgblack@eecs.umich.edu } 812623SN/A } 822623SN/A} 832623SN/A 842623SN/Avoid 858707Sandreas.hansson@arm.comTimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 862948Ssaidi@eecs.umich.edu{ 872948Ssaidi@eecs.umich.edu pkt = _pkt; 885606Snate@binkert.org cpu->schedule(this, t); 892948Ssaidi@eecs.umich.edu} 902948Ssaidi@eecs.umich.edu 915529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 928707Sandreas.hansson@arm.com : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 939179Sandreas.hansson@arm.com dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 949442SAndreas.Sandberg@ARM.com fetchEvent(this), drainManager(NULL) 952623SN/A{ 962623SN/A _status = Idle; 973647Srdreslin@umich.edu 987897Shestness@cs.utexas.edu system->totalNumInsts = 0; 992623SN/A} 1002623SN/A 1012623SN/A 10210030SAli.Saidi@ARM.com 1032623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1042623SN/A{ 1052623SN/A} 1062623SN/A 1072901Ssaidi@eecs.umich.eduunsigned int 1089342SAndreas.Sandberg@arm.comTimingSimpleCPU::drain(DrainManager *drain_manager) 1092798Sktlim@umich.edu{ 1109448SAndreas.Sandberg@ARM.com assert(!drainManager); 1119448SAndreas.Sandberg@ARM.com if (switchedOut()) 1129448SAndreas.Sandberg@ARM.com return 0; 1139448SAndreas.Sandberg@ARM.com 1149342SAndreas.Sandberg@arm.com if (_status == Idle || 1159448SAndreas.Sandberg@ARM.com (_status == BaseSimpleCPU::Running && isDrained())) { 1169442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "No need to drain.\n"); 1172901Ssaidi@eecs.umich.edu return 0; 1182798Sktlim@umich.edu } else { 1199342SAndreas.Sandberg@arm.com drainManager = drain_manager; 1209442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Requesting drain: %s\n", pcState()); 1219442SAndreas.Sandberg@ARM.com 1229442SAndreas.Sandberg@ARM.com // The fetch event can become descheduled if a drain didn't 1239442SAndreas.Sandberg@ARM.com // succeed on the first attempt. We need to reschedule it if 1249442SAndreas.Sandberg@ARM.com // the CPU is waiting for a microcode routine to complete. 1259448SAndreas.Sandberg@ARM.com if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 1269648Sdam.sunwoo@arm.com schedule(fetchEvent, clockEdge()); 1279442SAndreas.Sandberg@ARM.com 1282901Ssaidi@eecs.umich.edu return 1; 1292798Sktlim@umich.edu } 1302623SN/A} 1312623SN/A 1322623SN/Avoid 1339342SAndreas.Sandberg@arm.comTimingSimpleCPU::drainResume() 1342623SN/A{ 1359442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1369448SAndreas.Sandberg@ARM.com assert(!drainManager); 1379448SAndreas.Sandberg@ARM.com if (switchedOut()) 1389448SAndreas.Sandberg@ARM.com return; 1399442SAndreas.Sandberg@ARM.com 1405221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1419523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1423201Shsul@eecs.umich.edu 1439448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1449448SAndreas.Sandberg@ARM.com if (threadContexts.size() > 1) 1459448SAndreas.Sandberg@ARM.com fatal("The timing CPU only supports one thread.\n"); 1469448SAndreas.Sandberg@ARM.com 1479448SAndreas.Sandberg@ARM.com if (thread->status() == ThreadContext::Active) { 1485710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1499448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Running; 1509837Slena@cs.wisc,edu notIdleFraction = 1; 1519448SAndreas.Sandberg@ARM.com } else { 1529448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Idle; 1539837Slena@cs.wisc,edu notIdleFraction = 0; 1542623SN/A } 1559442SAndreas.Sandberg@ARM.com} 1562798Sktlim@umich.edu 1579442SAndreas.Sandberg@ARM.combool 1589442SAndreas.Sandberg@ARM.comTimingSimpleCPU::tryCompleteDrain() 1599442SAndreas.Sandberg@ARM.com{ 1609442SAndreas.Sandberg@ARM.com if (!drainManager) 1619442SAndreas.Sandberg@ARM.com return false; 1629442SAndreas.Sandberg@ARM.com 1639442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "tryCompleteDrain: %s\n", pcState()); 1649442SAndreas.Sandberg@ARM.com if (!isDrained()) 1659442SAndreas.Sandberg@ARM.com return false; 1669442SAndreas.Sandberg@ARM.com 1679442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 1689442SAndreas.Sandberg@ARM.com drainManager->signalDrainDone(); 1699442SAndreas.Sandberg@ARM.com drainManager = NULL; 1709442SAndreas.Sandberg@ARM.com 1719442SAndreas.Sandberg@ARM.com return true; 1722798Sktlim@umich.edu} 1732798Sktlim@umich.edu 1742798Sktlim@umich.eduvoid 1752798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1762798Sktlim@umich.edu{ 1779429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1789429SAndreas.Sandberg@ARM.com 1799442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1809342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 1819442SAndreas.Sandberg@ARM.com assert(!stayAtPC); 1829442SAndreas.Sandberg@ARM.com assert(microPC() == 0); 1839442SAndreas.Sandberg@ARM.com 18410464SAndreas.Sandberg@ARM.com updateCycleCounts(); 1852623SN/A} 1862623SN/A 1872623SN/A 1882623SN/Avoid 1892623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1902623SN/A{ 1919429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 1922623SN/A 1939179Sandreas.hansson@arm.com previousCycle = curCycle(); 1942623SN/A} 1952623SN/A 1969523SAndreas.Sandberg@ARM.comvoid 1979523SAndreas.Sandberg@ARM.comTimingSimpleCPU::verifyMemoryMode() const 1989523SAndreas.Sandberg@ARM.com{ 1999524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 2009523SAndreas.Sandberg@ARM.com fatal("The timing CPU requires the memory system to be in " 2019523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 2029523SAndreas.Sandberg@ARM.com } 2039523SAndreas.Sandberg@ARM.com} 2042623SN/A 2052623SN/Avoid 20610407Smitch.hayenga@arm.comTimingSimpleCPU::activateContext(ThreadID thread_num) 2072623SN/A{ 20810407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2095221Ssaidi@eecs.umich.edu 2102623SN/A assert(thread_num == 0); 2112683Sktlim@umich.edu assert(thread); 2122623SN/A 2132623SN/A assert(_status == Idle); 2142623SN/A 2159837Slena@cs.wisc,edu notIdleFraction = 1; 2169342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 2173686Sktlim@umich.edu 2182623SN/A // kick things off by initiating the fetch of the next instruction 21910407Smitch.hayenga@arm.com schedule(fetchEvent, clockEdge(Cycles(0))); 2202623SN/A} 2212623SN/A 2222623SN/A 2232623SN/Avoid 2248737Skoansin.tan@gmail.comTimingSimpleCPU::suspendContext(ThreadID thread_num) 2252623SN/A{ 2265221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2275221Ssaidi@eecs.umich.edu 2282623SN/A assert(thread_num == 0); 2292683Sktlim@umich.edu assert(thread); 2302623SN/A 2316043Sgblack@eecs.umich.edu if (_status == Idle) 2326043Sgblack@eecs.umich.edu return; 2336043Sgblack@eecs.umich.edu 2349342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2352623SN/A 2362644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2372644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2382623SN/A 2399837Slena@cs.wisc,edu notIdleFraction = 0; 2402623SN/A _status = Idle; 2412623SN/A} 2422623SN/A 2435728Sgblack@eecs.umich.edubool 2445728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2455728Sgblack@eecs.umich.edu{ 2465728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 24710533Sali.saidi@arm.com 24810533Sali.saidi@arm.com // We're about the issues a locked load, so tell the monitor 24910533Sali.saidi@arm.com // to start caring about this address 25010533Sali.saidi@arm.com if (pkt->isRead() && pkt->req->isLLSC()) { 25110533Sali.saidi@arm.com TheISA::handleLockedRead(thread, pkt->req); 25210533Sali.saidi@arm.com } 2538105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2549180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 2559179Sandreas.hansson@arm.com new IprEvent(pkt, this, clockEdge(delay)); 2565728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2575728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2588975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(pkt)) { 2595728Sgblack@eecs.umich.edu _status = DcacheRetry; 2605728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2615728Sgblack@eecs.umich.edu } else { 2625728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2635728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2645728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2655728Sgblack@eecs.umich.edu } 2665728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2675728Sgblack@eecs.umich.edu} 2682623SN/A 2695894Sgblack@eecs.umich.eduvoid 2706973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2716973Stjones1@inf.ed.ac.uk bool read) 2725744Sgblack@eecs.umich.edu{ 27310653Sandreas.hansson@arm.com PacketPtr pkt = buildPacket(req, read); 27410566Sandreas.hansson@arm.com pkt->dataDynamic<uint8_t>(data); 2755894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2765894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2775894Sgblack@eecs.umich.edu pkt->makeResponse(); 2785894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2795894Sgblack@eecs.umich.edu } else if (read) { 2805894Sgblack@eecs.umich.edu handleReadPacket(pkt); 2815894Sgblack@eecs.umich.edu } else { 2825894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 2835894Sgblack@eecs.umich.edu 2846102Sgblack@eecs.umich.edu if (req->isLLSC()) { 28510030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 2865894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 2875894Sgblack@eecs.umich.edu assert(res); 2885894Sgblack@eecs.umich.edu req->setExtraData(*res); 2895894Sgblack@eecs.umich.edu } 2905894Sgblack@eecs.umich.edu 2915894Sgblack@eecs.umich.edu if (do_access) { 2925894Sgblack@eecs.umich.edu dcache_pkt = pkt; 2935894Sgblack@eecs.umich.edu handleWritePacket(); 2945894Sgblack@eecs.umich.edu } else { 2955894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2965894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2975894Sgblack@eecs.umich.edu } 2985894Sgblack@eecs.umich.edu } 2995894Sgblack@eecs.umich.edu} 3005894Sgblack@eecs.umich.edu 3015894Sgblack@eecs.umich.eduvoid 3026973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 3036973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 3045894Sgblack@eecs.umich.edu{ 3055894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3065894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3075894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3085894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3095894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3105894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3115894Sgblack@eecs.umich.edu } else if (read) { 3127911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3137911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3145894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3155894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3167911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3177911Shestness@cs.utexas.edu pkt2->senderState); 3185894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3195894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3205894Sgblack@eecs.umich.edu } 3215894Sgblack@eecs.umich.edu } 3225894Sgblack@eecs.umich.edu } else { 3235894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3247911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3257911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3265894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3275894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3285894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3297911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3307911Shestness@cs.utexas.edu pkt2->senderState); 3315894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3325894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3335894Sgblack@eecs.umich.edu } 3345894Sgblack@eecs.umich.edu } 3355894Sgblack@eecs.umich.edu } 3365894Sgblack@eecs.umich.edu} 3375894Sgblack@eecs.umich.edu 3385894Sgblack@eecs.umich.eduvoid 33910379Sandreas.hansson@arm.comTimingSimpleCPU::translationFault(const Fault &fault) 3405894Sgblack@eecs.umich.edu{ 3416739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3426739Sgblack@eecs.umich.edu // for instance prefetches. 34310464SAndreas.Sandberg@ARM.com updateCycleCounts(); 3445894Sgblack@eecs.umich.edu 3455894Sgblack@eecs.umich.edu if (traceData) { 3465894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3475894Sgblack@eecs.umich.edu delete traceData; 3485894Sgblack@eecs.umich.edu traceData = NULL; 3495744Sgblack@eecs.umich.edu } 3505744Sgblack@eecs.umich.edu 3515894Sgblack@eecs.umich.edu postExecute(); 3525894Sgblack@eecs.umich.edu 3539442SAndreas.Sandberg@ARM.com advanceInst(fault); 3545894Sgblack@eecs.umich.edu} 3555894Sgblack@eecs.umich.edu 35610653Sandreas.hansson@arm.comPacketPtr 35710653Sandreas.hansson@arm.comTimingSimpleCPU::buildPacket(RequestPtr req, bool read) 3585894Sgblack@eecs.umich.edu{ 35910653Sandreas.hansson@arm.com return read ? Packet::createRead(req) : Packet::createWrite(req); 3605894Sgblack@eecs.umich.edu} 3615894Sgblack@eecs.umich.edu 3625894Sgblack@eecs.umich.eduvoid 3635894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3645894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 3655894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3665894Sgblack@eecs.umich.edu{ 3675894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3685894Sgblack@eecs.umich.edu 3698105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 3705744Sgblack@eecs.umich.edu 3715894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 37210653Sandreas.hansson@arm.com pkt1 = buildPacket(req, read); 3735894Sgblack@eecs.umich.edu return; 3745894Sgblack@eecs.umich.edu } 3755894Sgblack@eecs.umich.edu 37610653Sandreas.hansson@arm.com pkt1 = buildPacket(req1, read); 37710653Sandreas.hansson@arm.com pkt2 = buildPacket(req2, read); 3785894Sgblack@eecs.umich.edu 3798949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 3805744Sgblack@eecs.umich.edu 38110566Sandreas.hansson@arm.com pkt->dataDynamic<uint8_t>(data); 3825744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 3835744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 3845744Sgblack@eecs.umich.edu 3855744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 3865744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 3875744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 3885744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 3895744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 3905744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 3915744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 3925744Sgblack@eecs.umich.edu} 3935744Sgblack@eecs.umich.edu 3942623SN/AFault 3958444Sgblack@eecs.umich.eduTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 3968444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 3972623SN/A{ 3985728Sgblack@eecs.umich.edu Fault fault; 3995728Sgblack@eecs.umich.edu const int asid = 0; 4006221Snate@binkert.org const ThreadID tid = 0; 4017720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4029814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 4036973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4042623SN/A 40510665SAli.Saidi@ARM.com if (traceData) 40610665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 4077045Ssteve.reinhardt@amd.com 4087520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4098832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4105728Sgblack@eecs.umich.edu 41110024Sdam.sunwoo@arm.com req->taskId(taskId()); 41210024Sdam.sunwoo@arm.com 4137520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4145744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4155728Sgblack@eecs.umich.edu 4165894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4175744Sgblack@eecs.umich.edu if (split_addr > addr) { 4185894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4196102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4205894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4215894Sgblack@eecs.umich.edu 4226973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4237520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4246973Stjones1@inf.ed.ac.uk NULL, mode); 4258486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4268486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4278486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4288486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4296973Stjones1@inf.ed.ac.uk 4306973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 4316973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 4325744Sgblack@eecs.umich.edu } else { 4336973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4347520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4358486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4368486Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 4376973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 4382623SN/A } 4392623SN/A 4405728Sgblack@eecs.umich.edu return NoFault; 4412623SN/A} 4422623SN/A 4435728Sgblack@eecs.umich.edubool 4445728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4455728Sgblack@eecs.umich.edu{ 4465728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4478105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4489180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4499179Sandreas.hansson@arm.com new IprEvent(dcache_pkt, this, clockEdge(delay)); 4505728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4515728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4528975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 4535728Sgblack@eecs.umich.edu _status = DcacheRetry; 4545728Sgblack@eecs.umich.edu } else { 4555728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4565728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4575728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4585728Sgblack@eecs.umich.edu } 4595728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4605728Sgblack@eecs.umich.edu} 4612623SN/A 4622623SN/AFault 4638444Sgblack@eecs.umich.eduTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 4648444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 4652623SN/A{ 4668443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 4675728Sgblack@eecs.umich.edu const int asid = 0; 4686221Snate@binkert.org const ThreadID tid = 0; 4697720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4709814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 4716973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 4723169Sstever@eecs.umich.edu 47310031SAli.Saidi@ARM.com if (data == NULL) { 47410031SAli.Saidi@ARM.com assert(flags & Request::CACHE_BLOCK_ZERO); 47510031SAli.Saidi@ARM.com // This must be a cache block cleaning request 47610031SAli.Saidi@ARM.com memset(newData, 0, size); 47710031SAli.Saidi@ARM.com } else { 47810031SAli.Saidi@ARM.com memcpy(newData, data, size); 47910031SAli.Saidi@ARM.com } 48010031SAli.Saidi@ARM.com 48110665SAli.Saidi@ARM.com if (traceData) 48210665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 4837045Ssteve.reinhardt@amd.com 4847520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4858832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4865728Sgblack@eecs.umich.edu 48710024Sdam.sunwoo@arm.com req->taskId(taskId()); 48810024Sdam.sunwoo@arm.com 4897520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4905744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4915728Sgblack@eecs.umich.edu 4925894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4935744Sgblack@eecs.umich.edu if (split_addr > addr) { 4945894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4956102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4965894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4975894Sgblack@eecs.umich.edu 4986973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4998443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 5008486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 5018486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 5028486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 5038486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 5046973Stjones1@inf.ed.ac.uk 5056973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 5066973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 5075744Sgblack@eecs.umich.edu } else { 5086973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5098443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5108486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation = 5118486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state); 5126973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 5132623SN/A } 5142623SN/A 5157045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5165728Sgblack@eecs.umich.edu return NoFault; 5172623SN/A} 5182623SN/A 5192623SN/A 5202623SN/Avoid 5216973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5226973Stjones1@inf.ed.ac.uk{ 5239342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5246973Stjones1@inf.ed.ac.uk 5256973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 5266973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 5276973Stjones1@inf.ed.ac.uk state->setNoFault(); 5286973Stjones1@inf.ed.ac.uk } 5297691SAli.Saidi@ARM.com delete [] state->data; 5306973Stjones1@inf.ed.ac.uk state->deleteReqs(); 5316973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 5326973Stjones1@inf.ed.ac.uk } else { 5336973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 5346973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 5356973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 5366973Stjones1@inf.ed.ac.uk } else { 5376973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5386973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 5396973Stjones1@inf.ed.ac.uk } 5406973Stjones1@inf.ed.ac.uk } 5416973Stjones1@inf.ed.ac.uk 5426973Stjones1@inf.ed.ac.uk delete state; 5436973Stjones1@inf.ed.ac.uk} 5446973Stjones1@inf.ed.ac.uk 5456973Stjones1@inf.ed.ac.uk 5466973Stjones1@inf.ed.ac.ukvoid 5472623SN/ATimingSimpleCPU::fetch() 5482623SN/A{ 5495221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5505221Ssaidi@eecs.umich.edu 55110596Sgabeblack@google.com if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 5523387Sgblack@eecs.umich.edu checkForInterrupts(); 55310596Sgabeblack@google.com checkPcEventQueue(); 55410596Sgabeblack@google.com } 5555348Ssaidi@eecs.umich.edu 5568143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5578143SAli.Saidi@ARM.com if (_status == Idle) 5588143SAli.Saidi@ARM.com return; 5598143SAli.Saidi@ARM.com 5607720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5617720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 5622623SN/A 5637720Sgblack@eecs.umich.edu if (needToFetch) { 5649342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5655669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 56610024Sdam.sunwoo@arm.com ifetch_req->taskId(taskId()); 5675712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 5685894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 5698277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 5706023Snate@binkert.org thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 5716023Snate@binkert.org BaseTLB::Execute); 5722623SN/A } else { 5735669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5745669Sgblack@eecs.umich.edu completeIfetch(NULL); 5755894Sgblack@eecs.umich.edu 57610464SAndreas.Sandberg@ARM.com updateCycleCounts(); 5775894Sgblack@eecs.umich.edu } 5785894Sgblack@eecs.umich.edu} 5795894Sgblack@eecs.umich.edu 5805894Sgblack@eecs.umich.edu 5815894Sgblack@eecs.umich.eduvoid 58210379Sandreas.hansson@arm.comTimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, 58310379Sandreas.hansson@arm.com ThreadContext *tc) 5845894Sgblack@eecs.umich.edu{ 5855894Sgblack@eecs.umich.edu if (fault == NoFault) { 5868277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 5878277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 5888949Sandreas.hansson@arm.com ifetch_pkt = new Packet(req, MemCmd::ReadReq); 5895894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 5908277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 5915894Sgblack@eecs.umich.edu 5928975Sandreas.hansson@arm.com if (!icachePort.sendTimingReq(ifetch_pkt)) { 5935894Sgblack@eecs.umich.edu // Need to wait for retry 5945894Sgblack@eecs.umich.edu _status = IcacheRetry; 5955894Sgblack@eecs.umich.edu } else { 5965894Sgblack@eecs.umich.edu // Need to wait for cache to respond 5975894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5985894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 5995894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 6005894Sgblack@eecs.umich.edu } 6015894Sgblack@eecs.umich.edu } else { 6028277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 6035894Sgblack@eecs.umich.edu delete req; 6045894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 6059342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6065894Sgblack@eecs.umich.edu advanceInst(fault); 6072623SN/A } 6083222Sktlim@umich.edu 60910464SAndreas.Sandberg@ARM.com updateCycleCounts(); 6102623SN/A} 6112623SN/A 6122623SN/A 6132623SN/Avoid 61410379Sandreas.hansson@arm.comTimingSimpleCPU::advanceInst(const Fault &fault) 6152623SN/A{ 6168276SAli.Saidi@ARM.com if (_status == Faulting) 6178276SAli.Saidi@ARM.com return; 6188276SAli.Saidi@ARM.com 6198276SAli.Saidi@ARM.com if (fault != NoFault) { 6208276SAli.Saidi@ARM.com advancePC(fault); 6218276SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 6229648Sdam.sunwoo@arm.com reschedule(fetchEvent, clockEdge(), true); 6238276SAli.Saidi@ARM.com _status = Faulting; 6248276SAli.Saidi@ARM.com return; 6258276SAli.Saidi@ARM.com } 6268276SAli.Saidi@ARM.com 6278276SAli.Saidi@ARM.com 6288276SAli.Saidi@ARM.com if (!stayAtPC) 6295726Sgblack@eecs.umich.edu advancePC(fault); 6302623SN/A 6319442SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6329442SAndreas.Sandberg@ARM.com return; 6339442SAndreas.Sandberg@ARM.com 6349342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6352631SN/A // kick off fetch of next instruction... callback from icache 6362631SN/A // response will cause that instruction to be executed, 6372631SN/A // keeping the CPU running. 6382631SN/A fetch(); 6392631SN/A } 6402623SN/A} 6412623SN/A 6422623SN/A 6432623SN/Avoid 6443349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 6452623SN/A{ 6468277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 6478277SAli.Saidi@ARM.com pkt->getAddr() : 0); 6488277SAli.Saidi@ARM.com 6492623SN/A // received a response from the icache: execute the received 6502623SN/A // instruction 6515669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 6522623SN/A assert(_status == IcacheWaitResponse); 6532798Sktlim@umich.edu 6549342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6552644Sstever@eecs.umich.edu 65610464SAndreas.Sandberg@ARM.com updateCycleCounts(); 6573222Sktlim@umich.edu 65810020Smatt.horsnell@ARM.com if (pkt) 65910020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 66010020Smatt.horsnell@ARM.com 66110020Smatt.horsnell@ARM.com 6622623SN/A preExecute(); 6637725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 6642623SN/A // load or store: just send to dcache 6652623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 6667945SAli.Saidi@ARM.com 6677945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 6687945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 6697945SAli.Saidi@ARM.com // ifetch 6709342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6715894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 6725001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6735001Sgblack@eecs.umich.edu delete traceData; 6745001Sgblack@eecs.umich.edu traceData = NULL; 6753170Sstever@eecs.umich.edu } 6764998Sgblack@eecs.umich.edu 6772644Sstever@eecs.umich.edu postExecute(); 6785103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6795103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6805103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6815103Ssaidi@eecs.umich.edu instCnt++; 6822644Sstever@eecs.umich.edu advanceInst(fault); 6832644Sstever@eecs.umich.edu } 6845726Sgblack@eecs.umich.edu } else if (curStaticInst) { 6852623SN/A // non-memory instruction: execute completely now 6862623SN/A Fault fault = curStaticInst->execute(this, traceData); 6874998Sgblack@eecs.umich.edu 6884998Sgblack@eecs.umich.edu // keep an instruction count 6894998Sgblack@eecs.umich.edu if (fault == NoFault) 6904998Sgblack@eecs.umich.edu countInst(); 6917655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 6925001Sgblack@eecs.umich.edu delete traceData; 6935001Sgblack@eecs.umich.edu traceData = NULL; 6945001Sgblack@eecs.umich.edu } 6954998Sgblack@eecs.umich.edu 6962644Sstever@eecs.umich.edu postExecute(); 6975103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6985103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6995103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7005103Ssaidi@eecs.umich.edu instCnt++; 7012644Sstever@eecs.umich.edu advanceInst(fault); 7025726Sgblack@eecs.umich.edu } else { 7035726Sgblack@eecs.umich.edu advanceInst(NoFault); 7042623SN/A } 7053658Sktlim@umich.edu 7065669Sgblack@eecs.umich.edu if (pkt) { 7075669Sgblack@eecs.umich.edu delete pkt->req; 7085669Sgblack@eecs.umich.edu delete pkt; 7095669Sgblack@eecs.umich.edu } 7102623SN/A} 7112623SN/A 7122948Ssaidi@eecs.umich.eduvoid 7132948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7142948Ssaidi@eecs.umich.edu{ 7152948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7162948Ssaidi@eecs.umich.edu} 7172623SN/A 7182623SN/Abool 7198975Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 7202623SN/A{ 72110669Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr()); 72210669Sandreas.hansson@arm.com // we should only ever see one response per cycle since we only 72310669Sandreas.hansson@arm.com // issue a new request once this response is sunk 72410669Sandreas.hansson@arm.com assert(!tickEvent.scheduled()); 7259165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 72610669Sandreas.hansson@arm.com tickEvent.schedule(pkt, cpu->clockEdge()); 7278948Sandreas.hansson@arm.com 7284433Ssaidi@eecs.umich.edu return true; 7292623SN/A} 7302623SN/A 7312657Ssaidi@eecs.umich.eduvoid 73210713Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvReqRetry() 7332623SN/A{ 7342623SN/A // we shouldn't get a retry unless we have a packet that we're 7352623SN/A // waiting to transmit 7362623SN/A assert(cpu->ifetch_pkt != NULL); 7372623SN/A assert(cpu->_status == IcacheRetry); 7383349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7398975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 7402657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7412657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7422657Ssaidi@eecs.umich.edu } 7432623SN/A} 7442623SN/A 7452623SN/Avoid 7463349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 7472623SN/A{ 7482623SN/A // received a response from the dcache: complete the load or store 7492623SN/A // instruction 7504870Sstever@eecs.umich.edu assert(!pkt->isError()); 7517516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 7527516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 7532623SN/A 75410020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 75510464SAndreas.Sandberg@ARM.com 75610464SAndreas.Sandberg@ARM.com updateCycleCounts(); 7573184Srdreslin@umich.edu 7585728Sgblack@eecs.umich.edu if (pkt->senderState) { 7595728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 7605728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 7615728Sgblack@eecs.umich.edu assert(send_state); 7625728Sgblack@eecs.umich.edu delete pkt->req; 7635728Sgblack@eecs.umich.edu delete pkt; 7645728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 7655728Sgblack@eecs.umich.edu delete send_state; 7665728Sgblack@eecs.umich.edu 7675728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 7685728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 7695728Sgblack@eecs.umich.edu assert(main_send_state); 7705728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 7715728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 7725728Sgblack@eecs.umich.edu main_send_state->outstanding--; 7735728Sgblack@eecs.umich.edu 7745728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 7755728Sgblack@eecs.umich.edu return; 7765728Sgblack@eecs.umich.edu } else { 7775728Sgblack@eecs.umich.edu delete main_send_state; 7785728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 7795728Sgblack@eecs.umich.edu pkt = big_pkt; 7805728Sgblack@eecs.umich.edu } 7815728Sgblack@eecs.umich.edu } 7825728Sgblack@eecs.umich.edu 7839342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 7845728Sgblack@eecs.umich.edu 7852623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 7862623SN/A 7874998Sgblack@eecs.umich.edu // keep an instruction count 7884998Sgblack@eecs.umich.edu if (fault == NoFault) 7894998Sgblack@eecs.umich.edu countInst(); 7905001Sgblack@eecs.umich.edu else if (traceData) { 7915001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7925001Sgblack@eecs.umich.edu delete traceData; 7935001Sgblack@eecs.umich.edu traceData = NULL; 7945001Sgblack@eecs.umich.edu } 7954998Sgblack@eecs.umich.edu 7962644Sstever@eecs.umich.edu delete pkt->req; 7972644Sstever@eecs.umich.edu delete pkt; 7982644Sstever@eecs.umich.edu 7993184Srdreslin@umich.edu postExecute(); 8003227Sktlim@umich.edu 8012644Sstever@eecs.umich.edu advanceInst(fault); 8022623SN/A} 8032623SN/A 80410030SAli.Saidi@ARM.comvoid 80510464SAndreas.Sandberg@ARM.comTimingSimpleCPU::updateCycleCounts() 80610464SAndreas.Sandberg@ARM.com{ 80710464SAndreas.Sandberg@ARM.com const Cycles delta(curCycle() - previousCycle); 80810464SAndreas.Sandberg@ARM.com 80910464SAndreas.Sandberg@ARM.com numCycles += delta; 81010464SAndreas.Sandberg@ARM.com ppCycles->notify(delta); 81110464SAndreas.Sandberg@ARM.com 81210464SAndreas.Sandberg@ARM.com previousCycle = curCycle(); 81310464SAndreas.Sandberg@ARM.com} 81410464SAndreas.Sandberg@ARM.com 81510464SAndreas.Sandberg@ARM.comvoid 81610030SAli.Saidi@ARM.comTimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 81710030SAli.Saidi@ARM.com{ 81810529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 81910529Smorr@cs.wisc.edu if(cpu->getAddrMonitor()->doMonitor(pkt)) { 82010529Smorr@cs.wisc.edu cpu->wakeup(); 82110529Smorr@cs.wisc.edu } 82210030SAli.Saidi@ARM.com TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 82310030SAli.Saidi@ARM.com} 82410030SAli.Saidi@ARM.com 82510529Smorr@cs.wisc.eduvoid 82610529Smorr@cs.wisc.eduTimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) 82710529Smorr@cs.wisc.edu{ 82810529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 82910529Smorr@cs.wisc.edu if(cpu->getAddrMonitor()->doMonitor(pkt)) { 83010529Smorr@cs.wisc.edu cpu->wakeup(); 83110529Smorr@cs.wisc.edu } 83210529Smorr@cs.wisc.edu} 83310030SAli.Saidi@ARM.com 8342623SN/Abool 8358975Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 8362623SN/A{ 83710669Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr()); 8382948Ssaidi@eecs.umich.edu 83910669Sandreas.hansson@arm.com // The timing CPU is not really ticked, instead it relies on the 84010669Sandreas.hansson@arm.com // memory system (fetch and load/store) to set the pace. 84110669Sandreas.hansson@arm.com if (!tickEvent.scheduled()) { 84210669Sandreas.hansson@arm.com // Delay processing of returned data until next CPU clock edge 84310669Sandreas.hansson@arm.com tickEvent.schedule(pkt, cpu->clockEdge()); 84410669Sandreas.hansson@arm.com return true; 8459165Sandreas.hansson@arm.com } else { 84610669Sandreas.hansson@arm.com // In the case of a split transaction and a cache that is 84710669Sandreas.hansson@arm.com // faster than a CPU we could get two responses in the 84810669Sandreas.hansson@arm.com // same tick, delay the second one 84910713Sandreas.hansson@arm.com if (!retryRespEvent.scheduled()) 85010713Sandreas.hansson@arm.com cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1))); 85110669Sandreas.hansson@arm.com return false; 8523310Srdreslin@umich.edu } 8532948Ssaidi@eecs.umich.edu} 8542948Ssaidi@eecs.umich.edu 8552948Ssaidi@eecs.umich.eduvoid 8562948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 8572948Ssaidi@eecs.umich.edu{ 8582630SN/A cpu->completeDataAccess(pkt); 8592623SN/A} 8602623SN/A 8612657Ssaidi@eecs.umich.eduvoid 86210713Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvReqRetry() 8632623SN/A{ 8642623SN/A // we shouldn't get a retry unless we have a packet that we're 8652623SN/A // waiting to transmit 8662623SN/A assert(cpu->dcache_pkt != NULL); 8672623SN/A assert(cpu->_status == DcacheRetry); 8683349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 8695728Sgblack@eecs.umich.edu if (tmp->senderState) { 8705728Sgblack@eecs.umich.edu // This is a packet from a split access. 8715728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8725728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 8735728Sgblack@eecs.umich.edu assert(send_state); 8745728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8755728Sgblack@eecs.umich.edu 8765728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8775728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8785728Sgblack@eecs.umich.edu assert(main_send_state); 8795728Sgblack@eecs.umich.edu 8808975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 8815728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 8825728Sgblack@eecs.umich.edu // and try sending the other fragment. 8835728Sgblack@eecs.umich.edu send_state->clearFromParent(); 8845728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 8855728Sgblack@eecs.umich.edu if (other_index > 0) { 8865728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 8875728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 8885728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 8895728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 8905728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 8915728Sgblack@eecs.umich.edu } 8925728Sgblack@eecs.umich.edu } else { 8935728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 8945728Sgblack@eecs.umich.edu // memory system takes ownership of packet 8955728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 8965728Sgblack@eecs.umich.edu } 8975728Sgblack@eecs.umich.edu } 8988975Sandreas.hansson@arm.com } else if (sendTimingReq(tmp)) { 8992657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9003170Sstever@eecs.umich.edu // memory system takes ownership of packet 9012657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 9022657Ssaidi@eecs.umich.edu } 9032623SN/A} 9042623SN/A 9055606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 9065606Snate@binkert.org Tick t) 9075606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 9085103Ssaidi@eecs.umich.edu{ 9095606Snate@binkert.org cpu->schedule(this, t); 9105103Ssaidi@eecs.umich.edu} 9115103Ssaidi@eecs.umich.edu 9125103Ssaidi@eecs.umich.eduvoid 9135103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 9145103Ssaidi@eecs.umich.edu{ 9155103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 9165103Ssaidi@eecs.umich.edu} 9175103Ssaidi@eecs.umich.edu 9185103Ssaidi@eecs.umich.educonst char * 9195336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 9205103Ssaidi@eecs.umich.edu{ 9215103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 9225103Ssaidi@eecs.umich.edu} 9235103Ssaidi@eecs.umich.edu 9242623SN/A 9255315Sstever@gmail.comvoid 9265315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 9275315Sstever@gmail.com{ 9285315Sstever@gmail.com dcachePort.printAddr(a); 9295315Sstever@gmail.com} 9305315Sstever@gmail.com 9315315Sstever@gmail.com 9322623SN/A//////////////////////////////////////////////////////////////////////// 9332623SN/A// 9342623SN/A// TimingSimpleCPU Simulation Object 9352623SN/A// 9364762Snate@binkert.orgTimingSimpleCPU * 9374762Snate@binkert.orgTimingSimpleCPUParams::create() 9382623SN/A{ 9395529Snate@binkert.org numThreads = 1; 9408779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 9414762Snate@binkert.org panic("only one workload allowed"); 9425529Snate@binkert.org return new TimingSimpleCPU(this); 9432623SN/A} 944