timing.cc revision 10596
12623SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 310030SAli.Saidi@ARM.com * Copyright (c) 2010-2013 ARM Limited 47725SAli.Saidi@ARM.com * All rights reserved 57725SAli.Saidi@ARM.com * 67725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147725SAli.Saidi@ARM.com * 152623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162623SN/A * All rights reserved. 172623SN/A * 182623SN/A * Redistribution and use in source and binary forms, with or without 192623SN/A * modification, are permitted provided that the following conditions are 202623SN/A * met: redistributions of source code must retain the above copyright 212623SN/A * notice, this list of conditions and the following disclaimer; 222623SN/A * redistributions in binary form must reproduce the above copyright 232623SN/A * notice, this list of conditions and the following disclaimer in the 242623SN/A * documentation and/or other materials provided with the distribution; 252623SN/A * neither the name of the copyright holders nor the names of its 262623SN/A * contributors may be used to endorse or promote products derived from 272623SN/A * this software without specific prior written permission. 282623SN/A * 292623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422623SN/A */ 432623SN/A 443170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 458105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 462623SN/A#include "arch/utility.hh" 474040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 498229Snate@binkert.org#include "cpu/simple/timing.hh" 502623SN/A#include "cpu/exetrace.hh" 518232Snate@binkert.org#include "debug/Config.hh" 529152Satgutier@umich.edu#include "debug/Drain.hh" 538232Snate@binkert.org#include "debug/ExecFaulting.hh" 548232Snate@binkert.org#include "debug/SimpleCPU.hh" 553348Sbinkertn@umich.edu#include "mem/packet.hh" 563348Sbinkertn@umich.edu#include "mem/packet_access.hh" 574762Snate@binkert.org#include "params/TimingSimpleCPU.hh" 587678Sgblack@eecs.umich.edu#include "sim/faults.hh" 598779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 602901Ssaidi@eecs.umich.edu#include "sim/system.hh" 612623SN/A 6210529Smorr@cs.wisc.edu#include "debug/Mwait.hh" 6310529Smorr@cs.wisc.edu 642623SN/Ausing namespace std; 652623SN/Ausing namespace TheISA; 662623SN/A 672623SN/Avoid 682623SN/ATimingSimpleCPU::init() 692623SN/A{ 702623SN/A BaseCPU::init(); 718921Sandreas.hansson@arm.com 728921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 738921Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 748921Sandreas.hansson@arm.com 759433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 768779Sgblack@eecs.umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 778779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 788779Sgblack@eecs.umich.edu // initialize CPU, including PC 798779Sgblack@eecs.umich.edu TheISA::initCPU(tc, _cpuId); 808779Sgblack@eecs.umich.edu } 812623SN/A } 822623SN/A} 832623SN/A 842623SN/Avoid 858707Sandreas.hansson@arm.comTimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 862948Ssaidi@eecs.umich.edu{ 872948Ssaidi@eecs.umich.edu pkt = _pkt; 885606Snate@binkert.org cpu->schedule(this, t); 892948Ssaidi@eecs.umich.edu} 902948Ssaidi@eecs.umich.edu 915529Snate@binkert.orgTimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) 928707Sandreas.hansson@arm.com : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 939179Sandreas.hansson@arm.com dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), 949442SAndreas.Sandberg@ARM.com fetchEvent(this), drainManager(NULL) 952623SN/A{ 962623SN/A _status = Idle; 973647Srdreslin@umich.edu 987897Shestness@cs.utexas.edu system->totalNumInsts = 0; 992623SN/A} 1002623SN/A 1012623SN/A 10210030SAli.Saidi@ARM.com 1032623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1042623SN/A{ 1052623SN/A} 1062623SN/A 1072901Ssaidi@eecs.umich.eduunsigned int 1089342SAndreas.Sandberg@arm.comTimingSimpleCPU::drain(DrainManager *drain_manager) 1092798Sktlim@umich.edu{ 1109448SAndreas.Sandberg@ARM.com assert(!drainManager); 1119448SAndreas.Sandberg@ARM.com if (switchedOut()) 1129448SAndreas.Sandberg@ARM.com return 0; 1139448SAndreas.Sandberg@ARM.com 1149342SAndreas.Sandberg@arm.com if (_status == Idle || 1159448SAndreas.Sandberg@ARM.com (_status == BaseSimpleCPU::Running && isDrained())) { 1169442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "No need to drain.\n"); 1172901Ssaidi@eecs.umich.edu return 0; 1182798Sktlim@umich.edu } else { 1199342SAndreas.Sandberg@arm.com drainManager = drain_manager; 1209442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Requesting drain: %s\n", pcState()); 1219442SAndreas.Sandberg@ARM.com 1229442SAndreas.Sandberg@ARM.com // The fetch event can become descheduled if a drain didn't 1239442SAndreas.Sandberg@ARM.com // succeed on the first attempt. We need to reschedule it if 1249442SAndreas.Sandberg@ARM.com // the CPU is waiting for a microcode routine to complete. 1259448SAndreas.Sandberg@ARM.com if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) 1269648Sdam.sunwoo@arm.com schedule(fetchEvent, clockEdge()); 1279442SAndreas.Sandberg@ARM.com 1282901Ssaidi@eecs.umich.edu return 1; 1292798Sktlim@umich.edu } 1302623SN/A} 1312623SN/A 1322623SN/Avoid 1339342SAndreas.Sandberg@arm.comTimingSimpleCPU::drainResume() 1342623SN/A{ 1359442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1369448SAndreas.Sandberg@ARM.com assert(!drainManager); 1379448SAndreas.Sandberg@ARM.com if (switchedOut()) 1389448SAndreas.Sandberg@ARM.com return; 1399442SAndreas.Sandberg@ARM.com 1405221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1419523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1423201Shsul@eecs.umich.edu 1439448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1449448SAndreas.Sandberg@ARM.com if (threadContexts.size() > 1) 1459448SAndreas.Sandberg@ARM.com fatal("The timing CPU only supports one thread.\n"); 1469448SAndreas.Sandberg@ARM.com 1479448SAndreas.Sandberg@ARM.com if (thread->status() == ThreadContext::Active) { 1485710Scws3k@cs.virginia.edu schedule(fetchEvent, nextCycle()); 1499448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Running; 1509837Slena@cs.wisc,edu notIdleFraction = 1; 1519448SAndreas.Sandberg@ARM.com } else { 1529448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Idle; 1539837Slena@cs.wisc,edu notIdleFraction = 0; 1542623SN/A } 1559442SAndreas.Sandberg@ARM.com} 1562798Sktlim@umich.edu 1579442SAndreas.Sandberg@ARM.combool 1589442SAndreas.Sandberg@ARM.comTimingSimpleCPU::tryCompleteDrain() 1599442SAndreas.Sandberg@ARM.com{ 1609442SAndreas.Sandberg@ARM.com if (!drainManager) 1619442SAndreas.Sandberg@ARM.com return false; 1629442SAndreas.Sandberg@ARM.com 1639442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "tryCompleteDrain: %s\n", pcState()); 1649442SAndreas.Sandberg@ARM.com if (!isDrained()) 1659442SAndreas.Sandberg@ARM.com return false; 1669442SAndreas.Sandberg@ARM.com 1679442SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 1689442SAndreas.Sandberg@ARM.com drainManager->signalDrainDone(); 1699442SAndreas.Sandberg@ARM.com drainManager = NULL; 1709442SAndreas.Sandberg@ARM.com 1719442SAndreas.Sandberg@ARM.com return true; 1722798Sktlim@umich.edu} 1732798Sktlim@umich.edu 1742798Sktlim@umich.eduvoid 1752798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1762798Sktlim@umich.edu{ 1779429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1789429SAndreas.Sandberg@ARM.com 1799442SAndreas.Sandberg@ARM.com assert(!fetchEvent.scheduled()); 1809342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 1819442SAndreas.Sandberg@ARM.com assert(!stayAtPC); 1829442SAndreas.Sandberg@ARM.com assert(microPC() == 0); 1839442SAndreas.Sandberg@ARM.com 18410464SAndreas.Sandberg@ARM.com updateCycleCounts(); 1852623SN/A} 1862623SN/A 1872623SN/A 1882623SN/Avoid 1892623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1902623SN/A{ 1919429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 1922623SN/A 1939179Sandreas.hansson@arm.com previousCycle = curCycle(); 1942623SN/A} 1952623SN/A 1969523SAndreas.Sandberg@ARM.comvoid 1979523SAndreas.Sandberg@ARM.comTimingSimpleCPU::verifyMemoryMode() const 1989523SAndreas.Sandberg@ARM.com{ 1999524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 2009523SAndreas.Sandberg@ARM.com fatal("The timing CPU requires the memory system to be in " 2019523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 2029523SAndreas.Sandberg@ARM.com } 2039523SAndreas.Sandberg@ARM.com} 2042623SN/A 2052623SN/Avoid 20610407Smitch.hayenga@arm.comTimingSimpleCPU::activateContext(ThreadID thread_num) 2072623SN/A{ 20810407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2095221Ssaidi@eecs.umich.edu 2102623SN/A assert(thread_num == 0); 2112683Sktlim@umich.edu assert(thread); 2122623SN/A 2132623SN/A assert(_status == Idle); 2142623SN/A 2159837Slena@cs.wisc,edu notIdleFraction = 1; 2169342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 2173686Sktlim@umich.edu 2182623SN/A // kick things off by initiating the fetch of the next instruction 21910407Smitch.hayenga@arm.com schedule(fetchEvent, clockEdge(Cycles(0))); 2202623SN/A} 2212623SN/A 2222623SN/A 2232623SN/Avoid 2248737Skoansin.tan@gmail.comTimingSimpleCPU::suspendContext(ThreadID thread_num) 2252623SN/A{ 2265221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2275221Ssaidi@eecs.umich.edu 2282623SN/A assert(thread_num == 0); 2292683Sktlim@umich.edu assert(thread); 2302623SN/A 2316043Sgblack@eecs.umich.edu if (_status == Idle) 2326043Sgblack@eecs.umich.edu return; 2336043Sgblack@eecs.umich.edu 2349342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2352623SN/A 2362644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2372644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2382623SN/A 2399837Slena@cs.wisc,edu notIdleFraction = 0; 2402623SN/A _status = Idle; 2412623SN/A} 2422623SN/A 2435728Sgblack@eecs.umich.edubool 2445728Sgblack@eecs.umich.eduTimingSimpleCPU::handleReadPacket(PacketPtr pkt) 2455728Sgblack@eecs.umich.edu{ 2465728Sgblack@eecs.umich.edu RequestPtr req = pkt->req; 24710533Sali.saidi@arm.com 24810533Sali.saidi@arm.com // We're about the issues a locked load, so tell the monitor 24910533Sali.saidi@arm.com // to start caring about this address 25010533Sali.saidi@arm.com if (pkt->isRead() && pkt->req->isLLSC()) { 25110533Sali.saidi@arm.com TheISA::handleLockedRead(thread, pkt->req); 25210533Sali.saidi@arm.com } 2538105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 2549180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); 2559179Sandreas.hansson@arm.com new IprEvent(pkt, this, clockEdge(delay)); 2565728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2575728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2588975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(pkt)) { 2595728Sgblack@eecs.umich.edu _status = DcacheRetry; 2605728Sgblack@eecs.umich.edu dcache_pkt = pkt; 2615728Sgblack@eecs.umich.edu } else { 2625728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2635728Sgblack@eecs.umich.edu // memory system takes ownership of packet 2645728Sgblack@eecs.umich.edu dcache_pkt = NULL; 2655728Sgblack@eecs.umich.edu } 2665728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 2675728Sgblack@eecs.umich.edu} 2682623SN/A 2695894Sgblack@eecs.umich.eduvoid 2706973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 2716973Stjones1@inf.ed.ac.uk bool read) 2725744Sgblack@eecs.umich.edu{ 2735894Sgblack@eecs.umich.edu PacketPtr pkt; 2745894Sgblack@eecs.umich.edu buildPacket(pkt, req, read); 27510566Sandreas.hansson@arm.com pkt->dataDynamic<uint8_t>(data); 2765894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 2775894Sgblack@eecs.umich.edu assert(!dcache_pkt); 2785894Sgblack@eecs.umich.edu pkt->makeResponse(); 2795894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2805894Sgblack@eecs.umich.edu } else if (read) { 2815894Sgblack@eecs.umich.edu handleReadPacket(pkt); 2825894Sgblack@eecs.umich.edu } else { 2835894Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 2845894Sgblack@eecs.umich.edu 2856102Sgblack@eecs.umich.edu if (req->isLLSC()) { 28610030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 2875894Sgblack@eecs.umich.edu } else if (req->isCondSwap()) { 2885894Sgblack@eecs.umich.edu assert(res); 2895894Sgblack@eecs.umich.edu req->setExtraData(*res); 2905894Sgblack@eecs.umich.edu } 2915894Sgblack@eecs.umich.edu 2925894Sgblack@eecs.umich.edu if (do_access) { 2935894Sgblack@eecs.umich.edu dcache_pkt = pkt; 2945894Sgblack@eecs.umich.edu handleWritePacket(); 2955894Sgblack@eecs.umich.edu } else { 2965894Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 2975894Sgblack@eecs.umich.edu completeDataAccess(pkt); 2985894Sgblack@eecs.umich.edu } 2995894Sgblack@eecs.umich.edu } 3005894Sgblack@eecs.umich.edu} 3015894Sgblack@eecs.umich.edu 3025894Sgblack@eecs.umich.eduvoid 3036973Stjones1@inf.ed.ac.ukTimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, 3046973Stjones1@inf.ed.ac.uk RequestPtr req, uint8_t *data, bool read) 3055894Sgblack@eecs.umich.edu{ 3065894Sgblack@eecs.umich.edu PacketPtr pkt1, pkt2; 3075894Sgblack@eecs.umich.edu buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); 3085894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3095894Sgblack@eecs.umich.edu assert(!dcache_pkt); 3105894Sgblack@eecs.umich.edu pkt1->makeResponse(); 3115894Sgblack@eecs.umich.edu completeDataAccess(pkt1); 3125894Sgblack@eecs.umich.edu } else if (read) { 3137911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3147911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3155894Sgblack@eecs.umich.edu if (handleReadPacket(pkt1)) { 3165894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3177911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3187911Shestness@cs.utexas.edu pkt2->senderState); 3195894Sgblack@eecs.umich.edu if (handleReadPacket(pkt2)) { 3205894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3215894Sgblack@eecs.umich.edu } 3225894Sgblack@eecs.umich.edu } 3235894Sgblack@eecs.umich.edu } else { 3245894Sgblack@eecs.umich.edu dcache_pkt = pkt1; 3257911Shestness@cs.utexas.edu SplitFragmentSenderState * send_state = 3267911Shestness@cs.utexas.edu dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState); 3275894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3285894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3295894Sgblack@eecs.umich.edu dcache_pkt = pkt2; 3307911Shestness@cs.utexas.edu send_state = dynamic_cast<SplitFragmentSenderState *>( 3317911Shestness@cs.utexas.edu pkt2->senderState); 3325894Sgblack@eecs.umich.edu if (handleWritePacket()) { 3335894Sgblack@eecs.umich.edu send_state->clearFromParent(); 3345894Sgblack@eecs.umich.edu } 3355894Sgblack@eecs.umich.edu } 3365894Sgblack@eecs.umich.edu } 3375894Sgblack@eecs.umich.edu} 3385894Sgblack@eecs.umich.edu 3395894Sgblack@eecs.umich.eduvoid 34010379Sandreas.hansson@arm.comTimingSimpleCPU::translationFault(const Fault &fault) 3415894Sgblack@eecs.umich.edu{ 3426739Sgblack@eecs.umich.edu // fault may be NoFault in cases where a fault is suppressed, 3436739Sgblack@eecs.umich.edu // for instance prefetches. 34410464SAndreas.Sandberg@ARM.com updateCycleCounts(); 3455894Sgblack@eecs.umich.edu 3465894Sgblack@eecs.umich.edu if (traceData) { 3475894Sgblack@eecs.umich.edu // Since there was a fault, we shouldn't trace this instruction. 3485894Sgblack@eecs.umich.edu delete traceData; 3495894Sgblack@eecs.umich.edu traceData = NULL; 3505744Sgblack@eecs.umich.edu } 3515744Sgblack@eecs.umich.edu 3525894Sgblack@eecs.umich.edu postExecute(); 3535894Sgblack@eecs.umich.edu 3549442SAndreas.Sandberg@ARM.com advanceInst(fault); 3555894Sgblack@eecs.umich.edu} 3565894Sgblack@eecs.umich.edu 3575894Sgblack@eecs.umich.eduvoid 3585894Sgblack@eecs.umich.eduTimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 3595894Sgblack@eecs.umich.edu{ 36010342SCurtis.Dunham@arm.com pkt = read ? Packet::createRead(req) : Packet::createWrite(req); 3615894Sgblack@eecs.umich.edu} 3625894Sgblack@eecs.umich.edu 3635894Sgblack@eecs.umich.eduvoid 3645894Sgblack@eecs.umich.eduTimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 3655894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 3665894Sgblack@eecs.umich.edu uint8_t *data, bool read) 3675894Sgblack@eecs.umich.edu{ 3685894Sgblack@eecs.umich.edu pkt1 = pkt2 = NULL; 3695894Sgblack@eecs.umich.edu 3708105Sgblack@eecs.umich.edu assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 3715744Sgblack@eecs.umich.edu 3725894Sgblack@eecs.umich.edu if (req->getFlags().isSet(Request::NO_ACCESS)) { 3735894Sgblack@eecs.umich.edu buildPacket(pkt1, req, read); 3745894Sgblack@eecs.umich.edu return; 3755894Sgblack@eecs.umich.edu } 3765894Sgblack@eecs.umich.edu 3775894Sgblack@eecs.umich.edu buildPacket(pkt1, req1, read); 3785894Sgblack@eecs.umich.edu buildPacket(pkt2, req2, read); 3795894Sgblack@eecs.umich.edu 3808832SAli.Saidi@ARM.com req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId()); 3818949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 3825744Sgblack@eecs.umich.edu 38310566Sandreas.hansson@arm.com pkt->dataDynamic<uint8_t>(data); 3845744Sgblack@eecs.umich.edu pkt1->dataStatic<uint8_t>(data); 3855744Sgblack@eecs.umich.edu pkt2->dataStatic<uint8_t>(data + req1->getSize()); 3865744Sgblack@eecs.umich.edu 3875744Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = new SplitMainSenderState; 3885744Sgblack@eecs.umich.edu pkt->senderState = main_send_state; 3895744Sgblack@eecs.umich.edu main_send_state->fragments[0] = pkt1; 3905744Sgblack@eecs.umich.edu main_send_state->fragments[1] = pkt2; 3915744Sgblack@eecs.umich.edu main_send_state->outstanding = 2; 3925744Sgblack@eecs.umich.edu pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 3935744Sgblack@eecs.umich.edu pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 3945744Sgblack@eecs.umich.edu} 3955744Sgblack@eecs.umich.edu 3962623SN/AFault 3978444Sgblack@eecs.umich.eduTimingSimpleCPU::readMem(Addr addr, uint8_t *data, 3988444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 3992623SN/A{ 4005728Sgblack@eecs.umich.edu Fault fault; 4015728Sgblack@eecs.umich.edu const int asid = 0; 4026221Snate@binkert.org const ThreadID tid = 0; 4037720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4049814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 4056973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Read; 4062623SN/A 4077045Ssteve.reinhardt@amd.com if (traceData) { 4087045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4097045Ssteve.reinhardt@amd.com } 4107045Ssteve.reinhardt@amd.com 4117520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4128832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4135728Sgblack@eecs.umich.edu 41410024Sdam.sunwoo@arm.com req->taskId(taskId()); 41510024Sdam.sunwoo@arm.com 4167520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4175744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4185728Sgblack@eecs.umich.edu 4195894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4205744Sgblack@eecs.umich.edu if (split_addr > addr) { 4215894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4226102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 4235894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 4245894Sgblack@eecs.umich.edu 4256973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4267520Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, new uint8_t[size], 4276973Stjones1@inf.ed.ac.uk NULL, mode); 4288486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 4298486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 4308486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 4318486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 4326973Stjones1@inf.ed.ac.uk 4336973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 4346973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 4355744Sgblack@eecs.umich.edu } else { 4366973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 4377520Sgblack@eecs.umich.edu new WholeTranslationState(req, new uint8_t[size], NULL, mode); 4388486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation 4398486Sgblack@eecs.umich.edu = new DataTranslation<TimingSimpleCPU *>(this, state); 4406973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 4412623SN/A } 4422623SN/A 4435728Sgblack@eecs.umich.edu return NoFault; 4442623SN/A} 4452623SN/A 4465728Sgblack@eecs.umich.edubool 4475728Sgblack@eecs.umich.eduTimingSimpleCPU::handleWritePacket() 4485728Sgblack@eecs.umich.edu{ 4495728Sgblack@eecs.umich.edu RequestPtr req = dcache_pkt->req; 4508105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4519180Sandreas.hansson@arm.com Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 4529179Sandreas.hansson@arm.com new IprEvent(dcache_pkt, this, clockEdge(delay)); 4535728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4545728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4558975Sandreas.hansson@arm.com } else if (!dcachePort.sendTimingReq(dcache_pkt)) { 4565728Sgblack@eecs.umich.edu _status = DcacheRetry; 4575728Sgblack@eecs.umich.edu } else { 4585728Sgblack@eecs.umich.edu _status = DcacheWaitResponse; 4595728Sgblack@eecs.umich.edu // memory system takes ownership of packet 4605728Sgblack@eecs.umich.edu dcache_pkt = NULL; 4615728Sgblack@eecs.umich.edu } 4625728Sgblack@eecs.umich.edu return dcache_pkt == NULL; 4635728Sgblack@eecs.umich.edu} 4642623SN/A 4652623SN/AFault 4668444Sgblack@eecs.umich.eduTimingSimpleCPU::writeMem(uint8_t *data, unsigned size, 4678444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 4682623SN/A{ 4698443Sgblack@eecs.umich.edu uint8_t *newData = new uint8_t[size]; 4705728Sgblack@eecs.umich.edu const int asid = 0; 4716221Snate@binkert.org const ThreadID tid = 0; 4727720Sgblack@eecs.umich.edu const Addr pc = thread->instAddr(); 4739814Sandreas.hansson@arm.com unsigned block_size = cacheLineSize(); 4746973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode = BaseTLB::Write; 4753169Sstever@eecs.umich.edu 47610031SAli.Saidi@ARM.com if (data == NULL) { 47710031SAli.Saidi@ARM.com assert(flags & Request::CACHE_BLOCK_ZERO); 47810031SAli.Saidi@ARM.com // This must be a cache block cleaning request 47910031SAli.Saidi@ARM.com memset(newData, 0, size); 48010031SAli.Saidi@ARM.com } else { 48110031SAli.Saidi@ARM.com memcpy(newData, data, size); 48210031SAli.Saidi@ARM.com } 48310031SAli.Saidi@ARM.com 4847045Ssteve.reinhardt@amd.com if (traceData) { 4857045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 4867045Ssteve.reinhardt@amd.com } 4877045Ssteve.reinhardt@amd.com 4887520Sgblack@eecs.umich.edu RequestPtr req = new Request(asid, addr, size, 4898832SAli.Saidi@ARM.com flags, dataMasterId(), pc, _cpuId, tid); 4905728Sgblack@eecs.umich.edu 49110024Sdam.sunwoo@arm.com req->taskId(taskId()); 49210024Sdam.sunwoo@arm.com 4937520Sgblack@eecs.umich.edu Addr split_addr = roundDown(addr + size - 1, block_size); 4945744Sgblack@eecs.umich.edu assert(split_addr <= addr || split_addr - addr < block_size); 4955728Sgblack@eecs.umich.edu 4965894Sgblack@eecs.umich.edu _status = DTBWaitResponse; 4975744Sgblack@eecs.umich.edu if (split_addr > addr) { 4985894Sgblack@eecs.umich.edu RequestPtr req1, req2; 4996102Sgblack@eecs.umich.edu assert(!req->isLLSC() && !req->isSwap()); 5005894Sgblack@eecs.umich.edu req->splitOnVaddr(split_addr, req1, req2); 5015894Sgblack@eecs.umich.edu 5026973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5038443Sgblack@eecs.umich.edu new WholeTranslationState(req, req1, req2, newData, res, mode); 5048486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans1 = 5058486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 0); 5068486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *trans2 = 5078486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state, 1); 5086973Stjones1@inf.ed.ac.uk 5096973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req1, tc, trans1, mode); 5106973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req2, tc, trans2, mode); 5115744Sgblack@eecs.umich.edu } else { 5126973Stjones1@inf.ed.ac.uk WholeTranslationState *state = 5138443Sgblack@eecs.umich.edu new WholeTranslationState(req, newData, res, mode); 5148486Sgblack@eecs.umich.edu DataTranslation<TimingSimpleCPU *> *translation = 5158486Sgblack@eecs.umich.edu new DataTranslation<TimingSimpleCPU *>(this, state); 5166973Stjones1@inf.ed.ac.uk thread->dtb->translateTiming(req, tc, translation, mode); 5172623SN/A } 5182623SN/A 5197045Ssteve.reinhardt@amd.com // Translation faults will be returned via finishTranslation() 5205728Sgblack@eecs.umich.edu return NoFault; 5212623SN/A} 5222623SN/A 5232623SN/A 5242623SN/Avoid 5256973Stjones1@inf.ed.ac.ukTimingSimpleCPU::finishTranslation(WholeTranslationState *state) 5266973Stjones1@inf.ed.ac.uk{ 5279342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5286973Stjones1@inf.ed.ac.uk 5296973Stjones1@inf.ed.ac.uk if (state->getFault() != NoFault) { 5306973Stjones1@inf.ed.ac.uk if (state->isPrefetch()) { 5316973Stjones1@inf.ed.ac.uk state->setNoFault(); 5326973Stjones1@inf.ed.ac.uk } 5337691SAli.Saidi@ARM.com delete [] state->data; 5346973Stjones1@inf.ed.ac.uk state->deleteReqs(); 5356973Stjones1@inf.ed.ac.uk translationFault(state->getFault()); 5366973Stjones1@inf.ed.ac.uk } else { 5376973Stjones1@inf.ed.ac.uk if (!state->isSplit) { 5386973Stjones1@inf.ed.ac.uk sendData(state->mainReq, state->data, state->res, 5396973Stjones1@inf.ed.ac.uk state->mode == BaseTLB::Read); 5406973Stjones1@inf.ed.ac.uk } else { 5416973Stjones1@inf.ed.ac.uk sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, 5426973Stjones1@inf.ed.ac.uk state->data, state->mode == BaseTLB::Read); 5436973Stjones1@inf.ed.ac.uk } 5446973Stjones1@inf.ed.ac.uk } 5456973Stjones1@inf.ed.ac.uk 5466973Stjones1@inf.ed.ac.uk delete state; 5476973Stjones1@inf.ed.ac.uk} 5486973Stjones1@inf.ed.ac.uk 5496973Stjones1@inf.ed.ac.uk 5506973Stjones1@inf.ed.ac.ukvoid 5512623SN/ATimingSimpleCPU::fetch() 5522623SN/A{ 5535221Ssaidi@eecs.umich.edu DPRINTF(SimpleCPU, "Fetch\n"); 5545221Ssaidi@eecs.umich.edu 55510596Sgabeblack@google.com if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 5563387Sgblack@eecs.umich.edu checkForInterrupts(); 55710596Sgabeblack@google.com checkPcEventQueue(); 55810596Sgabeblack@google.com } 5595348Ssaidi@eecs.umich.edu 5608143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5618143SAli.Saidi@ARM.com if (_status == Idle) 5628143SAli.Saidi@ARM.com return; 5638143SAli.Saidi@ARM.com 5647720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5657720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; 5662623SN/A 5677720Sgblack@eecs.umich.edu if (needToFetch) { 5689342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 5695669Sgblack@eecs.umich.edu Request *ifetch_req = new Request(); 57010024Sdam.sunwoo@arm.com ifetch_req->taskId(taskId()); 5715712Shsul@eecs.umich.edu ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); 5725894Sgblack@eecs.umich.edu setupFetchRequest(ifetch_req); 5738277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); 5746023Snate@binkert.org thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation, 5756023Snate@binkert.org BaseTLB::Execute); 5762623SN/A } else { 5775669Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 5785669Sgblack@eecs.umich.edu completeIfetch(NULL); 5795894Sgblack@eecs.umich.edu 58010464SAndreas.Sandberg@ARM.com updateCycleCounts(); 5815894Sgblack@eecs.umich.edu } 5825894Sgblack@eecs.umich.edu} 5835894Sgblack@eecs.umich.edu 5845894Sgblack@eecs.umich.edu 5855894Sgblack@eecs.umich.eduvoid 58610379Sandreas.hansson@arm.comTimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, 58710379Sandreas.hansson@arm.com ThreadContext *tc) 5885894Sgblack@eecs.umich.edu{ 5895894Sgblack@eecs.umich.edu if (fault == NoFault) { 5908277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n", 5918277SAli.Saidi@ARM.com req->getVaddr(), req->getPaddr()); 5928949Sandreas.hansson@arm.com ifetch_pkt = new Packet(req, MemCmd::ReadReq); 5935894Sgblack@eecs.umich.edu ifetch_pkt->dataStatic(&inst); 5948277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr()); 5955894Sgblack@eecs.umich.edu 5968975Sandreas.hansson@arm.com if (!icachePort.sendTimingReq(ifetch_pkt)) { 5975894Sgblack@eecs.umich.edu // Need to wait for retry 5985894Sgblack@eecs.umich.edu _status = IcacheRetry; 5995894Sgblack@eecs.umich.edu } else { 6005894Sgblack@eecs.umich.edu // Need to wait for cache to respond 6015894Sgblack@eecs.umich.edu _status = IcacheWaitResponse; 6025894Sgblack@eecs.umich.edu // ownership of packet transferred to memory system 6035894Sgblack@eecs.umich.edu ifetch_pkt = NULL; 6045894Sgblack@eecs.umich.edu } 6055894Sgblack@eecs.umich.edu } else { 6068277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); 6075894Sgblack@eecs.umich.edu delete req; 6085894Sgblack@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 6099342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6105894Sgblack@eecs.umich.edu advanceInst(fault); 6112623SN/A } 6123222Sktlim@umich.edu 61310464SAndreas.Sandberg@ARM.com updateCycleCounts(); 6142623SN/A} 6152623SN/A 6162623SN/A 6172623SN/Avoid 61810379Sandreas.hansson@arm.comTimingSimpleCPU::advanceInst(const Fault &fault) 6192623SN/A{ 6208276SAli.Saidi@ARM.com if (_status == Faulting) 6218276SAli.Saidi@ARM.com return; 6228276SAli.Saidi@ARM.com 6238276SAli.Saidi@ARM.com if (fault != NoFault) { 6248276SAli.Saidi@ARM.com advancePC(fault); 6258276SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); 6269648Sdam.sunwoo@arm.com reschedule(fetchEvent, clockEdge(), true); 6278276SAli.Saidi@ARM.com _status = Faulting; 6288276SAli.Saidi@ARM.com return; 6298276SAli.Saidi@ARM.com } 6308276SAli.Saidi@ARM.com 6318276SAli.Saidi@ARM.com 6328276SAli.Saidi@ARM.com if (!stayAtPC) 6335726Sgblack@eecs.umich.edu advancePC(fault); 6342623SN/A 6359442SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6369442SAndreas.Sandberg@ARM.com return; 6379442SAndreas.Sandberg@ARM.com 6389342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6392631SN/A // kick off fetch of next instruction... callback from icache 6402631SN/A // response will cause that instruction to be executed, 6412631SN/A // keeping the CPU running. 6422631SN/A fetch(); 6432631SN/A } 6442623SN/A} 6452623SN/A 6462623SN/A 6472623SN/Avoid 6483349Sbinkertn@umich.eduTimingSimpleCPU::completeIfetch(PacketPtr pkt) 6492623SN/A{ 6508277SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ? 6518277SAli.Saidi@ARM.com pkt->getAddr() : 0); 6528277SAli.Saidi@ARM.com 6532623SN/A // received a response from the icache: execute the received 6542623SN/A // instruction 6555669Sgblack@eecs.umich.edu assert(!pkt || !pkt->isError()); 6562623SN/A assert(_status == IcacheWaitResponse); 6572798Sktlim@umich.edu 6589342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 6592644Sstever@eecs.umich.edu 66010464SAndreas.Sandberg@ARM.com updateCycleCounts(); 6613222Sktlim@umich.edu 66210020Smatt.horsnell@ARM.com if (pkt) 66310020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 66410020Smatt.horsnell@ARM.com 66510020Smatt.horsnell@ARM.com 6662623SN/A preExecute(); 6677725SAli.Saidi@ARM.com if (curStaticInst && curStaticInst->isMemRef()) { 6682623SN/A // load or store: just send to dcache 6692623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 6707945SAli.Saidi@ARM.com 6717945SAli.Saidi@ARM.com // If we're not running now the instruction will complete in a dcache 6727945SAli.Saidi@ARM.com // response callback or the instruction faulted and has started an 6737945SAli.Saidi@ARM.com // ifetch 6749342SAndreas.Sandberg@arm.com if (_status == BaseSimpleCPU::Running) { 6755894Sgblack@eecs.umich.edu if (fault != NoFault && traceData) { 6765001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 6775001Sgblack@eecs.umich.edu delete traceData; 6785001Sgblack@eecs.umich.edu traceData = NULL; 6793170Sstever@eecs.umich.edu } 6804998Sgblack@eecs.umich.edu 6812644Sstever@eecs.umich.edu postExecute(); 6825103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6835103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6845103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 6855103Ssaidi@eecs.umich.edu instCnt++; 6862644Sstever@eecs.umich.edu advanceInst(fault); 6872644Sstever@eecs.umich.edu } 6885726Sgblack@eecs.umich.edu } else if (curStaticInst) { 6892623SN/A // non-memory instruction: execute completely now 6902623SN/A Fault fault = curStaticInst->execute(this, traceData); 6914998Sgblack@eecs.umich.edu 6924998Sgblack@eecs.umich.edu // keep an instruction count 6934998Sgblack@eecs.umich.edu if (fault == NoFault) 6944998Sgblack@eecs.umich.edu countInst(); 6957655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 6965001Sgblack@eecs.umich.edu delete traceData; 6975001Sgblack@eecs.umich.edu traceData = NULL; 6985001Sgblack@eecs.umich.edu } 6994998Sgblack@eecs.umich.edu 7002644Sstever@eecs.umich.edu postExecute(); 7015103Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 7025103Ssaidi@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 7035103Ssaidi@eecs.umich.edu curStaticInst->isFirstMicroop())) 7045103Ssaidi@eecs.umich.edu instCnt++; 7052644Sstever@eecs.umich.edu advanceInst(fault); 7065726Sgblack@eecs.umich.edu } else { 7075726Sgblack@eecs.umich.edu advanceInst(NoFault); 7082623SN/A } 7093658Sktlim@umich.edu 7105669Sgblack@eecs.umich.edu if (pkt) { 7115669Sgblack@eecs.umich.edu delete pkt->req; 7125669Sgblack@eecs.umich.edu delete pkt; 7135669Sgblack@eecs.umich.edu } 7142623SN/A} 7152623SN/A 7162948Ssaidi@eecs.umich.eduvoid 7172948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 7182948Ssaidi@eecs.umich.edu{ 7192948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 7202948Ssaidi@eecs.umich.edu} 7212623SN/A 7222623SN/Abool 7238975Sandreas.hansson@arm.comTimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 7242623SN/A{ 7259165Sandreas.hansson@arm.com DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); 7269165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 7279648Sdam.sunwoo@arm.com Tick next_tick = cpu->clockEdge(); 7282948Ssaidi@eecs.umich.edu 7299165Sandreas.hansson@arm.com if (next_tick == curTick()) 7309165Sandreas.hansson@arm.com cpu->completeIfetch(pkt); 7319165Sandreas.hansson@arm.com else 7329165Sandreas.hansson@arm.com tickEvent.schedule(pkt, next_tick); 7338948Sandreas.hansson@arm.com 7344433Ssaidi@eecs.umich.edu return true; 7352623SN/A} 7362623SN/A 7372657Ssaidi@eecs.umich.eduvoid 7382623SN/ATimingSimpleCPU::IcachePort::recvRetry() 7392623SN/A{ 7402623SN/A // we shouldn't get a retry unless we have a packet that we're 7412623SN/A // waiting to transmit 7422623SN/A assert(cpu->ifetch_pkt != NULL); 7432623SN/A assert(cpu->_status == IcacheRetry); 7443349Sbinkertn@umich.edu PacketPtr tmp = cpu->ifetch_pkt; 7458975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 7462657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 7472657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 7482657Ssaidi@eecs.umich.edu } 7492623SN/A} 7502623SN/A 7512623SN/Avoid 7523349Sbinkertn@umich.eduTimingSimpleCPU::completeDataAccess(PacketPtr pkt) 7532623SN/A{ 7542623SN/A // received a response from the dcache: complete the load or store 7552623SN/A // instruction 7564870Sstever@eecs.umich.edu assert(!pkt->isError()); 7577516Shestness@cs.utexas.edu assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || 7587516Shestness@cs.utexas.edu pkt->req->getFlags().isSet(Request::NO_ACCESS)); 7592623SN/A 76010020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 76110464SAndreas.Sandberg@ARM.com 76210464SAndreas.Sandberg@ARM.com updateCycleCounts(); 7633184Srdreslin@umich.edu 7645728Sgblack@eecs.umich.edu if (pkt->senderState) { 7655728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 7665728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(pkt->senderState); 7675728Sgblack@eecs.umich.edu assert(send_state); 7685728Sgblack@eecs.umich.edu delete pkt->req; 7695728Sgblack@eecs.umich.edu delete pkt; 7705728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 7715728Sgblack@eecs.umich.edu delete send_state; 7725728Sgblack@eecs.umich.edu 7735728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 7745728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 7755728Sgblack@eecs.umich.edu assert(main_send_state); 7765728Sgblack@eecs.umich.edu // Record the fact that this packet is no longer outstanding. 7775728Sgblack@eecs.umich.edu assert(main_send_state->outstanding != 0); 7785728Sgblack@eecs.umich.edu main_send_state->outstanding--; 7795728Sgblack@eecs.umich.edu 7805728Sgblack@eecs.umich.edu if (main_send_state->outstanding) { 7815728Sgblack@eecs.umich.edu return; 7825728Sgblack@eecs.umich.edu } else { 7835728Sgblack@eecs.umich.edu delete main_send_state; 7845728Sgblack@eecs.umich.edu big_pkt->senderState = NULL; 7855728Sgblack@eecs.umich.edu pkt = big_pkt; 7865728Sgblack@eecs.umich.edu } 7875728Sgblack@eecs.umich.edu } 7885728Sgblack@eecs.umich.edu 7899342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 7905728Sgblack@eecs.umich.edu 7912623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 7922623SN/A 7934998Sgblack@eecs.umich.edu // keep an instruction count 7944998Sgblack@eecs.umich.edu if (fault == NoFault) 7954998Sgblack@eecs.umich.edu countInst(); 7965001Sgblack@eecs.umich.edu else if (traceData) { 7975001Sgblack@eecs.umich.edu // If there was a fault, we shouldn't trace this instruction. 7985001Sgblack@eecs.umich.edu delete traceData; 7995001Sgblack@eecs.umich.edu traceData = NULL; 8005001Sgblack@eecs.umich.edu } 8014998Sgblack@eecs.umich.edu 8022644Sstever@eecs.umich.edu delete pkt->req; 8032644Sstever@eecs.umich.edu delete pkt; 8042644Sstever@eecs.umich.edu 8053184Srdreslin@umich.edu postExecute(); 8063227Sktlim@umich.edu 8072644Sstever@eecs.umich.edu advanceInst(fault); 8082623SN/A} 8092623SN/A 81010030SAli.Saidi@ARM.comvoid 81110464SAndreas.Sandberg@ARM.comTimingSimpleCPU::updateCycleCounts() 81210464SAndreas.Sandberg@ARM.com{ 81310464SAndreas.Sandberg@ARM.com const Cycles delta(curCycle() - previousCycle); 81410464SAndreas.Sandberg@ARM.com 81510464SAndreas.Sandberg@ARM.com numCycles += delta; 81610464SAndreas.Sandberg@ARM.com ppCycles->notify(delta); 81710464SAndreas.Sandberg@ARM.com 81810464SAndreas.Sandberg@ARM.com previousCycle = curCycle(); 81910464SAndreas.Sandberg@ARM.com} 82010464SAndreas.Sandberg@ARM.com 82110464SAndreas.Sandberg@ARM.comvoid 82210030SAli.Saidi@ARM.comTimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 82310030SAli.Saidi@ARM.com{ 82410529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 82510529Smorr@cs.wisc.edu if(cpu->getAddrMonitor()->doMonitor(pkt)) { 82610529Smorr@cs.wisc.edu cpu->wakeup(); 82710529Smorr@cs.wisc.edu } 82810030SAli.Saidi@ARM.com TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 82910030SAli.Saidi@ARM.com} 83010030SAli.Saidi@ARM.com 83110529Smorr@cs.wisc.eduvoid 83210529Smorr@cs.wisc.eduTimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) 83310529Smorr@cs.wisc.edu{ 83410529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 83510529Smorr@cs.wisc.edu if(cpu->getAddrMonitor()->doMonitor(pkt)) { 83610529Smorr@cs.wisc.edu cpu->wakeup(); 83710529Smorr@cs.wisc.edu } 83810529Smorr@cs.wisc.edu} 83910030SAli.Saidi@ARM.com 8402623SN/Abool 8418975Sandreas.hansson@arm.comTimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 8422623SN/A{ 8439165Sandreas.hansson@arm.com // delay processing of returned data until next CPU clock edge 8449648Sdam.sunwoo@arm.com Tick next_tick = cpu->clockEdge(); 8452948Ssaidi@eecs.umich.edu 8469165Sandreas.hansson@arm.com if (next_tick == curTick()) { 8479165Sandreas.hansson@arm.com cpu->completeDataAccess(pkt); 8489165Sandreas.hansson@arm.com } else { 8499165Sandreas.hansson@arm.com if (!tickEvent.scheduled()) { 8509165Sandreas.hansson@arm.com tickEvent.schedule(pkt, next_tick); 8515728Sgblack@eecs.umich.edu } else { 8529165Sandreas.hansson@arm.com // In the case of a split transaction and a cache that is 8539165Sandreas.hansson@arm.com // faster than a CPU we could get two responses before 8549165Sandreas.hansson@arm.com // next_tick expires 8559165Sandreas.hansson@arm.com if (!retryEvent.scheduled()) 8569165Sandreas.hansson@arm.com cpu->schedule(retryEvent, next_tick); 8579165Sandreas.hansson@arm.com return false; 8584433Ssaidi@eecs.umich.edu } 8593310Srdreslin@umich.edu } 8608948Sandreas.hansson@arm.com 8614433Ssaidi@eecs.umich.edu return true; 8622948Ssaidi@eecs.umich.edu} 8632948Ssaidi@eecs.umich.edu 8642948Ssaidi@eecs.umich.eduvoid 8652948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 8662948Ssaidi@eecs.umich.edu{ 8672630SN/A cpu->completeDataAccess(pkt); 8682623SN/A} 8692623SN/A 8702657Ssaidi@eecs.umich.eduvoid 8712623SN/ATimingSimpleCPU::DcachePort::recvRetry() 8722623SN/A{ 8732623SN/A // we shouldn't get a retry unless we have a packet that we're 8742623SN/A // waiting to transmit 8752623SN/A assert(cpu->dcache_pkt != NULL); 8762623SN/A assert(cpu->_status == DcacheRetry); 8773349Sbinkertn@umich.edu PacketPtr tmp = cpu->dcache_pkt; 8785728Sgblack@eecs.umich.edu if (tmp->senderState) { 8795728Sgblack@eecs.umich.edu // This is a packet from a split access. 8805728Sgblack@eecs.umich.edu SplitFragmentSenderState * send_state = 8815728Sgblack@eecs.umich.edu dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); 8825728Sgblack@eecs.umich.edu assert(send_state); 8835728Sgblack@eecs.umich.edu PacketPtr big_pkt = send_state->bigPkt; 8845728Sgblack@eecs.umich.edu 8855728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 8865728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); 8875728Sgblack@eecs.umich.edu assert(main_send_state); 8885728Sgblack@eecs.umich.edu 8898975Sandreas.hansson@arm.com if (sendTimingReq(tmp)) { 8905728Sgblack@eecs.umich.edu // If we were able to send without retrying, record that fact 8915728Sgblack@eecs.umich.edu // and try sending the other fragment. 8925728Sgblack@eecs.umich.edu send_state->clearFromParent(); 8935728Sgblack@eecs.umich.edu int other_index = main_send_state->getPendingFragment(); 8945728Sgblack@eecs.umich.edu if (other_index > 0) { 8955728Sgblack@eecs.umich.edu tmp = main_send_state->fragments[other_index]; 8965728Sgblack@eecs.umich.edu cpu->dcache_pkt = tmp; 8975728Sgblack@eecs.umich.edu if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) || 8985728Sgblack@eecs.umich.edu (big_pkt->isWrite() && cpu->handleWritePacket())) { 8995728Sgblack@eecs.umich.edu main_send_state->fragments[other_index] = NULL; 9005728Sgblack@eecs.umich.edu } 9015728Sgblack@eecs.umich.edu } else { 9025728Sgblack@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9035728Sgblack@eecs.umich.edu // memory system takes ownership of packet 9045728Sgblack@eecs.umich.edu cpu->dcache_pkt = NULL; 9055728Sgblack@eecs.umich.edu } 9065728Sgblack@eecs.umich.edu } 9078975Sandreas.hansson@arm.com } else if (sendTimingReq(tmp)) { 9082657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 9093170Sstever@eecs.umich.edu // memory system takes ownership of packet 9102657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 9112657Ssaidi@eecs.umich.edu } 9122623SN/A} 9132623SN/A 9145606Snate@binkert.orgTimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, 9155606Snate@binkert.org Tick t) 9165606Snate@binkert.org : pkt(_pkt), cpu(_cpu) 9175103Ssaidi@eecs.umich.edu{ 9185606Snate@binkert.org cpu->schedule(this, t); 9195103Ssaidi@eecs.umich.edu} 9205103Ssaidi@eecs.umich.edu 9215103Ssaidi@eecs.umich.eduvoid 9225103Ssaidi@eecs.umich.eduTimingSimpleCPU::IprEvent::process() 9235103Ssaidi@eecs.umich.edu{ 9245103Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 9255103Ssaidi@eecs.umich.edu} 9265103Ssaidi@eecs.umich.edu 9275103Ssaidi@eecs.umich.educonst char * 9285336Shines@cs.fsu.eduTimingSimpleCPU::IprEvent::description() const 9295103Ssaidi@eecs.umich.edu{ 9305103Ssaidi@eecs.umich.edu return "Timing Simple CPU Delay IPR event"; 9315103Ssaidi@eecs.umich.edu} 9325103Ssaidi@eecs.umich.edu 9332623SN/A 9345315Sstever@gmail.comvoid 9355315Sstever@gmail.comTimingSimpleCPU::printAddr(Addr a) 9365315Sstever@gmail.com{ 9375315Sstever@gmail.com dcachePort.printAddr(a); 9385315Sstever@gmail.com} 9395315Sstever@gmail.com 9405315Sstever@gmail.com 9412623SN/A//////////////////////////////////////////////////////////////////////// 9422623SN/A// 9432623SN/A// TimingSimpleCPU Simulation Object 9442623SN/A// 9454762Snate@binkert.orgTimingSimpleCPU * 9464762Snate@binkert.orgTimingSimpleCPUParams::create() 9472623SN/A{ 9485529Snate@binkert.org numThreads = 1; 9498779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 9504762Snate@binkert.org panic("only one workload allowed"); 9515529Snate@binkert.org return new TimingSimpleCPU(this); 9522623SN/A} 953