noncaching.cc revision 13012 
1/*
2 * Copyright (c) 2012, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Sandberg
38 */
39
40#include "cpu/simple/noncaching.hh"
41
42NonCachingSimpleCPU::NonCachingSimpleCPU(NonCachingSimpleCPUParams *p)
43    : AtomicSimpleCPU(p)
44{
45}
46
47void
48NonCachingSimpleCPU::verifyMemoryMode() const
49{
50    if (!(system->isAtomicMode() && system->bypassCaches())) {
51        fatal("The direct CPU requires the memory system to be in the "
52              "'atomic_noncaching' mode.\n");
53    }
54}
55
56Tick
57NonCachingSimpleCPU::sendPacket(MasterPort &port, const PacketPtr &pkt)
58{
59    if (system->isMemAddr(pkt->getAddr())) {
60        system->getPhysMem().access(pkt);
61        return 0;
62    } else {
63        return port.sendAtomic(pkt);
64    }
65}
66
67NonCachingSimpleCPU *
68NonCachingSimpleCPUParams::create()
69{
70    numThreads = 1;
71    if (!FullSystem && workload.size() != 1)
72        fatal("only one workload allowed");
73    return new NonCachingSimpleCPU(this);
74}
75