exec_context.hh revision 13557
111147Smitch.hayenga@arm.com/* 212109SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2014-2016 ARM Limited 311147Smitch.hayenga@arm.com * All rights reserved 411147Smitch.hayenga@arm.com * 511147Smitch.hayenga@arm.com * The license below extends only to copyright in the software and shall 611147Smitch.hayenga@arm.com * not be construed as granting a license to any other intellectual 711147Smitch.hayenga@arm.com * property including but not limited to intellectual property relating 811147Smitch.hayenga@arm.com * to a hardware implementation of the functionality of the software 911147Smitch.hayenga@arm.com * licensed hereunder. You may use the software subject to the license 1011147Smitch.hayenga@arm.com * terms below provided that you ensure that this notice is replicated 1111147Smitch.hayenga@arm.com * unmodified and in its entirety in all distributions of the software, 1211147Smitch.hayenga@arm.com * modified or unmodified, in source code or in binary form. 1311147Smitch.hayenga@arm.com * 1411147Smitch.hayenga@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511147Smitch.hayenga@arm.com * All rights reserved. 1611147Smitch.hayenga@arm.com * 1711147Smitch.hayenga@arm.com * Redistribution and use in source and binary forms, with or without 1811147Smitch.hayenga@arm.com * modification, are permitted provided that the following conditions are 1911147Smitch.hayenga@arm.com * met: redistributions of source code must retain the above copyright 2011147Smitch.hayenga@arm.com * notice, this list of conditions and the following disclaimer; 2111147Smitch.hayenga@arm.com * redistributions in binary form must reproduce the above copyright 2211147Smitch.hayenga@arm.com * notice, this list of conditions and the following disclaimer in the 2311147Smitch.hayenga@arm.com * documentation and/or other materials provided with the distribution; 2411147Smitch.hayenga@arm.com * neither the name of the copyright holders nor the names of its 2511147Smitch.hayenga@arm.com * contributors may be used to endorse or promote products derived from 2611147Smitch.hayenga@arm.com * this software without specific prior written permission. 2711147Smitch.hayenga@arm.com * 2811147Smitch.hayenga@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2911147Smitch.hayenga@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3011147Smitch.hayenga@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3111147Smitch.hayenga@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3211147Smitch.hayenga@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3311147Smitch.hayenga@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3411147Smitch.hayenga@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3511147Smitch.hayenga@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3611147Smitch.hayenga@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3711147Smitch.hayenga@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3811147Smitch.hayenga@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3911147Smitch.hayenga@arm.com * 4011147Smitch.hayenga@arm.com * Authors: Kevin Lim 4111147Smitch.hayenga@arm.com * Andreas Sandberg 4211147Smitch.hayenga@arm.com * Mitch Hayenga 4311147Smitch.hayenga@arm.com */ 4411147Smitch.hayenga@arm.com 4511147Smitch.hayenga@arm.com#ifndef __CPU_SIMPLE_EXEC_CONTEXT_HH__ 4611147Smitch.hayenga@arm.com#define __CPU_SIMPLE_EXEC_CONTEXT_HH__ 4711147Smitch.hayenga@arm.com 4811147Smitch.hayenga@arm.com#include "arch/registers.hh" 4911147Smitch.hayenga@arm.com#include "base/types.hh" 5011147Smitch.hayenga@arm.com#include "config/the_isa.hh" 5111147Smitch.hayenga@arm.com#include "cpu/base.hh" 5211147Smitch.hayenga@arm.com#include "cpu/exec_context.hh" 5312104Snathanael.premillieu@arm.com#include "cpu/reg_class.hh" 5411147Smitch.hayenga@arm.com#include "cpu/simple/base.hh" 5511147Smitch.hayenga@arm.com#include "cpu/static_inst_fwd.hh" 5611147Smitch.hayenga@arm.com#include "cpu/translation.hh" 5711608Snikos.nikoleris@arm.com#include "mem/request.hh" 5811147Smitch.hayenga@arm.com 5911147Smitch.hayenga@arm.comclass BaseSimpleCPU; 6011147Smitch.hayenga@arm.com 6111147Smitch.hayenga@arm.comclass SimpleExecContext : public ExecContext { 6211147Smitch.hayenga@arm.com protected: 6311147Smitch.hayenga@arm.com typedef TheISA::CCReg CCReg; 6412109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 6512109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 6611147Smitch.hayenga@arm.com 6711147Smitch.hayenga@arm.com public: 6811147Smitch.hayenga@arm.com BaseSimpleCPU *cpu; 6911147Smitch.hayenga@arm.com SimpleThread* thread; 7011147Smitch.hayenga@arm.com 7111147Smitch.hayenga@arm.com // This is the offset from the current pc that fetch should be performed 7211147Smitch.hayenga@arm.com Addr fetchOffset; 7311147Smitch.hayenga@arm.com // This flag says to stay at the current pc. This is useful for 7411147Smitch.hayenga@arm.com // instructions which go beyond MachInst boundaries. 7511147Smitch.hayenga@arm.com bool stayAtPC; 7611147Smitch.hayenga@arm.com 7711147Smitch.hayenga@arm.com // Branch prediction 7811147Smitch.hayenga@arm.com TheISA::PCState predPC; 7911147Smitch.hayenga@arm.com 8011147Smitch.hayenga@arm.com /** PER-THREAD STATS */ 8111147Smitch.hayenga@arm.com 8211147Smitch.hayenga@arm.com // Number of simulated instructions 8311147Smitch.hayenga@arm.com Counter numInst; 8411147Smitch.hayenga@arm.com Stats::Scalar numInsts; 8511147Smitch.hayenga@arm.com Counter numOp; 8611147Smitch.hayenga@arm.com Stats::Scalar numOps; 8711147Smitch.hayenga@arm.com 8811147Smitch.hayenga@arm.com // Number of integer alu accesses 8911147Smitch.hayenga@arm.com Stats::Scalar numIntAluAccesses; 9011147Smitch.hayenga@arm.com 9111147Smitch.hayenga@arm.com // Number of float alu accesses 9211147Smitch.hayenga@arm.com Stats::Scalar numFpAluAccesses; 9311147Smitch.hayenga@arm.com 9412110SRekai.GonzalezAlberquilla@arm.com // Number of vector alu accesses 9512110SRekai.GonzalezAlberquilla@arm.com Stats::Scalar numVecAluAccesses; 9612110SRekai.GonzalezAlberquilla@arm.com 9711147Smitch.hayenga@arm.com // Number of function calls/returns 9811147Smitch.hayenga@arm.com Stats::Scalar numCallsReturns; 9911147Smitch.hayenga@arm.com 10011147Smitch.hayenga@arm.com // Conditional control instructions; 10111147Smitch.hayenga@arm.com Stats::Scalar numCondCtrlInsts; 10211147Smitch.hayenga@arm.com 10311147Smitch.hayenga@arm.com // Number of int instructions 10411147Smitch.hayenga@arm.com Stats::Scalar numIntInsts; 10511147Smitch.hayenga@arm.com 10611147Smitch.hayenga@arm.com // Number of float instructions 10711147Smitch.hayenga@arm.com Stats::Scalar numFpInsts; 10811147Smitch.hayenga@arm.com 10912110SRekai.GonzalezAlberquilla@arm.com // Number of vector instructions 11012110SRekai.GonzalezAlberquilla@arm.com Stats::Scalar numVecInsts; 11112110SRekai.GonzalezAlberquilla@arm.com 11211147Smitch.hayenga@arm.com // Number of integer register file accesses 11311147Smitch.hayenga@arm.com Stats::Scalar numIntRegReads; 11411147Smitch.hayenga@arm.com Stats::Scalar numIntRegWrites; 11511147Smitch.hayenga@arm.com 11611147Smitch.hayenga@arm.com // Number of float register file accesses 11711147Smitch.hayenga@arm.com Stats::Scalar numFpRegReads; 11811147Smitch.hayenga@arm.com Stats::Scalar numFpRegWrites; 11911147Smitch.hayenga@arm.com 12012109SRekai.GonzalezAlberquilla@arm.com // Number of vector register file accesses 12112109SRekai.GonzalezAlberquilla@arm.com mutable Stats::Scalar numVecRegReads; 12212109SRekai.GonzalezAlberquilla@arm.com Stats::Scalar numVecRegWrites; 12312109SRekai.GonzalezAlberquilla@arm.com 12411147Smitch.hayenga@arm.com // Number of condition code register file accesses 12511147Smitch.hayenga@arm.com Stats::Scalar numCCRegReads; 12611147Smitch.hayenga@arm.com Stats::Scalar numCCRegWrites; 12711147Smitch.hayenga@arm.com 12811147Smitch.hayenga@arm.com // Number of simulated memory references 12911147Smitch.hayenga@arm.com Stats::Scalar numMemRefs; 13011147Smitch.hayenga@arm.com Stats::Scalar numLoadInsts; 13111147Smitch.hayenga@arm.com Stats::Scalar numStoreInsts; 13211147Smitch.hayenga@arm.com 13311147Smitch.hayenga@arm.com // Number of idle cycles 13411147Smitch.hayenga@arm.com Stats::Formula numIdleCycles; 13511147Smitch.hayenga@arm.com 13611147Smitch.hayenga@arm.com // Number of busy cycles 13711147Smitch.hayenga@arm.com Stats::Formula numBusyCycles; 13811147Smitch.hayenga@arm.com 13911147Smitch.hayenga@arm.com // Number of simulated loads 14011147Smitch.hayenga@arm.com Counter numLoad; 14111147Smitch.hayenga@arm.com 14211147Smitch.hayenga@arm.com // Number of idle cycles 14311147Smitch.hayenga@arm.com Stats::Average notIdleFraction; 14411147Smitch.hayenga@arm.com Stats::Formula idleFraction; 14511147Smitch.hayenga@arm.com 14611147Smitch.hayenga@arm.com // Number of cycles stalled for I-cache responses 14711147Smitch.hayenga@arm.com Stats::Scalar icacheStallCycles; 14811147Smitch.hayenga@arm.com Counter lastIcacheStall; 14911147Smitch.hayenga@arm.com 15011147Smitch.hayenga@arm.com // Number of cycles stalled for D-cache responses 15111147Smitch.hayenga@arm.com Stats::Scalar dcacheStallCycles; 15211147Smitch.hayenga@arm.com Counter lastDcacheStall; 15311147Smitch.hayenga@arm.com 15411147Smitch.hayenga@arm.com /// @{ 15511147Smitch.hayenga@arm.com /// Total number of branches fetched 15611147Smitch.hayenga@arm.com Stats::Scalar numBranches; 15711147Smitch.hayenga@arm.com /// Number of branches predicted as taken 15811147Smitch.hayenga@arm.com Stats::Scalar numPredictedBranches; 15911147Smitch.hayenga@arm.com /// Number of misprediced branches 16011147Smitch.hayenga@arm.com Stats::Scalar numBranchMispred; 16111147Smitch.hayenga@arm.com /// @} 16211147Smitch.hayenga@arm.com 16311147Smitch.hayenga@arm.com // Instruction mix histogram by OpClass 16411147Smitch.hayenga@arm.com Stats::Vector statExecutedInstType; 16511147Smitch.hayenga@arm.com 16611147Smitch.hayenga@arm.com public: 16711147Smitch.hayenga@arm.com /** Constructor */ 16811147Smitch.hayenga@arm.com SimpleExecContext(BaseSimpleCPU* _cpu, SimpleThread* _thread) 16911147Smitch.hayenga@arm.com : cpu(_cpu), thread(_thread), fetchOffset(0), stayAtPC(false), 17011147Smitch.hayenga@arm.com numInst(0), numOp(0), numLoad(0), lastIcacheStall(0), lastDcacheStall(0) 17111147Smitch.hayenga@arm.com { } 17211147Smitch.hayenga@arm.com 17311147Smitch.hayenga@arm.com /** Reads an integer register. */ 17413557Sgabeblack@google.com RegVal 17513557Sgabeblack@google.com readIntRegOperand(const StaticInst *si, int idx) override 17611147Smitch.hayenga@arm.com { 17711147Smitch.hayenga@arm.com numIntRegReads++; 17812106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 17912106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 18012106SRekai.GonzalezAlberquilla@arm.com return thread->readIntReg(reg.index()); 18111147Smitch.hayenga@arm.com } 18211147Smitch.hayenga@arm.com 18311147Smitch.hayenga@arm.com /** Sets an integer register to a value. */ 18413557Sgabeblack@google.com void 18513557Sgabeblack@google.com setIntRegOperand(const StaticInst *si, int idx, RegVal val) override 18611147Smitch.hayenga@arm.com { 18711147Smitch.hayenga@arm.com numIntRegWrites++; 18812106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 18912106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 19012106SRekai.GonzalezAlberquilla@arm.com thread->setIntReg(reg.index(), val); 19111147Smitch.hayenga@arm.com } 19211147Smitch.hayenga@arm.com 19311147Smitch.hayenga@arm.com /** Reads a floating point register in its binary format, instead 19411147Smitch.hayenga@arm.com * of by value. */ 19513557Sgabeblack@google.com RegVal 19613557Sgabeblack@google.com readFloatRegOperandBits(const StaticInst *si, int idx) override 19711147Smitch.hayenga@arm.com { 19811147Smitch.hayenga@arm.com numFpRegReads++; 19912106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 20012106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 20112106SRekai.GonzalezAlberquilla@arm.com return thread->readFloatRegBits(reg.index()); 20211147Smitch.hayenga@arm.com } 20311147Smitch.hayenga@arm.com 20411147Smitch.hayenga@arm.com /** Sets the bits of a floating point register of single width 20511147Smitch.hayenga@arm.com * to a binary value. */ 20613557Sgabeblack@google.com void 20713557Sgabeblack@google.com setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override 20811147Smitch.hayenga@arm.com { 20911147Smitch.hayenga@arm.com numFpRegWrites++; 21012106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 21112106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 21212106SRekai.GonzalezAlberquilla@arm.com thread->setFloatRegBits(reg.index(), val); 21311147Smitch.hayenga@arm.com } 21411147Smitch.hayenga@arm.com 21512109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector register. */ 21613557Sgabeblack@google.com const VecRegContainer & 21712109SRekai.GonzalezAlberquilla@arm.com readVecRegOperand(const StaticInst *si, int idx) const override 21812109SRekai.GonzalezAlberquilla@arm.com { 21912109SRekai.GonzalezAlberquilla@arm.com numVecRegReads++; 22012109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 22112109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 22212109SRekai.GonzalezAlberquilla@arm.com return thread->readVecReg(reg); 22312109SRekai.GonzalezAlberquilla@arm.com } 22412109SRekai.GonzalezAlberquilla@arm.com 22512109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector register for modification. */ 22613557Sgabeblack@google.com VecRegContainer & 22712109SRekai.GonzalezAlberquilla@arm.com getWritableVecRegOperand(const StaticInst *si, int idx) override 22812109SRekai.GonzalezAlberquilla@arm.com { 22912109SRekai.GonzalezAlberquilla@arm.com numVecRegWrites++; 23012109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 23112109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 23212109SRekai.GonzalezAlberquilla@arm.com return thread->getWritableVecReg(reg); 23312109SRekai.GonzalezAlberquilla@arm.com } 23412109SRekai.GonzalezAlberquilla@arm.com 23512109SRekai.GonzalezAlberquilla@arm.com /** Sets a vector register to a value. */ 23613557Sgabeblack@google.com void 23713557Sgabeblack@google.com setVecRegOperand(const StaticInst *si, int idx, 23813557Sgabeblack@google.com const VecRegContainer& val) override 23912109SRekai.GonzalezAlberquilla@arm.com { 24012109SRekai.GonzalezAlberquilla@arm.com numVecRegWrites++; 24112109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 24212109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 24312109SRekai.GonzalezAlberquilla@arm.com thread->setVecReg(reg, val); 24412109SRekai.GonzalezAlberquilla@arm.com } 24512109SRekai.GonzalezAlberquilla@arm.com 24612109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 24712109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 24812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector lane. */ 24912109SRekai.GonzalezAlberquilla@arm.com template <typename VecElem> 25012109SRekai.GonzalezAlberquilla@arm.com VecLaneT<VecElem, true> 25112109SRekai.GonzalezAlberquilla@arm.com readVecLaneOperand(const StaticInst *si, int idx) const 25212109SRekai.GonzalezAlberquilla@arm.com { 25312109SRekai.GonzalezAlberquilla@arm.com numVecRegReads++; 25412109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 25512109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 25612109SRekai.GonzalezAlberquilla@arm.com return thread->readVecLane<VecElem>(reg); 25712109SRekai.GonzalezAlberquilla@arm.com } 25812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 25912109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 26012109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneOperand(const StaticInst *si, int idx) const 26112109SRekai.GonzalezAlberquilla@arm.com override 26212109SRekai.GonzalezAlberquilla@arm.com { return readVecLaneOperand<uint8_t>(si, idx); } 26312109SRekai.GonzalezAlberquilla@arm.com 26412109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 26512109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 26612109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneOperand(const StaticInst *si, int idx) const 26712109SRekai.GonzalezAlberquilla@arm.com override 26812109SRekai.GonzalezAlberquilla@arm.com { return readVecLaneOperand<uint16_t>(si, idx); } 26912109SRekai.GonzalezAlberquilla@arm.com 27012109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 27112109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 27212109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneOperand(const StaticInst *si, int idx) const 27312109SRekai.GonzalezAlberquilla@arm.com override 27412109SRekai.GonzalezAlberquilla@arm.com { return readVecLaneOperand<uint32_t>(si, idx); } 27512109SRekai.GonzalezAlberquilla@arm.com 27612109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 27712109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 27812109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneOperand(const StaticInst *si, int idx) const 27912109SRekai.GonzalezAlberquilla@arm.com override 28012109SRekai.GonzalezAlberquilla@arm.com { return readVecLaneOperand<uint64_t>(si, idx); } 28112109SRekai.GonzalezAlberquilla@arm.com 28212109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector operand. */ 28312109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 28412109SRekai.GonzalezAlberquilla@arm.com void 28512109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(const StaticInst *si, int idx, 28612109SRekai.GonzalezAlberquilla@arm.com const LD& val) 28712109SRekai.GonzalezAlberquilla@arm.com { 28812109SRekai.GonzalezAlberquilla@arm.com numVecRegWrites++; 28912109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 29012109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 29112109SRekai.GonzalezAlberquilla@arm.com return thread->setVecLane(reg, val); 29212109SRekai.GonzalezAlberquilla@arm.com } 29312109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector operand. */ 29412109SRekai.GonzalezAlberquilla@arm.com virtual void 29512109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 29612109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) override 29712109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneOperandT(si, idx, val); } 29812109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector operand. */ 29912109SRekai.GonzalezAlberquilla@arm.com virtual void 30012109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 30112109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) override 30212109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneOperandT(si, idx, val); } 30312109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector operand. */ 30412109SRekai.GonzalezAlberquilla@arm.com virtual void 30512109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 30612109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) override 30712109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneOperandT(si, idx, val); } 30812109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector operand. */ 30912109SRekai.GonzalezAlberquilla@arm.com virtual void 31012109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 31112109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) override 31212109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneOperandT(si, idx, val); } 31312109SRekai.GonzalezAlberquilla@arm.com /** @} */ 31412109SRekai.GonzalezAlberquilla@arm.com 31512109SRekai.GonzalezAlberquilla@arm.com /** Reads an element of a vector register. */ 31613557Sgabeblack@google.com VecElem 31713557Sgabeblack@google.com readVecElemOperand(const StaticInst *si, int idx) const override 31812109SRekai.GonzalezAlberquilla@arm.com { 31912109SRekai.GonzalezAlberquilla@arm.com numVecRegReads++; 32012109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 32112109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecElem()); 32212109SRekai.GonzalezAlberquilla@arm.com return thread->readVecElem(reg); 32312109SRekai.GonzalezAlberquilla@arm.com } 32412109SRekai.GonzalezAlberquilla@arm.com 32512109SRekai.GonzalezAlberquilla@arm.com /** Sets an element of a vector register to a value. */ 32613557Sgabeblack@google.com void 32713557Sgabeblack@google.com setVecElemOperand(const StaticInst *si, int idx, 32813557Sgabeblack@google.com const VecElem val) override 32912109SRekai.GonzalezAlberquilla@arm.com { 33012109SRekai.GonzalezAlberquilla@arm.com numVecRegWrites++; 33112109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 33212109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecElem()); 33312109SRekai.GonzalezAlberquilla@arm.com thread->setVecElem(reg, val); 33412109SRekai.GonzalezAlberquilla@arm.com } 33512109SRekai.GonzalezAlberquilla@arm.com 33613557Sgabeblack@google.com CCReg 33713557Sgabeblack@google.com readCCRegOperand(const StaticInst *si, int idx) override 33811147Smitch.hayenga@arm.com { 33911147Smitch.hayenga@arm.com numCCRegReads++; 34012106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 34112106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 34212106SRekai.GonzalezAlberquilla@arm.com return thread->readCCReg(reg.index()); 34311147Smitch.hayenga@arm.com } 34411147Smitch.hayenga@arm.com 34513557Sgabeblack@google.com void 34613557Sgabeblack@google.com setCCRegOperand(const StaticInst *si, int idx, CCReg val) override 34711147Smitch.hayenga@arm.com { 34811147Smitch.hayenga@arm.com numCCRegWrites++; 34912106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 35012106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 35112106SRekai.GonzalezAlberquilla@arm.com thread->setCCReg(reg.index(), val); 35211147Smitch.hayenga@arm.com } 35311147Smitch.hayenga@arm.com 35413557Sgabeblack@google.com RegVal 35513557Sgabeblack@google.com readMiscRegOperand(const StaticInst *si, int idx) override 35611147Smitch.hayenga@arm.com { 35711147Smitch.hayenga@arm.com numIntRegReads++; 35812106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 35912106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 36012106SRekai.GonzalezAlberquilla@arm.com return thread->readMiscReg(reg.index()); 36111147Smitch.hayenga@arm.com } 36211147Smitch.hayenga@arm.com 36313557Sgabeblack@google.com void 36413557Sgabeblack@google.com setMiscRegOperand(const StaticInst *si, int idx, 36513557Sgabeblack@google.com const RegVal &val) override 36611147Smitch.hayenga@arm.com { 36711147Smitch.hayenga@arm.com numIntRegWrites++; 36812106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 36912106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 37012106SRekai.GonzalezAlberquilla@arm.com thread->setMiscReg(reg.index(), val); 37111147Smitch.hayenga@arm.com } 37211147Smitch.hayenga@arm.com 37311147Smitch.hayenga@arm.com /** 37411147Smitch.hayenga@arm.com * Reads a miscellaneous register, handling any architectural 37511147Smitch.hayenga@arm.com * side effects due to reading that register. 37611147Smitch.hayenga@arm.com */ 37713557Sgabeblack@google.com RegVal 37813557Sgabeblack@google.com readMiscReg(int misc_reg) override 37911147Smitch.hayenga@arm.com { 38011147Smitch.hayenga@arm.com numIntRegReads++; 38111147Smitch.hayenga@arm.com return thread->readMiscReg(misc_reg); 38211147Smitch.hayenga@arm.com } 38311147Smitch.hayenga@arm.com 38411147Smitch.hayenga@arm.com /** 38511147Smitch.hayenga@arm.com * Sets a miscellaneous register, handling any architectural 38611147Smitch.hayenga@arm.com * side effects due to writing that register. 38711147Smitch.hayenga@arm.com */ 38813557Sgabeblack@google.com void 38913557Sgabeblack@google.com setMiscReg(int misc_reg, const RegVal &val) override 39011147Smitch.hayenga@arm.com { 39111147Smitch.hayenga@arm.com numIntRegWrites++; 39211147Smitch.hayenga@arm.com thread->setMiscReg(misc_reg, val); 39311147Smitch.hayenga@arm.com } 39411147Smitch.hayenga@arm.com 39513557Sgabeblack@google.com PCState 39613557Sgabeblack@google.com pcState() const override 39711147Smitch.hayenga@arm.com { 39811147Smitch.hayenga@arm.com return thread->pcState(); 39911147Smitch.hayenga@arm.com } 40011147Smitch.hayenga@arm.com 40113557Sgabeblack@google.com void 40213557Sgabeblack@google.com pcState(const PCState &val) override 40311147Smitch.hayenga@arm.com { 40411147Smitch.hayenga@arm.com thread->pcState(val); 40511147Smitch.hayenga@arm.com } 40611147Smitch.hayenga@arm.com 40711147Smitch.hayenga@arm.com 40813557Sgabeblack@google.com Fault 40913557Sgabeblack@google.com readMem(Addr addr, uint8_t *data, unsigned int size, 41013557Sgabeblack@google.com Request::Flags flags) override 41111147Smitch.hayenga@arm.com { 41211147Smitch.hayenga@arm.com return cpu->readMem(addr, data, size, flags); 41311147Smitch.hayenga@arm.com } 41411147Smitch.hayenga@arm.com 41513557Sgabeblack@google.com Fault 41613557Sgabeblack@google.com initiateMemRead(Addr addr, unsigned int size, 41713557Sgabeblack@google.com Request::Flags flags) override 41811303Ssteve.reinhardt@amd.com { 41911303Ssteve.reinhardt@amd.com return cpu->initiateMemRead(addr, size, flags); 42011303Ssteve.reinhardt@amd.com } 42111303Ssteve.reinhardt@amd.com 42213557Sgabeblack@google.com Fault 42313557Sgabeblack@google.com writeMem(uint8_t *data, unsigned int size, Addr addr, 42413557Sgabeblack@google.com Request::Flags flags, uint64_t *res) override 42511147Smitch.hayenga@arm.com { 42611147Smitch.hayenga@arm.com return cpu->writeMem(data, size, addr, flags, res); 42711147Smitch.hayenga@arm.com } 42811147Smitch.hayenga@arm.com 42911147Smitch.hayenga@arm.com /** 43011147Smitch.hayenga@arm.com * Sets the number of consecutive store conditional failures. 43111147Smitch.hayenga@arm.com */ 43213557Sgabeblack@google.com void 43313557Sgabeblack@google.com setStCondFailures(unsigned int sc_failures) override 43411147Smitch.hayenga@arm.com { 43511147Smitch.hayenga@arm.com thread->setStCondFailures(sc_failures); 43611147Smitch.hayenga@arm.com } 43711147Smitch.hayenga@arm.com 43811147Smitch.hayenga@arm.com /** 43911147Smitch.hayenga@arm.com * Returns the number of consecutive store conditional failures. 44011147Smitch.hayenga@arm.com */ 44113557Sgabeblack@google.com unsigned int 44213557Sgabeblack@google.com readStCondFailures() const override 44311147Smitch.hayenga@arm.com { 44411147Smitch.hayenga@arm.com return thread->readStCondFailures(); 44511147Smitch.hayenga@arm.com } 44611147Smitch.hayenga@arm.com 44711147Smitch.hayenga@arm.com /** 44811147Smitch.hayenga@arm.com * Executes a syscall specified by the callnum. 44911147Smitch.hayenga@arm.com */ 45013557Sgabeblack@google.com void 45113557Sgabeblack@google.com syscall(int64_t callnum, Fault *fault) override 45211147Smitch.hayenga@arm.com { 45311147Smitch.hayenga@arm.com if (FullSystem) 45411147Smitch.hayenga@arm.com panic("Syscall emulation isn't available in FS mode."); 45511147Smitch.hayenga@arm.com 45611877Sbrandon.potter@amd.com thread->syscall(callnum, fault); 45711147Smitch.hayenga@arm.com } 45811147Smitch.hayenga@arm.com 45911147Smitch.hayenga@arm.com /** Returns a pointer to the ThreadContext. */ 46013557Sgabeblack@google.com ThreadContext *tcBase() override { return thread->getTC(); } 46111147Smitch.hayenga@arm.com 46211147Smitch.hayenga@arm.com /** 46311147Smitch.hayenga@arm.com * Somewhat Alpha-specific function that handles returning from an 46411147Smitch.hayenga@arm.com * error or interrupt. 46511147Smitch.hayenga@arm.com */ 46613557Sgabeblack@google.com Fault hwrei() override { return thread->hwrei(); } 46711147Smitch.hayenga@arm.com 46811147Smitch.hayenga@arm.com /** 46911147Smitch.hayenga@arm.com * Check for special simulator handling of specific PAL calls. If 47011147Smitch.hayenga@arm.com * return value is false, actual PAL call will be suppressed. 47111147Smitch.hayenga@arm.com */ 47213557Sgabeblack@google.com bool 47313557Sgabeblack@google.com simPalCheck(int palFunc) override 47411147Smitch.hayenga@arm.com { 47511147Smitch.hayenga@arm.com return thread->simPalCheck(palFunc); 47611147Smitch.hayenga@arm.com } 47711147Smitch.hayenga@arm.com 47813557Sgabeblack@google.com bool 47913557Sgabeblack@google.com readPredicate() const override 48011147Smitch.hayenga@arm.com { 48111147Smitch.hayenga@arm.com return thread->readPredicate(); 48211147Smitch.hayenga@arm.com } 48311147Smitch.hayenga@arm.com 48413557Sgabeblack@google.com void 48513557Sgabeblack@google.com setPredicate(bool val) override 48611147Smitch.hayenga@arm.com { 48711147Smitch.hayenga@arm.com thread->setPredicate(val); 48811147Smitch.hayenga@arm.com 48911147Smitch.hayenga@arm.com if (cpu->traceData) { 49011147Smitch.hayenga@arm.com cpu->traceData->setPredicate(val); 49111147Smitch.hayenga@arm.com } 49211147Smitch.hayenga@arm.com } 49311147Smitch.hayenga@arm.com 49411147Smitch.hayenga@arm.com /** 49511147Smitch.hayenga@arm.com * Invalidate a page in the DTLB <i>and</i> ITLB. 49611147Smitch.hayenga@arm.com */ 49713557Sgabeblack@google.com void 49813557Sgabeblack@google.com demapPage(Addr vaddr, uint64_t asn) override 49911147Smitch.hayenga@arm.com { 50011147Smitch.hayenga@arm.com thread->demapPage(vaddr, asn); 50111147Smitch.hayenga@arm.com } 50211147Smitch.hayenga@arm.com 50313557Sgabeblack@google.com void 50413557Sgabeblack@google.com armMonitor(Addr address) override 50511147Smitch.hayenga@arm.com { 50611148Smitch.hayenga@arm.com cpu->armMonitor(thread->threadId(), address); 50711147Smitch.hayenga@arm.com } 50811147Smitch.hayenga@arm.com 50913557Sgabeblack@google.com bool 51013557Sgabeblack@google.com mwait(PacketPtr pkt) override 51111147Smitch.hayenga@arm.com { 51211148Smitch.hayenga@arm.com return cpu->mwait(thread->threadId(), pkt); 51311147Smitch.hayenga@arm.com } 51411147Smitch.hayenga@arm.com 51513557Sgabeblack@google.com void 51613557Sgabeblack@google.com mwaitAtomic(ThreadContext *tc) override 51711147Smitch.hayenga@arm.com { 51811148Smitch.hayenga@arm.com cpu->mwaitAtomic(thread->threadId(), tc, thread->dtb); 51911147Smitch.hayenga@arm.com } 52011147Smitch.hayenga@arm.com 52113557Sgabeblack@google.com AddressMonitor * 52213557Sgabeblack@google.com getAddrMonitor() override 52311147Smitch.hayenga@arm.com { 52411148Smitch.hayenga@arm.com return cpu->getCpuAddrMonitor(thread->threadId()); 52511147Smitch.hayenga@arm.com } 52611147Smitch.hayenga@arm.com 52711147Smitch.hayenga@arm.com#if THE_ISA == MIPS_ISA 52813557Sgabeblack@google.com RegVal 52913557Sgabeblack@google.com readRegOtherThread(const RegId& reg, ThreadID tid=InvalidThreadID) 53011168Sandreas.hansson@arm.com override 53111147Smitch.hayenga@arm.com { 53211147Smitch.hayenga@arm.com panic("Simple CPU models do not support multithreaded " 53311147Smitch.hayenga@arm.com "register access."); 53411147Smitch.hayenga@arm.com } 53511147Smitch.hayenga@arm.com 53613557Sgabeblack@google.com void 53713557Sgabeblack@google.com setRegOtherThread(const RegId& reg, RegVal val, 53813557Sgabeblack@google.com ThreadID tid=InvalidThreadID) override 53911147Smitch.hayenga@arm.com { 54011147Smitch.hayenga@arm.com panic("Simple CPU models do not support multithreaded " 54111147Smitch.hayenga@arm.com "register access."); 54211147Smitch.hayenga@arm.com } 54311147Smitch.hayenga@arm.com#endif 54411147Smitch.hayenga@arm.com 54511147Smitch.hayenga@arm.com}; 54611147Smitch.hayenga@arm.com 54711147Smitch.hayenga@arm.com#endif // __CPU_EXEC_CONTEXT_HH__ 548