base.hh revision 7725:00ea9430643b
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Dave Greene
30 *          Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "arch/predecoder.hh"
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "config/the_isa.hh"
40#include "cpu/base.hh"
41#include "cpu/simple_thread.hh"
42#include "cpu/pc_event.hh"
43#include "cpu/static_inst.hh"
44#include "mem/packet.hh"
45#include "mem/port.hh"
46#include "mem/request.hh"
47#include "sim/eventq.hh"
48#include "sim/system.hh"
49
50// forward declarations
51#if FULL_SYSTEM
52class Processor;
53namespace TheISA
54{
55    class ITB;
56    class DTB;
57}
58class MemObject;
59
60#else
61
62class Process;
63
64#endif // FULL_SYSTEM
65
66namespace TheISA
67{
68    class Predecoder;
69}
70class ThreadContext;
71class Checkpoint;
72
73namespace Trace {
74    class InstRecord;
75}
76
77class BaseSimpleCPUParams;
78
79
80class BaseSimpleCPU : public BaseCPU
81{
82  protected:
83    typedef TheISA::MiscReg MiscReg;
84    typedef TheISA::FloatReg FloatReg;
85    typedef TheISA::FloatRegBits FloatRegBits;
86
87  protected:
88    Trace::InstRecord *traceData;
89
90    inline void checkPcEventQueue() {
91        Addr oldpc, pc = thread->instAddr();
92        do {
93            oldpc = pc;
94            system->pcEventQueue.service(tc);
95            pc = thread->instAddr();
96        } while (oldpc != pc);
97    }
98
99  public:
100    void wakeup();
101
102    void zero_fill_64(Addr addr) {
103      static int warned = 0;
104      if (!warned) {
105        warn ("WH64 is not implemented");
106        warned = 1;
107      }
108    };
109
110  public:
111    BaseSimpleCPU(BaseSimpleCPUParams *params);
112    virtual ~BaseSimpleCPU();
113
114  public:
115    /** SimpleThread object, provides all the architectural state. */
116    SimpleThread *thread;
117
118    /** ThreadContext object, provides an interface for external
119     * objects to modify this thread's state.
120     */
121    ThreadContext *tc;
122  protected:
123
124    enum Status {
125        Idle,
126        Running,
127        ITBWaitResponse,
128        IcacheRetry,
129        IcacheWaitResponse,
130        IcacheWaitSwitch,
131        DTBWaitResponse,
132        DcacheRetry,
133        DcacheWaitResponse,
134        DcacheWaitSwitch,
135        SwitchedOut
136    };
137
138    Status _status;
139
140  public:
141
142#if FULL_SYSTEM
143    Addr dbg_vtophys(Addr addr);
144
145    bool interval_stats;
146#endif
147
148    // current instruction
149    TheISA::MachInst inst;
150
151    // The predecoder
152    TheISA::Predecoder predecoder;
153
154    StaticInstPtr curStaticInst;
155    StaticInstPtr curMacroStaticInst;
156
157    //This is the offset from the current pc that fetch should be performed at
158    Addr fetchOffset;
159    //This flag says to stay at the current pc. This is useful for
160    //instructions which go beyond MachInst boundaries.
161    bool stayAtPC;
162
163    void checkForInterrupts();
164    void setupFetchRequest(Request *req);
165    void preExecute();
166    void postExecute();
167    void advancePC(Fault fault);
168
169    virtual void deallocateContext(int thread_num);
170    virtual void haltContext(int thread_num);
171
172    // statistics
173    virtual void regStats();
174    virtual void resetStats();
175
176    // number of simulated instructions
177    Counter numInst;
178    Counter startNumInst;
179    Stats::Scalar numInsts;
180
181    void countInst()
182    {
183        numInst++;
184        numInsts++;
185
186        thread->funcExeInst++;
187    }
188
189    virtual Counter totalInstructions() const
190    {
191        return numInst - startNumInst;
192    }
193
194    // Mask to align PCs to MachInst sized boundaries
195    static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
196
197    // number of simulated memory references
198    Stats::Scalar numMemRefs;
199
200    // number of simulated loads
201    Counter numLoad;
202    Counter startNumLoad;
203
204    // number of idle cycles
205    Stats::Average notIdleFraction;
206    Stats::Formula idleFraction;
207
208    // number of cycles stalled for I-cache responses
209    Stats::Scalar icacheStallCycles;
210    Counter lastIcacheStall;
211
212    // number of cycles stalled for I-cache retries
213    Stats::Scalar icacheRetryCycles;
214    Counter lastIcacheRetry;
215
216    // number of cycles stalled for D-cache responses
217    Stats::Scalar dcacheStallCycles;
218    Counter lastDcacheStall;
219
220    // number of cycles stalled for D-cache retries
221    Stats::Scalar dcacheRetryCycles;
222    Counter lastDcacheRetry;
223
224    virtual void serialize(std::ostream &os);
225    virtual void unserialize(Checkpoint *cp, const std::string &section);
226
227    // These functions are only used in CPU models that split
228    // effective address computation from the actual memory access.
229    void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
230    Addr getEA()        { panic("BaseSimpleCPU::getEA() not implemented\n");
231        M5_DUMMY_RETURN}
232
233    // The register accessor methods provide the index of the
234    // instruction's operand (e.g., 0 or 1), not the architectural
235    // register index, to simplify the implementation of register
236    // renaming.  We find the architectural register index by indexing
237    // into the instruction's own operand index table.  Note that a
238    // raw pointer to the StaticInst is provided instead of a
239    // ref-counted StaticInstPtr to redice overhead.  This is fine as
240    // long as these methods don't copy the pointer into any long-term
241    // storage (which is pretty hard to imagine they would have reason
242    // to do).
243
244    uint64_t readIntRegOperand(const StaticInst *si, int idx)
245    {
246        return thread->readIntReg(si->srcRegIdx(idx));
247    }
248
249    FloatReg readFloatRegOperand(const StaticInst *si, int idx)
250    {
251        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
252        return thread->readFloatReg(reg_idx);
253    }
254
255    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
256    {
257        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
258        return thread->readFloatRegBits(reg_idx);
259    }
260
261    void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
262    {
263        thread->setIntReg(si->destRegIdx(idx), val);
264    }
265
266    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
267    {
268        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
269        thread->setFloatReg(reg_idx, val);
270    }
271
272    void setFloatRegOperandBits(const StaticInst *si, int idx,
273                                FloatRegBits val)
274    {
275        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
276        thread->setFloatRegBits(reg_idx, val);
277    }
278
279    bool readPredicate() { return thread->readPredicate(); }
280    void setPredicate(bool val)
281    {
282        thread->setPredicate(val);
283        if (traceData) {
284            traceData->setPredicate(val);
285        }
286    }
287    TheISA::PCState pcState() { return thread->pcState(); }
288    void pcState(const TheISA::PCState &val) { thread->pcState(val); }
289    Addr instAddr() { return thread->instAddr(); }
290    Addr nextInstAddr() { return thread->nextInstAddr(); }
291    MicroPC microPC() { return thread->microPC(); }
292
293    MiscReg readMiscRegNoEffect(int misc_reg)
294    {
295        return thread->readMiscRegNoEffect(misc_reg);
296    }
297
298    MiscReg readMiscReg(int misc_reg)
299    {
300        return thread->readMiscReg(misc_reg);
301    }
302
303    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
304    {
305        return thread->setMiscRegNoEffect(misc_reg, val);
306    }
307
308    void setMiscReg(int misc_reg, const MiscReg &val)
309    {
310        return thread->setMiscReg(misc_reg, val);
311    }
312
313    MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
314    {
315        int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
316        return thread->readMiscRegNoEffect(reg_idx);
317    }
318
319    MiscReg readMiscRegOperand(const StaticInst *si, int idx)
320    {
321        int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
322        return thread->readMiscReg(reg_idx);
323    }
324
325    void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
326    {
327        int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
328        return thread->setMiscRegNoEffect(reg_idx, val);
329    }
330
331    void setMiscRegOperand(
332            const StaticInst *si, int idx, const MiscReg &val)
333    {
334        int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
335        return thread->setMiscReg(reg_idx, val);
336    }
337
338    void demapPage(Addr vaddr, uint64_t asn)
339    {
340        thread->demapPage(vaddr, asn);
341    }
342
343    void demapInstPage(Addr vaddr, uint64_t asn)
344    {
345        thread->demapInstPage(vaddr, asn);
346    }
347
348    void demapDataPage(Addr vaddr, uint64_t asn)
349    {
350        thread->demapDataPage(vaddr, asn);
351    }
352
353    unsigned readStCondFailures() {
354        return thread->readStCondFailures();
355    }
356
357    void setStCondFailures(unsigned sc_failures) {
358        thread->setStCondFailures(sc_failures);
359    }
360
361     MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
362     {
363        panic("Simple CPU models do not support multithreaded "
364              "register access.\n");
365     }
366
367     void setRegOtherThread(int regIdx, const MiscReg &val,
368                            ThreadID tid = InvalidThreadID)
369     {
370        panic("Simple CPU models do not support multithreaded "
371              "register access.\n");
372     }
373
374    //Fault CacheOp(uint8_t Op, Addr EA);
375
376#if FULL_SYSTEM
377    Fault hwrei() { return thread->hwrei(); }
378    bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
379#else
380    void syscall(int64_t callnum) { thread->syscall(callnum); }
381#endif
382
383    bool misspeculating() { return thread->misspeculating(); }
384    ThreadContext *tcBase() { return tc; }
385};
386
387#endif // __CPU_SIMPLE_BASE_HH__
388