base.hh revision 6314:781969fbeca9
113531Sjairo.balart@metempsy.com/* 214167Sgiacomo.travaglini@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 314167Sgiacomo.travaglini@arm.com * All rights reserved. 414167Sgiacomo.travaglini@arm.com * 514167Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 614167Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 714167Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 814167Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 914167Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1014167Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 1114167Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 1214167Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 1314167Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 1413531Sjairo.balart@metempsy.com * this software without specific prior written permission. 1513531Sjairo.balart@metempsy.com * 1613531Sjairo.balart@metempsy.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1713531Sjairo.balart@metempsy.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1813531Sjairo.balart@metempsy.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1913531Sjairo.balart@metempsy.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2013531Sjairo.balart@metempsy.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2113531Sjairo.balart@metempsy.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2213531Sjairo.balart@metempsy.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2313531Sjairo.balart@metempsy.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2413531Sjairo.balart@metempsy.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2513531Sjairo.balart@metempsy.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2613531Sjairo.balart@metempsy.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2713531Sjairo.balart@metempsy.com * 2813531Sjairo.balart@metempsy.com * Authors: Steve Reinhardt 2913531Sjairo.balart@metempsy.com * Dave Greene 3013531Sjairo.balart@metempsy.com * Nathan Binkert 3113531Sjairo.balart@metempsy.com */ 3213531Sjairo.balart@metempsy.com 3313531Sjairo.balart@metempsy.com#ifndef __CPU_SIMPLE_BASE_HH__ 3413531Sjairo.balart@metempsy.com#define __CPU_SIMPLE_BASE_HH__ 3513531Sjairo.balart@metempsy.com 3613531Sjairo.balart@metempsy.com#include "arch/predecoder.hh" 3713531Sjairo.balart@metempsy.com#include "base/statistics.hh" 3813531Sjairo.balart@metempsy.com#include "config/full_system.hh" 3913531Sjairo.balart@metempsy.com#include "cpu/base.hh" 4013531Sjairo.balart@metempsy.com#include "cpu/simple_thread.hh" 4113531Sjairo.balart@metempsy.com#include "cpu/pc_event.hh" 4213756Sjairo.balart@metempsy.com#include "cpu/static_inst.hh" 4313531Sjairo.balart@metempsy.com#include "mem/packet.hh" 4413531Sjairo.balart@metempsy.com#include "mem/port.hh" 4513531Sjairo.balart@metempsy.com#include "mem/request.hh" 4613531Sjairo.balart@metempsy.com#include "sim/eventq.hh" 4714257Sgiacomo.travaglini@arm.com#include "sim/system.hh" 4813531Sjairo.balart@metempsy.com 4913531Sjairo.balart@metempsy.com// forward declarations 5013531Sjairo.balart@metempsy.com#if FULL_SYSTEM 5113531Sjairo.balart@metempsy.comclass Processor; 5213531Sjairo.balart@metempsy.comnamespace TheISA 5313756Sjairo.balart@metempsy.com{ 5413756Sjairo.balart@metempsy.com class ITB; 5513756Sjairo.balart@metempsy.com class DTB; 5613756Sjairo.balart@metempsy.com} 5713756Sjairo.balart@metempsy.comclass MemObject; 5813756Sjairo.balart@metempsy.com 5913756Sjairo.balart@metempsy.com#else 6013531Sjairo.balart@metempsy.com 6113756Sjairo.balart@metempsy.comclass Process; 6213756Sjairo.balart@metempsy.com 6313756Sjairo.balart@metempsy.com#endif // FULL_SYSTEM 6413756Sjairo.balart@metempsy.com 6513756Sjairo.balart@metempsy.comclass RemoteGDB; 6613756Sjairo.balart@metempsy.comclass GDBListener; 6713756Sjairo.balart@metempsy.com 6813531Sjairo.balart@metempsy.comnamespace TheISA 6913531Sjairo.balart@metempsy.com{ 7013531Sjairo.balart@metempsy.com class Predecoder; 7113531Sjairo.balart@metempsy.com} 7214258Sgiacomo.travaglini@arm.comclass ThreadContext; 7314258Sgiacomo.travaglini@arm.comclass Checkpoint; 7414258Sgiacomo.travaglini@arm.com 7514258Sgiacomo.travaglini@arm.comnamespace Trace { 7614258Sgiacomo.travaglini@arm.com class InstRecord; 7714258Sgiacomo.travaglini@arm.com} 7814258Sgiacomo.travaglini@arm.com 7914258Sgiacomo.travaglini@arm.comclass BaseSimpleCPUParams; 8014258Sgiacomo.travaglini@arm.com 8114258Sgiacomo.travaglini@arm.com 8214258Sgiacomo.travaglini@arm.comclass BaseSimpleCPU : public BaseCPU 8314258Sgiacomo.travaglini@arm.com{ 8414258Sgiacomo.travaglini@arm.com protected: 8514257Sgiacomo.travaglini@arm.com typedef TheISA::MiscReg MiscReg; 8614167Sgiacomo.travaglini@arm.com typedef TheISA::FloatReg FloatReg; 8714167Sgiacomo.travaglini@arm.com typedef TheISA::FloatRegBits FloatRegBits; 8814167Sgiacomo.travaglini@arm.com 8914167Sgiacomo.travaglini@arm.com protected: 9014167Sgiacomo.travaglini@arm.com Trace::InstRecord *traceData; 9113531Sjairo.balart@metempsy.com 9213531Sjairo.balart@metempsy.com inline void checkPcEventQueue() { 9314257Sgiacomo.travaglini@arm.com Addr oldpc; 9414257Sgiacomo.travaglini@arm.com do { 9514257Sgiacomo.travaglini@arm.com oldpc = thread->readPC(); 9614257Sgiacomo.travaglini@arm.com system->pcEventQueue.service(tc); 9714257Sgiacomo.travaglini@arm.com } while (oldpc != thread->readPC()); 9814257Sgiacomo.travaglini@arm.com } 9914257Sgiacomo.travaglini@arm.com 10014257Sgiacomo.travaglini@arm.com public: 10114257Sgiacomo.travaglini@arm.com void wakeup(); 10214257Sgiacomo.travaglini@arm.com 10314257Sgiacomo.travaglini@arm.com void zero_fill_64(Addr addr) { 10414257Sgiacomo.travaglini@arm.com static int warned = 0; 10514257Sgiacomo.travaglini@arm.com if (!warned) { 10614257Sgiacomo.travaglini@arm.com warn ("WH64 is not implemented"); 10714257Sgiacomo.travaglini@arm.com warned = 1; 10814257Sgiacomo.travaglini@arm.com } 10914257Sgiacomo.travaglini@arm.com }; 11014257Sgiacomo.travaglini@arm.com 11114257Sgiacomo.travaglini@arm.com public: 11214257Sgiacomo.travaglini@arm.com BaseSimpleCPU(BaseSimpleCPUParams *params); 11314257Sgiacomo.travaglini@arm.com virtual ~BaseSimpleCPU(); 11414257Sgiacomo.travaglini@arm.com 11514257Sgiacomo.travaglini@arm.com public: 11614257Sgiacomo.travaglini@arm.com /** SimpleThread object, provides all the architectural state. */ 11714257Sgiacomo.travaglini@arm.com SimpleThread *thread; 11814257Sgiacomo.travaglini@arm.com 11914257Sgiacomo.travaglini@arm.com /** ThreadContext object, provides an interface for external 12014257Sgiacomo.travaglini@arm.com * objects to modify this thread's state. 12114257Sgiacomo.travaglini@arm.com */ 12214257Sgiacomo.travaglini@arm.com ThreadContext *tc; 12314257Sgiacomo.travaglini@arm.com protected: 12413531Sjairo.balart@metempsy.com 12513531Sjairo.balart@metempsy.com enum Status { 12613531Sjairo.balart@metempsy.com Idle, 12713531Sjairo.balart@metempsy.com Running, 12813531Sjairo.balart@metempsy.com ITBWaitResponse, 12913531Sjairo.balart@metempsy.com IcacheRetry, 13014258Sgiacomo.travaglini@arm.com IcacheWaitResponse, 13113531Sjairo.balart@metempsy.com IcacheWaitSwitch, 13214258Sgiacomo.travaglini@arm.com DTBWaitResponse, 13314258Sgiacomo.travaglini@arm.com DcacheRetry, 13414258Sgiacomo.travaglini@arm.com DcacheWaitResponse, 13513531Sjairo.balart@metempsy.com DcacheWaitSwitch, 13613531Sjairo.balart@metempsy.com SwitchedOut 13713531Sjairo.balart@metempsy.com }; 13813531Sjairo.balart@metempsy.com 13913531Sjairo.balart@metempsy.com Status _status; 14013531Sjairo.balart@metempsy.com 14113531Sjairo.balart@metempsy.com public: 14213531Sjairo.balart@metempsy.com 14313531Sjairo.balart@metempsy.com#if FULL_SYSTEM 14413531Sjairo.balart@metempsy.com Addr dbg_vtophys(Addr addr); 14513531Sjairo.balart@metempsy.com 14613531Sjairo.balart@metempsy.com bool interval_stats; 14713531Sjairo.balart@metempsy.com#endif 14813531Sjairo.balart@metempsy.com 14913531Sjairo.balart@metempsy.com // current instruction 15013531Sjairo.balart@metempsy.com TheISA::MachInst inst; 15113531Sjairo.balart@metempsy.com 15213531Sjairo.balart@metempsy.com // The predecoder 15313531Sjairo.balart@metempsy.com TheISA::Predecoder predecoder; 15413531Sjairo.balart@metempsy.com 15513756Sjairo.balart@metempsy.com StaticInstPtr curStaticInst; 15613531Sjairo.balart@metempsy.com StaticInstPtr curMacroStaticInst; 15713531Sjairo.balart@metempsy.com 15813531Sjairo.balart@metempsy.com //This is the offset from the current pc that fetch should be performed at 15913531Sjairo.balart@metempsy.com Addr fetchOffset; 16013756Sjairo.balart@metempsy.com //This flag says to stay at the current pc. This is useful for 16113531Sjairo.balart@metempsy.com //instructions which go beyond MachInst boundaries. 16213531Sjairo.balart@metempsy.com bool stayAtPC; 16313531Sjairo.balart@metempsy.com 16413531Sjairo.balart@metempsy.com void checkForInterrupts(); 16513531Sjairo.balart@metempsy.com void setupFetchRequest(Request *req); 16613531Sjairo.balart@metempsy.com void preExecute(); 16713531Sjairo.balart@metempsy.com void postExecute(); 16813531Sjairo.balart@metempsy.com void advancePC(Fault fault); 16913531Sjairo.balart@metempsy.com 17013756Sjairo.balart@metempsy.com virtual void deallocateContext(int thread_num); 17113756Sjairo.balart@metempsy.com virtual void haltContext(int thread_num); 17213531Sjairo.balart@metempsy.com 17313531Sjairo.balart@metempsy.com // statistics 17413531Sjairo.balart@metempsy.com virtual void regStats(); 17513531Sjairo.balart@metempsy.com virtual void resetStats(); 17613531Sjairo.balart@metempsy.com 17713531Sjairo.balart@metempsy.com // number of simulated instructions 17813531Sjairo.balart@metempsy.com Counter numInst; 17913531Sjairo.balart@metempsy.com Counter startNumInst; 18013531Sjairo.balart@metempsy.com Stats::Scalar numInsts; 18113531Sjairo.balart@metempsy.com 18213531Sjairo.balart@metempsy.com void countInst() 18313531Sjairo.balart@metempsy.com { 18413531Sjairo.balart@metempsy.com numInst++; 18513531Sjairo.balart@metempsy.com numInsts++; 18613531Sjairo.balart@metempsy.com 18713531Sjairo.balart@metempsy.com thread->funcExeInst++; 18813531Sjairo.balart@metempsy.com } 18913531Sjairo.balart@metempsy.com 19013531Sjairo.balart@metempsy.com virtual Counter totalInstructions() const 19113756Sjairo.balart@metempsy.com { 19213756Sjairo.balart@metempsy.com return numInst - startNumInst; 19313531Sjairo.balart@metempsy.com } 19413531Sjairo.balart@metempsy.com 19513531Sjairo.balart@metempsy.com // Mask to align PCs to MachInst sized boundaries 19613531Sjairo.balart@metempsy.com static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 19713531Sjairo.balart@metempsy.com 19813531Sjairo.balart@metempsy.com // number of simulated memory references 19913531Sjairo.balart@metempsy.com Stats::Scalar numMemRefs; 20013531Sjairo.balart@metempsy.com 20113531Sjairo.balart@metempsy.com // number of simulated loads 20213531Sjairo.balart@metempsy.com Counter numLoad; 20313756Sjairo.balart@metempsy.com Counter startNumLoad; 20413531Sjairo.balart@metempsy.com 20513531Sjairo.balart@metempsy.com // number of idle cycles 20613531Sjairo.balart@metempsy.com Stats::Average notIdleFraction; 20713531Sjairo.balart@metempsy.com Stats::Formula idleFraction; 20813531Sjairo.balart@metempsy.com 20913531Sjairo.balart@metempsy.com // number of cycles stalled for I-cache responses 21013531Sjairo.balart@metempsy.com Stats::Scalar icacheStallCycles; 21113531Sjairo.balart@metempsy.com Counter lastIcacheStall; 21213756Sjairo.balart@metempsy.com 21313756Sjairo.balart@metempsy.com // number of cycles stalled for I-cache retries 21413531Sjairo.balart@metempsy.com Stats::Scalar icacheRetryCycles; 21513531Sjairo.balart@metempsy.com Counter lastIcacheRetry; 21613531Sjairo.balart@metempsy.com 21713531Sjairo.balart@metempsy.com // number of cycles stalled for D-cache responses 21813531Sjairo.balart@metempsy.com Stats::Scalar dcacheStallCycles; 21913531Sjairo.balart@metempsy.com Counter lastDcacheStall; 22013531Sjairo.balart@metempsy.com 22113531Sjairo.balart@metempsy.com // number of cycles stalled for D-cache retries 22213531Sjairo.balart@metempsy.com Stats::Scalar dcacheRetryCycles; 22313531Sjairo.balart@metempsy.com Counter lastDcacheRetry; 22413531Sjairo.balart@metempsy.com 22513531Sjairo.balart@metempsy.com virtual void serialize(std::ostream &os); 22613531Sjairo.balart@metempsy.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 22713756Sjairo.balart@metempsy.com 22813531Sjairo.balart@metempsy.com // These functions are only used in CPU models that split 22913531Sjairo.balart@metempsy.com // effective address computation from the actual memory access. 23013531Sjairo.balart@metempsy.com void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 23113531Sjairo.balart@metempsy.com Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); 23213531Sjairo.balart@metempsy.com M5_DUMMY_RETURN} 23313531Sjairo.balart@metempsy.com 23413531Sjairo.balart@metempsy.com void prefetch(Addr addr, unsigned flags) 23513531Sjairo.balart@metempsy.com { 23613756Sjairo.balart@metempsy.com // need to do this... 23713756Sjairo.balart@metempsy.com } 23813531Sjairo.balart@metempsy.com 23913531Sjairo.balart@metempsy.com void writeHint(Addr addr, int size, unsigned flags) 24013531Sjairo.balart@metempsy.com { 24113531Sjairo.balart@metempsy.com // need to do this... 24213531Sjairo.balart@metempsy.com } 24313531Sjairo.balart@metempsy.com 24413531Sjairo.balart@metempsy.com 24513531Sjairo.balart@metempsy.com Fault copySrcTranslate(Addr src); 24613531Sjairo.balart@metempsy.com 24713531Sjairo.balart@metempsy.com Fault copy(Addr dest); 24813531Sjairo.balart@metempsy.com 24913531Sjairo.balart@metempsy.com // The register accessor methods provide the index of the 25013756Sjairo.balart@metempsy.com // instruction's operand (e.g., 0 or 1), not the architectural 25113531Sjairo.balart@metempsy.com // register index, to simplify the implementation of register 25213531Sjairo.balart@metempsy.com // renaming. We find the architectural register index by indexing 25313531Sjairo.balart@metempsy.com // into the instruction's own operand index table. Note that a 25413531Sjairo.balart@metempsy.com // raw pointer to the StaticInst is provided instead of a 25513531Sjairo.balart@metempsy.com // ref-counted StaticInstPtr to redice overhead. This is fine as 25613531Sjairo.balart@metempsy.com // long as these methods don't copy the pointer into any long-term 25713531Sjairo.balart@metempsy.com // storage (which is pretty hard to imagine they would have reason 25813531Sjairo.balart@metempsy.com // to do). 25913531Sjairo.balart@metempsy.com 26013531Sjairo.balart@metempsy.com uint64_t readIntRegOperand(const StaticInst *si, int idx) 26113756Sjairo.balart@metempsy.com { 26213756Sjairo.balart@metempsy.com return thread->readIntReg(si->srcRegIdx(idx)); 26313531Sjairo.balart@metempsy.com } 26413531Sjairo.balart@metempsy.com 26513531Sjairo.balart@metempsy.com FloatReg readFloatRegOperand(const StaticInst *si, int idx) 26613531Sjairo.balart@metempsy.com { 26713531Sjairo.balart@metempsy.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 26813531Sjairo.balart@metempsy.com return thread->readFloatReg(reg_idx); 26913531Sjairo.balart@metempsy.com } 27013531Sjairo.balart@metempsy.com 27113531Sjairo.balart@metempsy.com FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 27213531Sjairo.balart@metempsy.com { 27313531Sjairo.balart@metempsy.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 27413531Sjairo.balart@metempsy.com return thread->readFloatRegBits(reg_idx); 27513756Sjairo.balart@metempsy.com } 27613531Sjairo.balart@metempsy.com 27713531Sjairo.balart@metempsy.com void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 27813531Sjairo.balart@metempsy.com { 27913531Sjairo.balart@metempsy.com thread->setIntReg(si->destRegIdx(idx), val); 28013531Sjairo.balart@metempsy.com } 28113531Sjairo.balart@metempsy.com 28213531Sjairo.balart@metempsy.com void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 28313531Sjairo.balart@metempsy.com { 28413531Sjairo.balart@metempsy.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 28513531Sjairo.balart@metempsy.com thread->setFloatReg(reg_idx, val); 28613756Sjairo.balart@metempsy.com } 28713756Sjairo.balart@metempsy.com 28813531Sjairo.balart@metempsy.com void setFloatRegOperandBits(const StaticInst *si, int idx, 28913531Sjairo.balart@metempsy.com FloatRegBits val) 29013531Sjairo.balart@metempsy.com { 29113531Sjairo.balart@metempsy.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 29213531Sjairo.balart@metempsy.com thread->setFloatRegBits(reg_idx, val); 29313531Sjairo.balart@metempsy.com } 29413531Sjairo.balart@metempsy.com 29513531Sjairo.balart@metempsy.com uint64_t readPC() { return thread->readPC(); } 29613531Sjairo.balart@metempsy.com uint64_t readMicroPC() { return thread->readMicroPC(); } 29713531Sjairo.balart@metempsy.com uint64_t readNextPC() { return thread->readNextPC(); } 29813531Sjairo.balart@metempsy.com uint64_t readNextMicroPC() { return thread->readNextMicroPC(); } 29913756Sjairo.balart@metempsy.com uint64_t readNextNPC() { return thread->readNextNPC(); } 30013531Sjairo.balart@metempsy.com 30113531Sjairo.balart@metempsy.com void setPC(uint64_t val) { thread->setPC(val); } 30213531Sjairo.balart@metempsy.com void setMicroPC(uint64_t val) { thread->setMicroPC(val); } 30313531Sjairo.balart@metempsy.com void setNextPC(uint64_t val) { thread->setNextPC(val); } 30413531Sjairo.balart@metempsy.com void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); } 30513531Sjairo.balart@metempsy.com void setNextNPC(uint64_t val) { thread->setNextNPC(val); } 30613531Sjairo.balart@metempsy.com 30713531Sjairo.balart@metempsy.com MiscReg readMiscRegNoEffect(int misc_reg) 30813531Sjairo.balart@metempsy.com { 30913756Sjairo.balart@metempsy.com return thread->readMiscRegNoEffect(misc_reg); 31013756Sjairo.balart@metempsy.com } 31113531Sjairo.balart@metempsy.com 31213531Sjairo.balart@metempsy.com MiscReg readMiscReg(int misc_reg) 31313531Sjairo.balart@metempsy.com { 31413531Sjairo.balart@metempsy.com return thread->readMiscReg(misc_reg); 31513531Sjairo.balart@metempsy.com } 31613531Sjairo.balart@metempsy.com 31713531Sjairo.balart@metempsy.com void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 31813531Sjairo.balart@metempsy.com { 31913531Sjairo.balart@metempsy.com return thread->setMiscRegNoEffect(misc_reg, val); 32013531Sjairo.balart@metempsy.com } 32113531Sjairo.balart@metempsy.com 32213531Sjairo.balart@metempsy.com void setMiscReg(int misc_reg, const MiscReg &val) 32313531Sjairo.balart@metempsy.com { 32413531Sjairo.balart@metempsy.com return thread->setMiscReg(misc_reg, val); 32513531Sjairo.balart@metempsy.com } 32613531Sjairo.balart@metempsy.com 32713531Sjairo.balart@metempsy.com MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) 32813531Sjairo.balart@metempsy.com { 32913531Sjairo.balart@metempsy.com int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 33013531Sjairo.balart@metempsy.com return thread->readMiscRegNoEffect(reg_idx); 33113531Sjairo.balart@metempsy.com } 33213531Sjairo.balart@metempsy.com 33313756Sjairo.balart@metempsy.com MiscReg readMiscRegOperand(const StaticInst *si, int idx) 33413531Sjairo.balart@metempsy.com { 33513531Sjairo.balart@metempsy.com int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 33613531Sjairo.balart@metempsy.com return thread->readMiscReg(reg_idx); 33713531Sjairo.balart@metempsy.com } 33813531Sjairo.balart@metempsy.com 33913531Sjairo.balart@metempsy.com void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val) 34013531Sjairo.balart@metempsy.com { 34113531Sjairo.balart@metempsy.com int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 34213531Sjairo.balart@metempsy.com return thread->setMiscRegNoEffect(reg_idx, val); 34313531Sjairo.balart@metempsy.com } 34413756Sjairo.balart@metempsy.com 34513756Sjairo.balart@metempsy.com void setMiscRegOperand( 34613531Sjairo.balart@metempsy.com const StaticInst *si, int idx, const MiscReg &val) 34713531Sjairo.balart@metempsy.com { 34813531Sjairo.balart@metempsy.com int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 34913531Sjairo.balart@metempsy.com return thread->setMiscReg(reg_idx, val); 35013531Sjairo.balart@metempsy.com } 35113531Sjairo.balart@metempsy.com 35213531Sjairo.balart@metempsy.com void demapPage(Addr vaddr, uint64_t asn) 35313531Sjairo.balart@metempsy.com { 35413531Sjairo.balart@metempsy.com thread->demapPage(vaddr, asn); 35513531Sjairo.balart@metempsy.com } 35613531Sjairo.balart@metempsy.com 35713531Sjairo.balart@metempsy.com void demapInstPage(Addr vaddr, uint64_t asn) 35813531Sjairo.balart@metempsy.com { 35913531Sjairo.balart@metempsy.com thread->demapInstPage(vaddr, asn); 36013531Sjairo.balart@metempsy.com } 36113531Sjairo.balart@metempsy.com 36213531Sjairo.balart@metempsy.com void demapDataPage(Addr vaddr, uint64_t asn) 36313531Sjairo.balart@metempsy.com { 36413531Sjairo.balart@metempsy.com thread->demapDataPage(vaddr, asn); 36513531Sjairo.balart@metempsy.com } 36613531Sjairo.balart@metempsy.com 36713531Sjairo.balart@metempsy.com unsigned readStCondFailures() { 36813531Sjairo.balart@metempsy.com return thread->readStCondFailures(); 36913531Sjairo.balart@metempsy.com } 37013531Sjairo.balart@metempsy.com 37113531Sjairo.balart@metempsy.com void setStCondFailures(unsigned sc_failures) { 37213531Sjairo.balart@metempsy.com thread->setStCondFailures(sc_failures); 37313531Sjairo.balart@metempsy.com } 37413531Sjairo.balart@metempsy.com 37513531Sjairo.balart@metempsy.com MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID) 37613756Sjairo.balart@metempsy.com { 37713531Sjairo.balart@metempsy.com panic("Simple CPU models do not support multithreaded " 37813531Sjairo.balart@metempsy.com "register access.\n"); 37913531Sjairo.balart@metempsy.com } 38013531Sjairo.balart@metempsy.com 38113531Sjairo.balart@metempsy.com void setRegOtherThread(int regIdx, const MiscReg &val, 38213531Sjairo.balart@metempsy.com ThreadID tid = InvalidThreadID) 38313756Sjairo.balart@metempsy.com { 38413531Sjairo.balart@metempsy.com panic("Simple CPU models do not support multithreaded " 38513531Sjairo.balart@metempsy.com "register access.\n"); 38613531Sjairo.balart@metempsy.com } 38713531Sjairo.balart@metempsy.com 38813531Sjairo.balart@metempsy.com //Fault CacheOp(uint8_t Op, Addr EA); 38913531Sjairo.balart@metempsy.com 39013531Sjairo.balart@metempsy.com#if FULL_SYSTEM 39113531Sjairo.balart@metempsy.com Fault hwrei() { return thread->hwrei(); } 39213531Sjairo.balart@metempsy.com void ev5_trap(Fault fault) { fault->invoke(tc); } 39313531Sjairo.balart@metempsy.com bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 39413531Sjairo.balart@metempsy.com#else 39513531Sjairo.balart@metempsy.com void syscall(int64_t callnum) { thread->syscall(callnum); } 39613531Sjairo.balart@metempsy.com#endif 39713531Sjairo.balart@metempsy.com 39813531Sjairo.balart@metempsy.com bool misspeculating() { return thread->misspeculating(); } 39913756Sjairo.balart@metempsy.com ThreadContext *tcBase() { return tc; } 40013531Sjairo.balart@metempsy.com}; 40113531Sjairo.balart@metempsy.com 40213531Sjairo.balart@metempsy.com#endif // __CPU_SIMPLE_BASE_HH__ 40313531Sjairo.balart@metempsy.com