base.hh revision 3735:86a7cf4dcc11
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Dave Greene
30 *          Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "base/statistics.hh"
37#include "config/full_system.hh"
38#include "cpu/base.hh"
39#include "cpu/simple_thread.hh"
40#include "cpu/pc_event.hh"
41#include "cpu/static_inst.hh"
42#include "mem/packet.hh"
43#include "mem/port.hh"
44#include "mem/request.hh"
45#include "sim/eventq.hh"
46
47// forward declarations
48#if FULL_SYSTEM
49class Processor;
50namespace TheISA
51{
52    class ITB;
53    class DTB;
54}
55class MemObject;
56
57class RemoteGDB;
58class GDBListener;
59
60#else
61
62class Process;
63
64#endif // FULL_SYSTEM
65
66class ThreadContext;
67class Checkpoint;
68
69namespace Trace {
70    class InstRecord;
71}
72
73
74class BaseSimpleCPU : public BaseCPU
75{
76  protected:
77    typedef TheISA::MachInst MachInst;
78    typedef TheISA::MiscReg MiscReg;
79    typedef TheISA::FloatReg FloatReg;
80    typedef TheISA::FloatRegBits FloatRegBits;
81
82  protected:
83    Trace::InstRecord *traceData;
84
85  public:
86    void post_interrupt(int int_num, int index);
87
88    void zero_fill_64(Addr addr) {
89      static int warned = 0;
90      if (!warned) {
91        warn ("WH64 is not implemented");
92        warned = 1;
93      }
94    };
95
96  public:
97    struct Params : public BaseCPU::Params
98    {
99#if FULL_SYSTEM
100        TheISA::ITB *itb;
101        TheISA::DTB *dtb;
102#else
103        Process *process;
104#endif
105    };
106    BaseSimpleCPU(Params *params);
107    virtual ~BaseSimpleCPU();
108
109  public:
110    /** SimpleThread object, provides all the architectural state. */
111    SimpleThread *thread;
112
113    /** ThreadContext object, provides an interface for external
114     * objects to modify this thread's state.
115     */
116    ThreadContext *tc;
117
118#if FULL_SYSTEM
119    Addr dbg_vtophys(Addr addr);
120
121    bool interval_stats;
122#endif
123
124    // current instruction
125    MachInst inst;
126
127    // Static data storage
128    TheISA::IntReg dataReg;
129
130    StaticInstPtr curStaticInst;
131    StaticInstPtr curMacroStaticInst;
132
133    void checkForInterrupts();
134    Fault setupFetchRequest(Request *req);
135    void preExecute();
136    void postExecute();
137    void advancePC(Fault fault);
138
139    virtual void deallocateContext(int thread_num);
140    virtual void haltContext(int thread_num);
141
142    // statistics
143    virtual void regStats();
144    virtual void resetStats();
145
146    // number of simulated instructions
147    Counter numInst;
148    Counter startNumInst;
149    Stats::Scalar<> numInsts;
150
151    virtual Counter totalInstructions() const
152    {
153        return numInst - startNumInst;
154    }
155
156    // number of simulated memory references
157    Stats::Scalar<> numMemRefs;
158
159    // number of simulated loads
160    Counter numLoad;
161    Counter startNumLoad;
162
163    // number of idle cycles
164    Stats::Average<> notIdleFraction;
165    Stats::Formula idleFraction;
166
167    // number of cycles stalled for I-cache responses
168    Stats::Scalar<> icacheStallCycles;
169    Counter lastIcacheStall;
170
171    // number of cycles stalled for I-cache retries
172    Stats::Scalar<> icacheRetryCycles;
173    Counter lastIcacheRetry;
174
175    // number of cycles stalled for D-cache responses
176    Stats::Scalar<> dcacheStallCycles;
177    Counter lastDcacheStall;
178
179    // number of cycles stalled for D-cache retries
180    Stats::Scalar<> dcacheRetryCycles;
181    Counter lastDcacheRetry;
182
183    virtual void serialize(std::ostream &os);
184    virtual void unserialize(Checkpoint *cp, const std::string &section);
185
186    // These functions are only used in CPU models that split
187    // effective address computation from the actual memory access.
188    void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
189    Addr getEA() 	{ panic("BaseSimpleCPU::getEA() not implemented\n"); }
190
191    void prefetch(Addr addr, unsigned flags)
192    {
193        // need to do this...
194    }
195
196    void writeHint(Addr addr, int size, unsigned flags)
197    {
198        // need to do this...
199    }
200
201    Fault copySrcTranslate(Addr src);
202
203    Fault copy(Addr dest);
204
205    // The register accessor methods provide the index of the
206    // instruction's operand (e.g., 0 or 1), not the architectural
207    // register index, to simplify the implementation of register
208    // renaming.  We find the architectural register index by indexing
209    // into the instruction's own operand index table.  Note that a
210    // raw pointer to the StaticInst is provided instead of a
211    // ref-counted StaticInstPtr to redice overhead.  This is fine as
212    // long as these methods don't copy the pointer into any long-term
213    // storage (which is pretty hard to imagine they would have reason
214    // to do).
215
216    uint64_t readIntRegOperand(const StaticInst *si, int idx)
217    {
218        return thread->readIntReg(si->srcRegIdx(idx));
219    }
220
221    FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
222    {
223        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
224        return thread->readFloatReg(reg_idx, width);
225    }
226
227    FloatReg readFloatRegOperand(const StaticInst *si, int idx)
228    {
229        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
230        return thread->readFloatReg(reg_idx);
231    }
232
233    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
234                                         int width)
235    {
236        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
237        return thread->readFloatRegBits(reg_idx, width);
238    }
239
240    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
241    {
242        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
243        return thread->readFloatRegBits(reg_idx);
244    }
245
246    void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
247    {
248        thread->setIntReg(si->destRegIdx(idx), val);
249    }
250
251    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
252                            int width)
253    {
254        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
255        thread->setFloatReg(reg_idx, val, width);
256    }
257
258    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
259    {
260        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
261        thread->setFloatReg(reg_idx, val);
262    }
263
264    void setFloatRegOperandBits(const StaticInst *si, int idx,
265                                FloatRegBits val, int width)
266    {
267        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
268        thread->setFloatRegBits(reg_idx, val, width);
269    }
270
271    void setFloatRegOperandBits(const StaticInst *si, int idx,
272                                FloatRegBits val)
273    {
274        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
275        thread->setFloatRegBits(reg_idx, val);
276    }
277
278    uint64_t readPC() { return thread->readPC(); }
279    uint64_t readNextPC() { return thread->readNextPC(); }
280    uint64_t readNextNPC() { return thread->readNextNPC(); }
281
282    void setPC(uint64_t val) { thread->setPC(val); }
283    void setNextPC(uint64_t val) { thread->setNextPC(val); }
284    void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
285
286    MiscReg readMiscReg(int misc_reg)
287    {
288        return thread->readMiscReg(misc_reg);
289    }
290
291    MiscReg readMiscRegWithEffect(int misc_reg)
292    {
293        return thread->readMiscRegWithEffect(misc_reg);
294    }
295
296    void setMiscReg(int misc_reg, const MiscReg &val)
297    {
298        return thread->setMiscReg(misc_reg, val);
299    }
300
301    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
302    {
303        return thread->setMiscRegWithEffect(misc_reg, val);
304    }
305
306#if FULL_SYSTEM
307    Fault hwrei() { return thread->hwrei(); }
308    void ev5_trap(Fault fault) { fault->invoke(tc); }
309    bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
310#else
311    void syscall(int64_t callnum) { thread->syscall(callnum); }
312#endif
313
314    bool misspeculating() { return thread->misspeculating(); }
315    ThreadContext *tcBase() { return tc; }
316};
317
318#endif // __CPU_SIMPLE_BASE_HH__
319