base.hh revision 2390
16019Shines@cs.fsu.edu/* 210037SARM gem5 Developers * Copyright (c) 2002-2005 The Regents of The University of Michigan 37414SAli.Saidi@ARM.com * All rights reserved. 47414SAli.Saidi@ARM.com * 57414SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67414SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77414SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87414SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97414SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107414SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117414SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127414SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137414SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 146019Shines@cs.fsu.edu * this software without specific prior written permission. 156019Shines@cs.fsu.edu * 166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019Shines@cs.fsu.edu */ 286019Shines@cs.fsu.edu 296019Shines@cs.fsu.edu#ifndef __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ 306019Shines@cs.fsu.edu#define __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ 316019Shines@cs.fsu.edu 326019Shines@cs.fsu.edu#include "base/statistics.hh" 336019Shines@cs.fsu.edu#include "config/full_system.hh" 346019Shines@cs.fsu.edu#include "cpu/base.hh" 356019Shines@cs.fsu.edu#include "cpu/exec_context.hh" 366019Shines@cs.fsu.edu#include "cpu/pc_event.hh" 376019Shines@cs.fsu.edu#include "cpu/sampler/sampler.hh" 386019Shines@cs.fsu.edu#include "cpu/static_inst.hh" 396019Shines@cs.fsu.edu#include "mem/packet.hh" 406019Shines@cs.fsu.edu#include "mem/port.hh" 417414SAli.Saidi@ARM.com#include "mem/request.hh" 426019Shines@cs.fsu.edu#include "sim/eventq.hh" 436019Shines@cs.fsu.edu 4411793Sbrandon.potter@amd.com// forward declarations 4511793Sbrandon.potter@amd.com#if FULL_SYSTEM 466019Shines@cs.fsu.educlass Processor; 476019Shines@cs.fsu.educlass AlphaITB; 486019Shines@cs.fsu.educlass AlphaDTB; 496019Shines@cs.fsu.educlass PhysicalMemory; 506019Shines@cs.fsu.edu 516019Shines@cs.fsu.educlass RemoteGDB; 528232Snate@binkert.orgclass GDBListener; 536019Shines@cs.fsu.edu 547678Sgblack@eecs.umich.edu#else 556019Shines@cs.fsu.edu 566019Shines@cs.fsu.educlass Process; 576019Shines@cs.fsu.edu 586019Shines@cs.fsu.edu#endif // FULL_SYSTEM 596019Shines@cs.fsu.edu 606019Shines@cs.fsu.educlass MemInterface; 617096Sgblack@eecs.umich.educlass Checkpoint; 627096Sgblack@eecs.umich.edu 637096Sgblack@eecs.umich.edunamespace Trace { 646019Shines@cs.fsu.edu class InstRecord; 6510037SARM gem5 Developers} 6610037SARM gem5 Developers 6710037SARM gem5 Developersclass SimpleCPU : public BaseCPU 6810037SARM gem5 Developers{ 6910037SARM gem5 Developers class CpuPort : public Port 7010037SARM gem5 Developers { 716400Sgblack@eecs.umich.edu 726019Shines@cs.fsu.edu SimpleCPU *cpu; 736019Shines@cs.fsu.edu 746019Shines@cs.fsu.edu public: 756019Shines@cs.fsu.edu 766019Shines@cs.fsu.edu CpuPort(SimpleCPU *_cpu) 776019Shines@cs.fsu.edu : cpu(_cpu) 7810318Sandreas.hansson@arm.com { } 796019Shines@cs.fsu.edu 806019Shines@cs.fsu.edu protected: 8111386Ssteve.reinhardt@amd.com 826019Shines@cs.fsu.edu virtual bool recvTiming(Packet &pkt) 836019Shines@cs.fsu.edu { cpu->processCacheCompletion(pkt); return true; } 8410037SARM gem5 Developers 8510037SARM gem5 Developers virtual Tick recvAtomic(Packet &pkt) 8610037SARM gem5 Developers { panic("CPU doesn't expect callback!"); return curTick; } 8710037SARM gem5 Developers 8810037SARM gem5 Developers virtual void recvFunctional(Packet &pkt) 8910037SARM gem5 Developers { panic("CPU doesn't expect callback!"); } 9010037SARM gem5 Developers 9110037SARM gem5 Developers virtual void recvStatusChange(Status status) 9210037SARM gem5 Developers { cpu->recvStatusChange(status); } 9310037SARM gem5 Developers 9410037SARM gem5 Developers virtual Packet *recvRetry() { return cpu->processRetry(); } 9510318Sandreas.hansson@arm.com }; 9610037SARM gem5 Developers 9710037SARM gem5 Developers CpuPort icachePort; 9811386Ssteve.reinhardt@amd.com CpuPort dcachePort; 9910037SARM gem5 Developers 10010037SARM gem5 Developers public: 1016019Shines@cs.fsu.edu // main simulation loop (one cycle) 10210037SARM gem5 Developers void tick(); 1036019Shines@cs.fsu.edu 1048216Ssaidi@eecs.umich.edu private: 10510318Sandreas.hansson@arm.com struct TickEvent : public Event 1067640Sgblack@eecs.umich.edu { 1077640Sgblack@eecs.umich.edu SimpleCPU *cpu; 1087640Sgblack@eecs.umich.edu int width; 1097640Sgblack@eecs.umich.edu 1107640Sgblack@eecs.umich.edu TickEvent(SimpleCPU *c, int w); 1117640Sgblack@eecs.umich.edu void process(); 1127640Sgblack@eecs.umich.edu const char *description(); 1137640Sgblack@eecs.umich.edu }; 1147640Sgblack@eecs.umich.edu 1157640Sgblack@eecs.umich.edu TickEvent tickEvent; 1167640Sgblack@eecs.umich.edu 1177640Sgblack@eecs.umich.edu /// Schedule tick event, regardless of its current state. 1186019Shines@cs.fsu.edu void scheduleTickEvent(int numCycles) 1196019Shines@cs.fsu.edu { 1206019Shines@cs.fsu.edu if (tickEvent.squashed()) 12110037SARM gem5 Developers tickEvent.reschedule(curTick + cycles(numCycles)); 1226019Shines@cs.fsu.edu else if (!tickEvent.scheduled()) 12310037SARM gem5 Developers tickEvent.schedule(curTick + cycles(numCycles)); 12410318Sandreas.hansson@arm.com } 12510037SARM gem5 Developers 12610037SARM gem5 Developers /// Unschedule tick event, regardless of its current state. 12710037SARM gem5 Developers void unscheduleTickEvent() 12810037SARM gem5 Developers { 12910037SARM gem5 Developers if (tickEvent.scheduled()) 13010037SARM gem5 Developers tickEvent.squash(); 13110037SARM gem5 Developers } 13210037SARM gem5 Developers 13310037SARM gem5 Developers private: 13410037SARM gem5 Developers Trace::InstRecord *traceData; 13510037SARM gem5 Developers 13610037SARM gem5 Developers public: 13710037SARM gem5 Developers // 13810037SARM gem5 Developers enum Status { 13910037SARM gem5 Developers Running, 14010037SARM gem5 Developers Idle, 14110037SARM gem5 Developers IcacheRetry, 14210037SARM gem5 Developers IcacheWaitResponse, 14310037SARM gem5 Developers IcacheAccessComplete, 14410037SARM gem5 Developers DcacheRetry, 14510037SARM gem5 Developers DcacheWaitResponse, 14610037SARM gem5 Developers DcacheWaitSwitch, 14710037SARM gem5 Developers SwitchedOut 14810037SARM gem5 Developers }; 1496400Sgblack@eecs.umich.edu 1506400Sgblack@eecs.umich.edu private: 1516400Sgblack@eecs.umich.edu Status _status; 1526400Sgblack@eecs.umich.edu 1536400Sgblack@eecs.umich.edu public: 1546400Sgblack@eecs.umich.edu void post_interrupt(int int_num, int index); 1556400Sgblack@eecs.umich.edu 1566400Sgblack@eecs.umich.edu void zero_fill_64(Addr addr) { 1576400Sgblack@eecs.umich.edu static int warned = 0; 1586400Sgblack@eecs.umich.edu if (!warned) { 1596400Sgblack@eecs.umich.edu warn ("WH64 is not implemented"); 16011389Sbrandon.potter@amd.com warned = 1; 16111389Sbrandon.potter@amd.com } 16211389Sbrandon.potter@amd.com }; 1636019Shines@cs.fsu.edu 1646019Shines@cs.fsu.edu public: 1656019Shines@cs.fsu.edu struct Params : public BaseCPU::Params 1666400Sgblack@eecs.umich.edu { 1676400Sgblack@eecs.umich.edu int width; 1686400Sgblack@eecs.umich.edu#if FULL_SYSTEM 1696400Sgblack@eecs.umich.edu AlphaITB *itb; 1706400Sgblack@eecs.umich.edu AlphaDTB *dtb; 1716400Sgblack@eecs.umich.edu FunctionalMemory *mem; 1726400Sgblack@eecs.umich.edu#else 1736400Sgblack@eecs.umich.edu Process *process; 1746400Sgblack@eecs.umich.edu#endif 1756400Sgblack@eecs.umich.edu }; 1766400Sgblack@eecs.umich.edu SimpleCPU(Params *params); 1777414SAli.Saidi@ARM.com virtual ~SimpleCPU(); 1787414SAli.Saidi@ARM.com 1797414SAli.Saidi@ARM.com public: 1807414SAli.Saidi@ARM.com // execution context 1817414SAli.Saidi@ARM.com ExecContext *xc; 1826400Sgblack@eecs.umich.edu 1836400Sgblack@eecs.umich.edu void switchOut(Sampler *s); 1846400Sgblack@eecs.umich.edu void takeOverFrom(BaseCPU *oldCPU); 1856400Sgblack@eecs.umich.edu 1866400Sgblack@eecs.umich.edu#if FULL_SYSTEM 1876400Sgblack@eecs.umich.edu Addr dbg_vtophys(Addr addr); 1886400Sgblack@eecs.umich.edu 18910810Sbr@bsdpad.com bool interval_stats; 19010810Sbr@bsdpad.com#endif 19110810Sbr@bsdpad.com 19210810Sbr@bsdpad.com // current instruction 19310810Sbr@bsdpad.com MachInst inst; 19410810Sbr@bsdpad.com 19510810Sbr@bsdpad.com CpuRequest *req; 19610810Sbr@bsdpad.com Packet *pkt; 19710810Sbr@bsdpad.com 19810810Sbr@bsdpad.com // Pointer to the sampler that is telling us to switchover. 19910810Sbr@bsdpad.com // Used to signal the completion of the pipe drain and schedule 20010810Sbr@bsdpad.com // the next switchover 20110810Sbr@bsdpad.com Sampler *sampler; 20210810Sbr@bsdpad.com 20310810Sbr@bsdpad.com StaticInstPtr<TheISA> curStaticInst; 20410810Sbr@bsdpad.com 20510810Sbr@bsdpad.com Status status() const { return _status; } 20610810Sbr@bsdpad.com 20710810Sbr@bsdpad.com virtual void activateContext(int thread_num, int delay); 20810810Sbr@bsdpad.com virtual void suspendContext(int thread_num); 20910810Sbr@bsdpad.com virtual void deallocateContext(int thread_num); 21010810Sbr@bsdpad.com virtual void haltContext(int thread_num); 21110810Sbr@bsdpad.com 21210810Sbr@bsdpad.com // statistics 21310810Sbr@bsdpad.com virtual void regStats(); 21410810Sbr@bsdpad.com virtual void resetStats(); 21510810Sbr@bsdpad.com 21610810Sbr@bsdpad.com // number of simulated instructions 21710810Sbr@bsdpad.com Counter numInst; 21810810Sbr@bsdpad.com Counter startNumInst; 21910810Sbr@bsdpad.com Stats::Scalar<> numInsts; 22010810Sbr@bsdpad.com 22110810Sbr@bsdpad.com virtual Counter totalInstructions() const 22210810Sbr@bsdpad.com { 2236400Sgblack@eecs.umich.edu return numInst - startNumInst; 22410318Sandreas.hansson@arm.com } 2256400Sgblack@eecs.umich.edu 2266400Sgblack@eecs.umich.edu // number of simulated memory references 2276400Sgblack@eecs.umich.edu Stats::Scalar<> numMemRefs; 2286400Sgblack@eecs.umich.edu 2296400Sgblack@eecs.umich.edu // number of simulated loads 2306400Sgblack@eecs.umich.edu Counter numLoad; 2316400Sgblack@eecs.umich.edu Counter startNumLoad; 23211389Sbrandon.potter@amd.com 23311389Sbrandon.potter@amd.com // number of idle cycles 23411389Sbrandon.potter@amd.com Stats::Average<> notIdleFraction; 23511389Sbrandon.potter@amd.com Stats::Formula idleFraction; 2366400Sgblack@eecs.umich.edu 2376400Sgblack@eecs.umich.edu // number of cycles stalled for I-cache responses 2386400Sgblack@eecs.umich.edu Stats::Scalar<> icacheStallCycles; 2396400Sgblack@eecs.umich.edu Counter lastIcacheStall; 2406400Sgblack@eecs.umich.edu 2416400Sgblack@eecs.umich.edu // number of cycles stalled for I-cache retries 2426400Sgblack@eecs.umich.edu Stats::Scalar<> icacheRetryCycles; 2436400Sgblack@eecs.umich.edu Counter lastIcacheRetry; 2446400Sgblack@eecs.umich.edu 2456400Sgblack@eecs.umich.edu // number of cycles stalled for D-cache responses 2466400Sgblack@eecs.umich.edu Stats::Scalar<> dcacheStallCycles; 2476400Sgblack@eecs.umich.edu Counter lastDcacheStall; 2486400Sgblack@eecs.umich.edu 2496400Sgblack@eecs.umich.edu // number of cycles stalled for D-cache retries 2506400Sgblack@eecs.umich.edu Stats::Scalar<> dcacheRetryCycles; 2516400Sgblack@eecs.umich.edu Counter lastDcacheRetry; 2527414SAli.Saidi@ARM.com 2536400Sgblack@eecs.umich.edu void sendIcacheRequest(); 2546400Sgblack@eecs.umich.edu void sendDcacheRequest(); 2557414SAli.Saidi@ARM.com void processResponse(Packet *response); 2567414SAli.Saidi@ARM.com 2577414SAli.Saidi@ARM.com virtual void serialize(std::ostream &os); 2586400Sgblack@eecs.umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 2596400Sgblack@eecs.umich.edu 2606400Sgblack@eecs.umich.edu template <class T> 2616400Sgblack@eecs.umich.edu Fault read(Addr addr, T &data, unsigned flags); 2626400Sgblack@eecs.umich.edu 2636400Sgblack@eecs.umich.edu template <class T> 2646400Sgblack@eecs.umich.edu Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 2656400Sgblack@eecs.umich.edu 2666400Sgblack@eecs.umich.edu // These functions are only used in CPU models that split 2676400Sgblack@eecs.umich.edu // effective address computation from the actual memory access. 2686019Shines@cs.fsu.edu void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 2696019Shines@cs.fsu.edu Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 2706019Shines@cs.fsu.edu 2716019Shines@cs.fsu.edu void prefetch(Addr addr, unsigned flags) 2726400Sgblack@eecs.umich.edu { 2736400Sgblack@eecs.umich.edu // need to do this... 2746400Sgblack@eecs.umich.edu } 2757414SAli.Saidi@ARM.com 2766400Sgblack@eecs.umich.edu void writeHint(Addr addr, int size, unsigned flags) 2776400Sgblack@eecs.umich.edu { 2786400Sgblack@eecs.umich.edu // need to do this... 2796400Sgblack@eecs.umich.edu } 2806400Sgblack@eecs.umich.edu 2816400Sgblack@eecs.umich.edu Fault copySrcTranslate(Addr src); 2826400Sgblack@eecs.umich.edu 2836400Sgblack@eecs.umich.edu Fault copy(Addr dest); 2846400Sgblack@eecs.umich.edu 2856400Sgblack@eecs.umich.edu // The register accessor methods provide the index of the 2866400Sgblack@eecs.umich.edu // instruction's operand (e.g., 0 or 1), not the architectural 2876400Sgblack@eecs.umich.edu // register index, to simplify the implementation of register 2886400Sgblack@eecs.umich.edu // renaming. We find the architectural register index by indexing 2896400Sgblack@eecs.umich.edu // into the instruction's own operand index table. Note that a 2906400Sgblack@eecs.umich.edu // raw pointer to the StaticInst is provided instead of a 2916400Sgblack@eecs.umich.edu // ref-counted StaticInstPtr to redice overhead. This is fine as 2926400Sgblack@eecs.umich.edu // long as these methods don't copy the pointer into any long-term 2936400Sgblack@eecs.umich.edu // storage (which is pretty hard to imagine they would have reason 2946400Sgblack@eecs.umich.edu // to do). 2956400Sgblack@eecs.umich.edu 2966400Sgblack@eecs.umich.edu uint64_t readIntReg(const StaticInst<TheISA> *si, int idx) 2976400Sgblack@eecs.umich.edu { 2986400Sgblack@eecs.umich.edu return xc->readIntReg(si->srcRegIdx(idx)); 2996400Sgblack@eecs.umich.edu } 3006400Sgblack@eecs.umich.edu 3016400Sgblack@eecs.umich.edu float readFloatRegSingle(const StaticInst<TheISA> *si, int idx) 3026400Sgblack@eecs.umich.edu { 3036400Sgblack@eecs.umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 3046400Sgblack@eecs.umich.edu return xc->readFloatRegSingle(reg_idx); 3056400Sgblack@eecs.umich.edu } 3068601Ssteve.reinhardt@amd.com 3076400Sgblack@eecs.umich.edu double readFloatRegDouble(const StaticInst<TheISA> *si, int idx) 3086400Sgblack@eecs.umich.edu { 30910037SARM gem5 Developers int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 31010037SARM gem5 Developers return xc->readFloatRegDouble(reg_idx); 31110037SARM gem5 Developers } 31210037SARM gem5 Developers 31310037SARM gem5 Developers uint64_t readFloatRegInt(const StaticInst<TheISA> *si, int idx) 31410037SARM gem5 Developers { 31510037SARM gem5 Developers int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 31610037SARM gem5 Developers return xc->readFloatRegInt(reg_idx); 31710037SARM gem5 Developers } 31810037SARM gem5 Developers 3196400Sgblack@eecs.umich.edu void setIntReg(const StaticInst<TheISA> *si, int idx, uint64_t val) 3206400Sgblack@eecs.umich.edu { 3216400Sgblack@eecs.umich.edu xc->setIntReg(si->destRegIdx(idx), val); 3226400Sgblack@eecs.umich.edu } 3236400Sgblack@eecs.umich.edu 3247414SAli.Saidi@ARM.com void setFloatRegSingle(const StaticInst<TheISA> *si, int idx, float val) 3256400Sgblack@eecs.umich.edu { 3266400Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 3276400Sgblack@eecs.umich.edu xc->setFloatRegSingle(reg_idx, val); 3286400Sgblack@eecs.umich.edu } 3296400Sgblack@eecs.umich.edu 3306400Sgblack@eecs.umich.edu void setFloatRegDouble(const StaticInst<TheISA> *si, int idx, double val) 3316400Sgblack@eecs.umich.edu { 3326400Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 3336400Sgblack@eecs.umich.edu xc->setFloatRegDouble(reg_idx, val); 3346400Sgblack@eecs.umich.edu } 33510037SARM gem5 Developers 33610037SARM gem5 Developers void setFloatRegInt(const StaticInst<TheISA> *si, int idx, uint64_t val) 3376400Sgblack@eecs.umich.edu { 3386400Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 33910037SARM gem5 Developers xc->setFloatRegInt(reg_idx, val); 3408852Sandreas.hansson@arm.com } 3416400Sgblack@eecs.umich.edu 3426400Sgblack@eecs.umich.edu uint64_t readPC() { return xc->readPC(); } 3436400Sgblack@eecs.umich.edu void setNextPC(uint64_t val) { xc->setNextPC(val); } 3446400Sgblack@eecs.umich.edu 3456400Sgblack@eecs.umich.edu uint64_t readUniq() { return xc->readUniq(); } 3466400Sgblack@eecs.umich.edu void setUniq(uint64_t val) { xc->setUniq(val); } 3478852Sandreas.hansson@arm.com 3486400Sgblack@eecs.umich.edu uint64_t readFpcr() { return xc->readFpcr(); } 3496400Sgblack@eecs.umich.edu void setFpcr(uint64_t val) { xc->setFpcr(val); } 3508852Sandreas.hansson@arm.com 3517414SAli.Saidi@ARM.com#if FULL_SYSTEM 3527414SAli.Saidi@ARM.com uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); } 3537414SAli.Saidi@ARM.com Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); } 3546400Sgblack@eecs.umich.edu Fault hwrei() { return xc->hwrei(); } 3556019Shines@cs.fsu.edu int readIntrFlag() { return xc->readIntrFlag(); } 3566019Shines@cs.fsu.edu void setIntrFlag(int val) { xc->setIntrFlag(val); } 3576400Sgblack@eecs.umich.edu bool inPalMode() { return xc->inPalMode(); } 35810037SARM gem5 Developers void ev5_trap(Fault fault) { xc->ev5_trap(fault); } 3598852Sandreas.hansson@arm.com bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); } 3606400Sgblack@eecs.umich.edu#else 3618852Sandreas.hansson@arm.com void syscall() { xc->syscall(); } 3626400Sgblack@eecs.umich.edu#endif 3636400Sgblack@eecs.umich.edu 3646400Sgblack@eecs.umich.edu bool misspeculating() { return xc->misspeculating(); } 3656400Sgblack@eecs.umich.edu ExecContext *xcBase() { return xc; } 3668852Sandreas.hansson@arm.com}; 3676400Sgblack@eecs.umich.edu 3686019Shines@cs.fsu.edu#endif // __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ 3696400Sgblack@eecs.umich.edu