base.hh revision 237
1/* 2 * Copyright (c) 2003 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __SIMPLE_CPU_HH__ 30#define __SIMPLE_CPU_HH__ 31 32#include "cpu/base_cpu.hh" 33#include "sim/eventq.hh" 34#include "base/loader/symtab.hh" 35#include "cpu/pc_event.hh" 36#include "base/statistics.hh" 37 38 39// forward declarations 40#ifdef FULL_SYSTEM 41class Processor; 42class Kernel; 43class AlphaItb; 44class AlphaDtb; 45class PhysicalMemory; 46 47class RemoteGDB; 48class GDBListener; 49#endif // FULL_SYSTEM 50 51class MemInterface; 52class Checkpoint; 53 54namespace Trace { 55 class InstRecord; 56} 57 58class SimpleCPU : public BaseCPU 59{ 60 public: 61 // main simulation loop (one cycle) 62 void tick(); 63 64 private: 65 class TickEvent : public Event 66 { 67 private: 68 SimpleCPU *cpu; 69 70 public: 71 TickEvent(SimpleCPU *c); 72 void process(); 73 const char *description(); 74 }; 75 76 TickEvent tickEvent; 77 78 private: 79 Trace::InstRecord *traceData; 80 template<typename T> 81 void trace_data(T data) { 82 if (traceData) { 83 traceData->setData(data); 84 } 85 }; 86 87 public: 88 // 89 enum Status { 90 Running, 91 Idle, 92 IcacheMissStall, 93 IcacheMissComplete, 94 DcacheMissStall, 95 SwitchedOut 96 }; 97 98 private: 99 Status _status; 100 101 public: 102 void post_interrupt(int int_num, int index); 103 104 void zero_fill_64(Addr addr) { 105 static int warned = 0; 106 if (!warned) { 107 warn ("WH64 is not implemented"); 108 warned = 1; 109 } 110 }; 111 112#ifdef FULL_SYSTEM 113 114 SimpleCPU(const std::string &_name, 115 System *_system, 116 Counter max_insts_any_thread, Counter max_insts_all_threads, 117 Counter max_loads_any_thread, Counter max_loads_all_threads, 118 AlphaItb *itb, AlphaDtb *dtb, FunctionalMemory *mem, 119 MemInterface *icache_interface, MemInterface *dcache_interface, 120 Tick freq); 121 122#else 123 124 SimpleCPU(const std::string &_name, Process *_process, 125 Counter max_insts_any_thread, 126 Counter max_insts_all_threads, 127 Counter max_loads_any_thread, 128 Counter max_loads_all_threads, 129 MemInterface *icache_interface, MemInterface *dcache_interface); 130 131#endif 132 133 virtual ~SimpleCPU(); 134 135 // execution context 136 ExecContext *xc; 137 138 void switchOut(); 139 void takeOverFrom(BaseCPU *oldCPU); 140 141#ifdef FULL_SYSTEM 142 Addr dbg_vtophys(Addr addr); 143 144 bool interval_stats; 145#endif 146 147 // L1 instruction cache 148 MemInterface *icacheInterface; 149 150 // L1 data cache 151 MemInterface *dcacheInterface; 152 153 // current instruction 154 MachInst inst; 155 156 // Refcounted pointer to the one memory request. 157 MemReqPtr memReq; 158 159 class CacheCompletionEvent : public Event 160 { 161 private: 162 SimpleCPU *cpu; 163 164 public: 165 CacheCompletionEvent(SimpleCPU *_cpu); 166 167 virtual void process(); 168 virtual const char *description(); 169 }; 170 171 CacheCompletionEvent cacheCompletionEvent; 172 173 Status status() const { return _status; } 174 175 virtual void execCtxStatusChg(int thread_num); 176 177 void setStatus(Status new_status) { 178 Status old_status = status(); 179 180 // We should never even get here if the CPU has been switched out. 181 assert(old_status != SwitchedOut); 182 183 _status = new_status; 184 185 switch (status()) { 186 case IcacheMissStall: 187 assert(old_status == Running); 188 lastIcacheStall = curTick; 189 if (tickEvent.scheduled()) 190 tickEvent.squash(); 191 break; 192 193 case IcacheMissComplete: 194 assert(old_status == IcacheMissStall); 195 if (tickEvent.squashed()) 196 tickEvent.reschedule(curTick + 1); 197 else if (!tickEvent.scheduled()) 198 tickEvent.schedule(curTick + 1); 199 break; 200 201 case DcacheMissStall: 202 assert(old_status == Running); 203 lastDcacheStall = curTick; 204 if (tickEvent.scheduled()) 205 tickEvent.squash(); 206 break; 207 208 case Idle: 209 assert(old_status == Running); 210 last_idle = curTick; 211 if (tickEvent.scheduled()) 212 tickEvent.squash(); 213 break; 214 215 case Running: 216 assert(old_status == Idle || 217 old_status == DcacheMissStall || 218 old_status == IcacheMissComplete); 219 if (old_status == Idle) 220 idleCycles += curTick - last_idle; 221 222 if (tickEvent.squashed()) 223 tickEvent.reschedule(curTick + 1); 224 else if (!tickEvent.scheduled()) 225 tickEvent.schedule(curTick + 1); 226 break; 227 228 default: 229 panic("can't get here"); 230 } 231 } 232 233 // statistics 234 void regStats(); 235 236 // number of simulated instructions 237 Counter numInst; 238 Statistics::Formula numInsts; 239 240 // number of simulated memory references 241 Statistics::Scalar<> numMemRefs; 242 243 // number of simulated loads 244 Counter numLoad; 245 246 // number of idle cycles 247 Statistics::Scalar<> idleCycles; 248 Statistics::Formula idleFraction; 249 Counter last_idle; 250 251 // number of cycles stalled for I-cache misses 252 Statistics::Scalar<> icacheStallCycles; 253 Counter lastIcacheStall; 254 255 // number of cycles stalled for D-cache misses 256 Statistics::Scalar<> dcacheStallCycles; 257 Counter lastDcacheStall; 258 259 void processCacheCompletion(); 260 261 virtual void serialize(std::ostream &os); 262 virtual void unserialize(Checkpoint *cp, const std::string §ion); 263 264 template <class T> 265 Fault read(Addr addr, T& data, unsigned flags); 266 267 template <class T> 268 Fault write(T data, Addr addr, unsigned flags, 269 uint64_t *res); 270 271 Fault prefetch(Addr addr, unsigned flags) 272 { 273 // need to do this... 274 return No_Fault; 275 } 276 277 void writeHint(Addr addr, int size) 278 { 279 // need to do this... 280 } 281}; 282 283#endif // __SIMPLE_CPU_HH__ 284