base.hh revision 1354 
1/*
2 * Copyright (c) 2002-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__
30#define __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__
31
32#include "base/statistics.hh"
33#include "cpu/base_cpu.hh"
34#include "cpu/exec_context.hh"
35#include "cpu/pc_event.hh"
36#include "cpu/static_inst.hh"
37#include "sim/eventq.hh"
38
39// forward declarations
40#ifdef FULL_SYSTEM
41class Processor;
42class AlphaITB;
43class AlphaDTB;
44class PhysicalMemory;
45
46class RemoteGDB;
47class GDBListener;
48
49#else
50
51class Process;
52
53#endif // FULL_SYSTEM
54
55class MemInterface;
56class Checkpoint;
57
58namespace Trace {
59    class InstRecord;
60}
61
62class SimpleCPU : public BaseCPU
63{
64  public:
65    // main simulation loop (one cycle)
66    void tick();
67
68  private:
69    struct TickEvent : public Event
70    {
71        SimpleCPU *cpu;
72        int multiplier;
73
74        TickEvent(SimpleCPU *c);
75        void process();
76        const char *description();
77    };
78
79    TickEvent tickEvent;
80
81    /// Schedule tick event, regardless of its current state.
82    void scheduleTickEvent(int delay)
83    {
84        if (tickEvent.squashed())
85            tickEvent.reschedule(curTick + delay);
86        else if (!tickEvent.scheduled())
87            tickEvent.schedule(curTick + delay);
88    }
89
90    /// Unschedule tick event, regardless of its current state.
91    void unscheduleTickEvent()
92    {
93        if (tickEvent.scheduled())
94            tickEvent.squash();
95    }
96
97  public:
98    void setTickMultiplier(int multiplier)
99    {
100        tickEvent.multiplier = multiplier;
101    }
102
103  private:
104    Trace::InstRecord *traceData;
105    template<typename T>
106    void trace_data(T data);
107  public:
108    //
109    enum Status {
110        Running,
111        Idle,
112        IcacheMissStall,
113        IcacheMissComplete,
114        DcacheMissStall,
115        SwitchedOut
116    };
117
118  private:
119    Status _status;
120
121  public:
122    void post_interrupt(int int_num, int index);
123
124    void zero_fill_64(Addr addr) {
125      static int warned = 0;
126      if (!warned) {
127        warn ("WH64 is not implemented");
128        warned = 1;
129      }
130    };
131
132#ifdef FULL_SYSTEM
133
134    SimpleCPU(const std::string &_name,
135              System *_system,
136              Counter max_insts_any_thread, Counter max_insts_all_threads,
137              Counter max_loads_any_thread, Counter max_loads_all_threads,
138              AlphaITB *itb, AlphaDTB *dtb, FunctionalMemory *mem,
139              MemInterface *icache_interface, MemInterface *dcache_interface,
140              bool _def_reg, Tick freq,
141              bool _function_trace, Tick _function_trace_start);
142
143#else
144
145    SimpleCPU(const std::string &_name, Process *_process,
146              Counter max_insts_any_thread,
147              Counter max_insts_all_threads,
148              Counter max_loads_any_thread,
149              Counter max_loads_all_threads,
150              MemInterface *icache_interface, MemInterface *dcache_interface,
151              bool _def_reg,
152              bool _function_trace, Tick _function_trace_start);
153
154#endif
155
156    virtual ~SimpleCPU();
157
158    // execution context
159    ExecContext *xc;
160
161    void switchOut();
162    void takeOverFrom(BaseCPU *oldCPU);
163
164#ifdef FULL_SYSTEM
165    Addr dbg_vtophys(Addr addr);
166
167    bool interval_stats;
168#endif
169
170    // L1 instruction cache
171    MemInterface *icacheInterface;
172
173    // L1 data cache
174    MemInterface *dcacheInterface;
175
176    // current instruction
177    MachInst inst;
178
179    // Refcounted pointer to the one memory request.
180    MemReqPtr memReq;
181
182    class CacheCompletionEvent : public Event
183    {
184      private:
185        SimpleCPU *cpu;
186
187      public:
188        CacheCompletionEvent(SimpleCPU *_cpu);
189
190        virtual void process();
191        virtual const char *description();
192    };
193
194    CacheCompletionEvent cacheCompletionEvent;
195
196    Status status() const { return _status; }
197
198    virtual void activateContext(int thread_num, int delay);
199    virtual void suspendContext(int thread_num);
200    virtual void deallocateContext(int thread_num);
201    virtual void haltContext(int thread_num);
202
203    // statistics
204    virtual void regStats();
205    virtual void resetStats();
206
207    // number of simulated instructions
208    Counter numInst;
209    Counter startNumInst;
210    Stats::Scalar<> numInsts;
211
212    virtual Counter totalInstructions() const
213    {
214        return numInst - startNumInst;
215    }
216
217    // number of simulated memory references
218    Stats::Scalar<> numMemRefs;
219
220    // number of simulated loads
221    Counter numLoad;
222    Counter startNumLoad;
223
224    // number of idle cycles
225    Stats::Average<> notIdleFraction;
226    Stats::Formula idleFraction;
227
228    // number of cycles stalled for I-cache misses
229    Stats::Scalar<> icacheStallCycles;
230    Counter lastIcacheStall;
231
232    // number of cycles stalled for D-cache misses
233    Stats::Scalar<> dcacheStallCycles;
234    Counter lastDcacheStall;
235
236    void processCacheCompletion();
237
238    virtual void serialize(std::ostream &os);
239    virtual void unserialize(Checkpoint *cp, const std::string &section);
240
241    template <class T>
242    Fault read(Addr addr, T &data, unsigned flags);
243
244    template <class T>
245    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
246
247    void prefetch(Addr addr, unsigned flags)
248    {
249        // need to do this...
250    }
251
252    void writeHint(Addr addr, int size, unsigned flags)
253    {
254        // need to do this...
255    }
256
257    Fault copySrcTranslate(Addr src);
258
259    Fault copy(Addr dest);
260
261    // The register accessor methods provide the index of the
262    // instruction's operand (e.g., 0 or 1), not the architectural
263    // register index, to simplify the implementation of register
264    // renaming.  We find the architectural register index by indexing
265    // into the instruction's own operand index table.  Note that a
266    // raw pointer to the StaticInst is provided instead of a
267    // ref-counted StaticInstPtr to redice overhead.  This is fine as
268    // long as these methods don't copy the pointer into any long-term
269    // storage (which is pretty hard to imagine they would have reason
270    // to do).
271
272    uint64_t readIntReg(StaticInst<TheISA> *si, int idx)
273    {
274        return xc->readIntReg(si->srcRegIdx(idx));
275    }
276
277    float readFloatRegSingle(StaticInst<TheISA> *si, int idx)
278    {
279        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
280        return xc->readFloatRegSingle(reg_idx);
281    }
282
283    double readFloatRegDouble(StaticInst<TheISA> *si, int idx)
284    {
285        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
286        return xc->readFloatRegDouble(reg_idx);
287    }
288
289    uint64_t readFloatRegInt(StaticInst<TheISA> *si, int idx)
290    {
291        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
292        return xc->readFloatRegInt(reg_idx);
293    }
294
295    void setIntReg(StaticInst<TheISA> *si, int idx, uint64_t val)
296    {
297        xc->setIntReg(si->destRegIdx(idx), val);
298    }
299
300    void setFloatRegSingle(StaticInst<TheISA> *si, int idx, float val)
301    {
302        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
303        xc->setFloatRegSingle(reg_idx, val);
304    }
305
306    void setFloatRegDouble(StaticInst<TheISA> *si, int idx, double val)
307    {
308        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
309        xc->setFloatRegDouble(reg_idx, val);
310    }
311
312    void setFloatRegInt(StaticInst<TheISA> *si, int idx, uint64_t val)
313    {
314        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
315        xc->setFloatRegInt(reg_idx, val);
316    }
317
318    uint64_t readPC() { return xc->readPC(); }
319    void setNextPC(uint64_t val) { xc->setNextPC(val); }
320
321    uint64_t readUniq() { return xc->readUniq(); }
322    void setUniq(uint64_t val) { xc->setUniq(val); }
323
324    uint64_t readFpcr() { return xc->readFpcr(); }
325    void setFpcr(uint64_t val) { xc->setFpcr(val); }
326
327#ifdef FULL_SYSTEM
328    uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
329    Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
330    Fault hwrei() { return xc->hwrei(); }
331    int readIntrFlag() { return xc->readIntrFlag(); }
332    void setIntrFlag(int val) { xc->setIntrFlag(val); }
333    bool inPalMode() { return xc->inPalMode(); }
334    void ev5_trap(Fault fault) { xc->ev5_trap(fault); }
335    bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
336#else
337    void syscall() { xc->syscall(); }
338#endif
339
340    bool misspeculating() { return xc->misspeculating(); }
341    ExecContext *xcBase() { return xc; }
342};
343
344#endif // __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__
345