base.hh revision 124 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __SIMPLE_CPU_HH__
30#define __SIMPLE_CPU_HH__
31
32#include "cpu/base_cpu.hh"
33#include "sim/eventq.hh"
34#include "base/loader/symtab.hh"
35#include "cpu/pc_event.hh"
36#include "base/statistics.hh"
37
38
39// forward declarations
40#ifdef FULL_SYSTEM
41class Processor;
42class Kernel;
43class AlphaItb;
44class AlphaDtb;
45class PhysicalMemory;
46
47class RemoteGDB;
48class GDBListener;
49#endif // FULL_SYSTEM
50
51class MemInterface;
52class IniFile;
53
54namespace Trace {
55    class InstRecord;
56}
57
58class SimpleCPU : public BaseCPU
59{
60  public:
61    // main simulation loop (one cycle)
62    void tick();
63
64  private:
65    class TickEvent : public Event
66    {
67      private:
68        SimpleCPU *cpu;
69
70      public:
71        TickEvent(SimpleCPU *c)
72            : Event(&mainEventQueue, 100), cpu(c) { }
73        void process() { cpu->tick(); }
74        virtual const char *description() { return "tick event"; }
75    };
76
77    TickEvent tickEvent;
78
79  private:
80    Trace::InstRecord *traceData;
81    template<typename T>
82    void trace_data(T data) {
83      if (traceData) {
84        traceData->setData(data);
85      }
86    };
87
88  public:
89    //
90    enum Status {
91        Running,
92        Idle,
93        IcacheMissStall,
94        IcacheMissComplete,
95        DcacheMissStall
96    };
97
98  private:
99    Status _status;
100
101  public:
102    void post_interrupt(int int_num, int index);
103
104    void zero_fill_64(Addr addr) {
105      static int warned = 0;
106      if (!warned) {
107        warn ("WH64 is not implemented");
108        warned = 1;
109      }
110    };
111
112#ifdef FULL_SYSTEM
113
114    SimpleCPU(const std::string &_name,
115              System *_system,
116              Counter max_insts_any_thread, Counter max_insts_all_threads,
117              Counter max_loads_any_thread, Counter max_loads_all_threads,
118              AlphaItb *itb, AlphaDtb *dtb, FunctionalMemory *mem,
119              MemInterface *icache_interface, MemInterface *dcache_interface,
120              int cpu_id, Tick freq);
121
122#else
123
124    SimpleCPU(const std::string &_name, Process *_process,
125              Counter max_insts_any_thread,
126              Counter max_insts_all_threads,
127              Counter max_loads_any_thread,
128              Counter max_loads_all_threads,
129              MemInterface *icache_interface, MemInterface *dcache_interface);
130
131#endif
132
133    virtual ~SimpleCPU();
134
135    // execution context
136    ExecContext *xc;
137
138#ifdef FULL_SYSTEM
139    Addr dbg_vtophys(Addr addr);
140
141    bool interval_stats;
142#endif
143
144    // L1 instruction cache
145    MemInterface *icacheInterface;
146
147    // L1 data cache
148    MemInterface *dcacheInterface;
149
150    // current instruction
151    MachInst inst;
152
153    // current fault status
154    Fault fault;
155
156    // Refcounted pointer to the one memory request.
157    MemReqPtr memReq;
158
159    class CacheCompletionEvent : public Event
160    {
161      private:
162        SimpleCPU *cpu;
163
164      public:
165        CacheCompletionEvent(SimpleCPU *_cpu);
166
167        virtual void process();
168        virtual const char *description();
169    };
170
171    CacheCompletionEvent cacheCompletionEvent;
172
173    Status status() const { return _status; }
174    virtual void execCtxStatusChg() {
175        if (xc) {
176            if (xc->status() == ExecContext::Active)
177                setStatus(Running);
178            else
179                setStatus(Idle);
180        }
181    }
182
183    void setStatus(Status new_status) {
184        Status old_status = status();
185        _status = new_status;
186
187        switch (status()) {
188          case IcacheMissStall:
189            assert(old_status == Running);
190            lastIcacheStall = curTick;
191            if (tickEvent.scheduled())
192                tickEvent.squash();
193            break;
194
195          case IcacheMissComplete:
196            assert(old_status == IcacheMissStall);
197            if (tickEvent.squashed())
198                tickEvent.reschedule(curTick + 1);
199            else if (!tickEvent.scheduled())
200                tickEvent.schedule(curTick + 1);
201            break;
202
203          case DcacheMissStall:
204            assert(old_status == Running);
205            lastDcacheStall = curTick;
206            if (tickEvent.scheduled())
207                tickEvent.squash();
208            break;
209
210          case Idle:
211            assert(old_status == Running);
212            last_idle = curTick;
213            if (tickEvent.scheduled())
214                tickEvent.squash();
215            break;
216
217          case Running:
218            assert(old_status == Idle ||
219                   old_status == DcacheMissStall ||
220                   old_status == IcacheMissComplete);
221            if (old_status == Idle)
222                idleCycles += curTick - last_idle;
223
224            if (tickEvent.squashed())
225                tickEvent.reschedule(curTick + 1);
226            else if (!tickEvent.scheduled())
227                tickEvent.schedule(curTick + 1);
228            break;
229
230          default:
231            panic("can't get here");
232        }
233    }
234
235    // statistics
236    void regStats();
237
238    // number of simulated instructions
239    Counter numInst;
240    Statistics::Formula numInsts;
241
242    // number of simulated memory references
243    Statistics::Scalar<> numMemRefs;
244
245    // number of simulated loads
246    Counter numLoad;
247
248    // number of idle cycles
249    Statistics::Scalar<> idleCycles;
250    Statistics::Formula idleFraction;
251    Counter last_idle;
252
253    // number of cycles stalled for I-cache misses
254    Statistics::Scalar<> icacheStallCycles;
255    Counter lastIcacheStall;
256
257    // number of cycles stalled for D-cache misses
258    Statistics::Scalar<> dcacheStallCycles;
259    Counter lastDcacheStall;
260
261    void processCacheCompletion();
262
263    virtual void serialize();
264    virtual void unserialize(IniFile &db, const std::string &category,
265                             ConfigNode *node);
266
267    template <class T>
268    Fault read(Addr addr, T& data, unsigned flags);
269
270    template <class T>
271    Fault write(T data, Addr addr, unsigned flags,
272                        uint64_t *res);
273
274    Fault prefetch(Addr addr, unsigned flags)
275    {
276        // need to do this...
277        return No_Fault;
278    }
279
280    void writeHint(Addr addr, int size)
281    {
282        // need to do this...
283    }
284};
285
286#endif // __SIMPLE_CPU_HH__
287