base.hh revision 8779
12SN/A/*
21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292665Ssaidi@eecs.umich.edu *          Dave Greene
302665Ssaidi@eecs.umich.edu *          Nathan Binkert
312SN/A */
322SN/A
332623SN/A#ifndef __CPU_SIMPLE_BASE_HH__
342623SN/A#define __CPU_SIMPLE_BASE_HH__
352SN/A
364182Sgblack@eecs.umich.edu#include "arch/predecoder.hh"
371354SN/A#include "base/statistics.hh"
386658Snate@binkert.org#include "config/the_isa.hh"
391717SN/A#include "cpu/base.hh"
408541Sgblack@eecs.umich.edu#include "cpu/decode.hh"
418229Snate@binkert.org#include "cpu/pc_event.hh"
422683Sktlim@umich.edu#include "cpu/simple_thread.hh"
431354SN/A#include "cpu/static_inst.hh"
442387SN/A#include "mem/packet.hh"
452387SN/A#include "mem/port.hh"
462387SN/A#include "mem/request.hh"
4756SN/A#include "sim/eventq.hh"
488779Sgblack@eecs.umich.edu#include "sim/full_system.hh"
495348Ssaidi@eecs.umich.edu#include "sim/system.hh"
502SN/A
512SN/A// forward declarations
528779Sgblack@eecs.umich.educlass Checkpoint;
538779Sgblack@eecs.umich.educlass MemObject;
548779Sgblack@eecs.umich.educlass Process;
552SN/Aclass Processor;
568779Sgblack@eecs.umich.educlass ThreadContext;
572SN/A
584182Sgblack@eecs.umich.edunamespace TheISA
594182Sgblack@eecs.umich.edu{
608779Sgblack@eecs.umich.edu    class DTB;
618779Sgblack@eecs.umich.edu    class ITB;
624182Sgblack@eecs.umich.edu    class Predecoder;
634182Sgblack@eecs.umich.edu}
642SN/A
652SN/Anamespace Trace {
662SN/A    class InstRecord;
672SN/A}
682SN/A
695529Snate@binkert.orgclass BaseSimpleCPUParams;
705529Snate@binkert.org
712420SN/A
722623SN/Aclass BaseSimpleCPU : public BaseCPU
732SN/A{
742107SN/A  protected:
752159SN/A    typedef TheISA::MiscReg MiscReg;
762455SN/A    typedef TheISA::FloatReg FloatReg;
772455SN/A    typedef TheISA::FloatRegBits FloatRegBits;
782386SN/A
792623SN/A  protected:
802SN/A    Trace::InstRecord *traceData;
811371SN/A
825348Ssaidi@eecs.umich.edu    inline void checkPcEventQueue() {
837720Sgblack@eecs.umich.edu        Addr oldpc, pc = thread->instAddr();
845348Ssaidi@eecs.umich.edu        do {
857720Sgblack@eecs.umich.edu            oldpc = pc;
865348Ssaidi@eecs.umich.edu            system->pcEventQueue.service(tc);
877720Sgblack@eecs.umich.edu            pc = thread->instAddr();
887720Sgblack@eecs.umich.edu        } while (oldpc != pc);
895348Ssaidi@eecs.umich.edu    }
905348Ssaidi@eecs.umich.edu
912SN/A  public:
925807Snate@binkert.org    void wakeup();
932SN/A
942SN/A    void zero_fill_64(Addr addr) {
952SN/A      static int warned = 0;
962SN/A      if (!warned) {
972SN/A        warn ("WH64 is not implemented");
982SN/A        warned = 1;
992SN/A      }
1002SN/A    };
1012SN/A
1021400SN/A  public:
1035529Snate@binkert.org    BaseSimpleCPU(BaseSimpleCPUParams *params);
1042623SN/A    virtual ~BaseSimpleCPU();
1052SN/A
1061400SN/A  public:
1072683Sktlim@umich.edu    /** SimpleThread object, provides all the architectural state. */
1082683Sktlim@umich.edu    SimpleThread *thread;
1092190SN/A
1102683Sktlim@umich.edu    /** ThreadContext object, provides an interface for external
1112683Sktlim@umich.edu     * objects to modify this thread's state.
1122683Sktlim@umich.edu     */
1132680Sktlim@umich.edu    ThreadContext *tc;
1145169Ssaidi@eecs.umich.edu  protected:
1155169Ssaidi@eecs.umich.edu
1165496Ssaidi@eecs.umich.edu    enum Status {
1175496Ssaidi@eecs.umich.edu        Idle,
1185496Ssaidi@eecs.umich.edu        Running,
1198276SAli.Saidi@ARM.com        Faulting,
1205894Sgblack@eecs.umich.edu        ITBWaitResponse,
1215496Ssaidi@eecs.umich.edu        IcacheRetry,
1225496Ssaidi@eecs.umich.edu        IcacheWaitResponse,
1235496Ssaidi@eecs.umich.edu        IcacheWaitSwitch,
1245894Sgblack@eecs.umich.edu        DTBWaitResponse,
1255496Ssaidi@eecs.umich.edu        DcacheRetry,
1265496Ssaidi@eecs.umich.edu        DcacheWaitResponse,
1275496Ssaidi@eecs.umich.edu        DcacheWaitSwitch,
1285496Ssaidi@eecs.umich.edu        SwitchedOut
1295496Ssaidi@eecs.umich.edu    };
1305496Ssaidi@eecs.umich.edu
1315496Ssaidi@eecs.umich.edu    Status _status;
1325496Ssaidi@eecs.umich.edu
1335169Ssaidi@eecs.umich.edu  public:
1342SN/A
1352SN/A    Addr dbg_vtophys(Addr addr);
1362SN/A
1372SN/A    bool interval_stats;
1382SN/A
1392SN/A    // current instruction
1404181Sgblack@eecs.umich.edu    TheISA::MachInst inst;
1414181Sgblack@eecs.umich.edu
1424182Sgblack@eecs.umich.edu    // The predecoder
1434182Sgblack@eecs.umich.edu    TheISA::Predecoder predecoder;
1442SN/A
1452107SN/A    StaticInstPtr curStaticInst;
1463276Sgblack@eecs.umich.edu    StaticInstPtr curMacroStaticInst;
1471469SN/A
1484377Sgblack@eecs.umich.edu    //This is the offset from the current pc that fetch should be performed at
1494377Sgblack@eecs.umich.edu    Addr fetchOffset;
1504377Sgblack@eecs.umich.edu    //This flag says to stay at the current pc. This is useful for
1514377Sgblack@eecs.umich.edu    //instructions which go beyond MachInst boundaries.
1524377Sgblack@eecs.umich.edu    bool stayAtPC;
1534377Sgblack@eecs.umich.edu
1542623SN/A    void checkForInterrupts();
1555894Sgblack@eecs.umich.edu    void setupFetchRequest(Request *req);
1562623SN/A    void preExecute();
1572623SN/A    void postExecute();
1582623SN/A    void advancePC(Fault fault);
159180SN/A
160393SN/A    virtual void deallocateContext(int thread_num);
161393SN/A    virtual void haltContext(int thread_num);
1622SN/A
1632SN/A    // statistics
164334SN/A    virtual void regStats();
165334SN/A    virtual void resetStats();
1662SN/A
1672SN/A    // number of simulated instructions
1682SN/A    Counter numInst;
169334SN/A    Counter startNumInst;
1705999Snate@binkert.org    Stats::Scalar numInsts;
171707SN/A
1724998Sgblack@eecs.umich.edu    void countInst()
1734998Sgblack@eecs.umich.edu    {
1744998Sgblack@eecs.umich.edu        numInst++;
1754998Sgblack@eecs.umich.edu        numInsts++;
1767897Shestness@cs.utexas.edu        system->totalNumInsts++;
1774998Sgblack@eecs.umich.edu        thread->funcExeInst++;
1784998Sgblack@eecs.umich.edu    }
1794998Sgblack@eecs.umich.edu
180707SN/A    virtual Counter totalInstructions() const
181707SN/A    {
182707SN/A        return numInst - startNumInst;
183707SN/A    }
1842SN/A
1857897Shestness@cs.utexas.edu    //number of integer alu accesses
1867897Shestness@cs.utexas.edu    Stats::Scalar numIntAluAccesses;
1877897Shestness@cs.utexas.edu
1887897Shestness@cs.utexas.edu    //number of float alu accesses
1897897Shestness@cs.utexas.edu    Stats::Scalar numFpAluAccesses;
1907897Shestness@cs.utexas.edu
1917897Shestness@cs.utexas.edu    //number of function calls/returns
1927897Shestness@cs.utexas.edu    Stats::Scalar numCallsReturns;
1937897Shestness@cs.utexas.edu
1947897Shestness@cs.utexas.edu    //conditional control instructions;
1957897Shestness@cs.utexas.edu    Stats::Scalar numCondCtrlInsts;
1967897Shestness@cs.utexas.edu
1977897Shestness@cs.utexas.edu    //number of int instructions
1987897Shestness@cs.utexas.edu    Stats::Scalar numIntInsts;
1997897Shestness@cs.utexas.edu
2007897Shestness@cs.utexas.edu    //number of float instructions
2017897Shestness@cs.utexas.edu    Stats::Scalar numFpInsts;
2027897Shestness@cs.utexas.edu
2037897Shestness@cs.utexas.edu    //number of integer register file accesses
2047897Shestness@cs.utexas.edu    Stats::Scalar numIntRegReads;
2057897Shestness@cs.utexas.edu    Stats::Scalar numIntRegWrites;
2067897Shestness@cs.utexas.edu
2077897Shestness@cs.utexas.edu    //number of float register file accesses
2087897Shestness@cs.utexas.edu    Stats::Scalar numFpRegReads;
2097897Shestness@cs.utexas.edu    Stats::Scalar numFpRegWrites;
2107897Shestness@cs.utexas.edu
2112SN/A    // number of simulated memory references
2125999Snate@binkert.org    Stats::Scalar numMemRefs;
2137897Shestness@cs.utexas.edu    Stats::Scalar numLoadInsts;
2147897Shestness@cs.utexas.edu    Stats::Scalar numStoreInsts;
2157897Shestness@cs.utexas.edu
2167897Shestness@cs.utexas.edu    // number of idle cycles
2177897Shestness@cs.utexas.edu    Stats::Formula numIdleCycles;
2187897Shestness@cs.utexas.edu
2197897Shestness@cs.utexas.edu    // number of busy cycles
2207897Shestness@cs.utexas.edu    Stats::Formula numBusyCycles;
2212SN/A
222124SN/A    // number of simulated loads
223124SN/A    Counter numLoad;
224334SN/A    Counter startNumLoad;
225124SN/A
2262SN/A    // number of idle cycles
2275999Snate@binkert.org    Stats::Average notIdleFraction;
228729SN/A    Stats::Formula idleFraction;
2292SN/A
2302390SN/A    // number of cycles stalled for I-cache responses
2315999Snate@binkert.org    Stats::Scalar icacheStallCycles;
2322SN/A    Counter lastIcacheStall;
2332SN/A
2342390SN/A    // number of cycles stalled for I-cache retries
2355999Snate@binkert.org    Stats::Scalar icacheRetryCycles;
2362390SN/A    Counter lastIcacheRetry;
2372390SN/A
2382390SN/A    // number of cycles stalled for D-cache responses
2395999Snate@binkert.org    Stats::Scalar dcacheStallCycles;
2402SN/A    Counter lastDcacheStall;
2412SN/A
2422390SN/A    // number of cycles stalled for D-cache retries
2435999Snate@binkert.org    Stats::Scalar dcacheRetryCycles;
2442390SN/A    Counter lastDcacheRetry;
2452390SN/A
246217SN/A    virtual void serialize(std::ostream &os);
247237SN/A    virtual void unserialize(Checkpoint *cp, const std::string &section);
2482SN/A
2491371SN/A    // These functions are only used in CPU models that split
2501371SN/A    // effective address computation from the actual memory access.
2512623SN/A    void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
2525543Ssaidi@eecs.umich.edu    Addr getEA()        { panic("BaseSimpleCPU::getEA() not implemented\n");
2533918Ssaidi@eecs.umich.edu        M5_DUMMY_RETURN}
2541371SN/A
255726SN/A    // The register accessor methods provide the index of the
256726SN/A    // instruction's operand (e.g., 0 or 1), not the architectural
257726SN/A    // register index, to simplify the implementation of register
258726SN/A    // renaming.  We find the architectural register index by indexing
259726SN/A    // into the instruction's own operand index table.  Note that a
260726SN/A    // raw pointer to the StaticInst is provided instead of a
261726SN/A    // ref-counted StaticInstPtr to redice overhead.  This is fine as
262726SN/A    // long as these methods don't copy the pointer into any long-term
263726SN/A    // storage (which is pretty hard to imagine they would have reason
264726SN/A    // to do).
265705SN/A
2663735Sstever@eecs.umich.edu    uint64_t readIntRegOperand(const StaticInst *si, int idx)
267726SN/A    {
2687897Shestness@cs.utexas.edu        numIntRegReads++;
2692683Sktlim@umich.edu        return thread->readIntReg(si->srcRegIdx(idx));
270726SN/A    }
271705SN/A
2723735Sstever@eecs.umich.edu    FloatReg readFloatRegOperand(const StaticInst *si, int idx)
273726SN/A    {
2747897Shestness@cs.utexas.edu        numFpRegReads++;
275726SN/A        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
2762683Sktlim@umich.edu        return thread->readFloatReg(reg_idx);
277726SN/A    }
278705SN/A
2793735Sstever@eecs.umich.edu    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
2802455SN/A    {
2817897Shestness@cs.utexas.edu        numFpRegReads++;
2822455SN/A        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
2832683Sktlim@umich.edu        return thread->readFloatRegBits(reg_idx);
284726SN/A    }
285705SN/A
2863735Sstever@eecs.umich.edu    void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
287726SN/A    {
2887897Shestness@cs.utexas.edu        numIntRegWrites++;
2892683Sktlim@umich.edu        thread->setIntReg(si->destRegIdx(idx), val);
290726SN/A    }
291705SN/A
2923735Sstever@eecs.umich.edu    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
293726SN/A    {
2947897Shestness@cs.utexas.edu        numFpRegWrites++;
295726SN/A        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
2962683Sktlim@umich.edu        thread->setFloatReg(reg_idx, val);
297726SN/A    }
298726SN/A
2993735Sstever@eecs.umich.edu    void setFloatRegOperandBits(const StaticInst *si, int idx,
3003735Sstever@eecs.umich.edu                                FloatRegBits val)
3012455SN/A    {
3027897Shestness@cs.utexas.edu        numFpRegWrites++;
3032455SN/A        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
3042683Sktlim@umich.edu        thread->setFloatRegBits(reg_idx, val);
305726SN/A    }
306705SN/A
3077597Sminkyu.jeong@arm.com    bool readPredicate() { return thread->readPredicate(); }
3087597Sminkyu.jeong@arm.com    void setPredicate(bool val)
3097600Sminkyu.jeong@arm.com    {
3107600Sminkyu.jeong@arm.com        thread->setPredicate(val);
3117600Sminkyu.jeong@arm.com        if (traceData) {
3127600Sminkyu.jeong@arm.com            traceData->setPredicate(val);
3137600Sminkyu.jeong@arm.com        }
3147600Sminkyu.jeong@arm.com    }
3157720Sgblack@eecs.umich.edu    TheISA::PCState pcState() { return thread->pcState(); }
3167720Sgblack@eecs.umich.edu    void pcState(const TheISA::PCState &val) { thread->pcState(val); }
3177720Sgblack@eecs.umich.edu    Addr instAddr() { return thread->instAddr(); }
3187720Sgblack@eecs.umich.edu    Addr nextInstAddr() { return thread->nextInstAddr(); }
3197720Sgblack@eecs.umich.edu    MicroPC microPC() { return thread->microPC(); }
320705SN/A
3214172Ssaidi@eecs.umich.edu    MiscReg readMiscRegNoEffect(int misc_reg)
3224172Ssaidi@eecs.umich.edu    {
3234172Ssaidi@eecs.umich.edu        return thread->readMiscRegNoEffect(misc_reg);
3244172Ssaidi@eecs.umich.edu    }
3254172Ssaidi@eecs.umich.edu
3262159SN/A    MiscReg readMiscReg(int misc_reg)
3272159SN/A    {
3287897Shestness@cs.utexas.edu        numIntRegReads++;
3292683Sktlim@umich.edu        return thread->readMiscReg(misc_reg);
3302159SN/A    }
331705SN/A
3323468Sgblack@eecs.umich.edu    void setMiscReg(int misc_reg, const MiscReg &val)
3332159SN/A    {
3347897Shestness@cs.utexas.edu        numIntRegWrites++;
3352683Sktlim@umich.edu        return thread->setMiscReg(misc_reg, val);
3362159SN/A    }
3372159SN/A
3384185Ssaidi@eecs.umich.edu    MiscReg readMiscRegOperand(const StaticInst *si, int idx)
3393792Sgblack@eecs.umich.edu    {
3407897Shestness@cs.utexas.edu        numIntRegReads++;
3413792Sgblack@eecs.umich.edu        int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
3423792Sgblack@eecs.umich.edu        return thread->readMiscReg(reg_idx);
3433792Sgblack@eecs.umich.edu    }
3443792Sgblack@eecs.umich.edu
3454185Ssaidi@eecs.umich.edu    void setMiscRegOperand(
3463792Sgblack@eecs.umich.edu            const StaticInst *si, int idx, const MiscReg &val)
3473792Sgblack@eecs.umich.edu    {
3487897Shestness@cs.utexas.edu        numIntRegWrites++;
3493792Sgblack@eecs.umich.edu        int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
3504172Ssaidi@eecs.umich.edu        return thread->setMiscReg(reg_idx, val);
3513792Sgblack@eecs.umich.edu    }
3523792Sgblack@eecs.umich.edu
3535358Sgblack@eecs.umich.edu    void demapPage(Addr vaddr, uint64_t asn)
3545358Sgblack@eecs.umich.edu    {
3555358Sgblack@eecs.umich.edu        thread->demapPage(vaddr, asn);
3565358Sgblack@eecs.umich.edu    }
3575358Sgblack@eecs.umich.edu
3585358Sgblack@eecs.umich.edu    void demapInstPage(Addr vaddr, uint64_t asn)
3595358Sgblack@eecs.umich.edu    {
3605358Sgblack@eecs.umich.edu        thread->demapInstPage(vaddr, asn);
3615358Sgblack@eecs.umich.edu    }
3625358Sgblack@eecs.umich.edu
3635358Sgblack@eecs.umich.edu    void demapDataPage(Addr vaddr, uint64_t asn)
3645358Sgblack@eecs.umich.edu    {
3655358Sgblack@eecs.umich.edu        thread->demapDataPage(vaddr, asn);
3665358Sgblack@eecs.umich.edu    }
3675358Sgblack@eecs.umich.edu
3684027Sstever@eecs.umich.edu    unsigned readStCondFailures() {
3694027Sstever@eecs.umich.edu        return thread->readStCondFailures();
3704027Sstever@eecs.umich.edu    }
3714027Sstever@eecs.umich.edu
3724027Sstever@eecs.umich.edu    void setStCondFailures(unsigned sc_failures) {
3734027Sstever@eecs.umich.edu        thread->setStCondFailures(sc_failures);
3744027Sstever@eecs.umich.edu    }
3754027Sstever@eecs.umich.edu
3766221Snate@binkert.org     MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
3774661Sksewell@umich.edu     {
3784661Sksewell@umich.edu        panic("Simple CPU models do not support multithreaded "
3794661Sksewell@umich.edu              "register access.\n");
3804661Sksewell@umich.edu     }
3814661Sksewell@umich.edu
3826221Snate@binkert.org     void setRegOtherThread(int regIdx, const MiscReg &val,
3836221Snate@binkert.org                            ThreadID tid = InvalidThreadID)
3844661Sksewell@umich.edu     {
3854661Sksewell@umich.edu        panic("Simple CPU models do not support multithreaded "
3864661Sksewell@umich.edu              "register access.\n");
3874661Sksewell@umich.edu     }
3884661Sksewell@umich.edu
3895250Sksewell@umich.edu    //Fault CacheOp(uint8_t Op, Addr EA);
3905222Sksewell@umich.edu
3915702Ssaidi@eecs.umich.edu    Fault hwrei() { return thread->hwrei(); }
3925702Ssaidi@eecs.umich.edu    bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
3938557Sgblack@eecs.umich.edu
3948557Sgblack@eecs.umich.edu    void
3958557Sgblack@eecs.umich.edu    syscall(int64_t callnum)
3968557Sgblack@eecs.umich.edu    {
3978779Sgblack@eecs.umich.edu        if (FullSystem)
3988779Sgblack@eecs.umich.edu            panic("Syscall emulation isn't available in FS mode.\n");
3998779Sgblack@eecs.umich.edu        else
4008779Sgblack@eecs.umich.edu            thread->syscall(callnum);
4018557Sgblack@eecs.umich.edu    }
402705SN/A
4032683Sktlim@umich.edu    bool misspeculating() { return thread->misspeculating(); }
4042680Sktlim@umich.edu    ThreadContext *tcBase() { return tc; }
4052SN/A};
4062SN/A
4072623SN/A#endif // __CPU_SIMPLE_BASE_HH__
408