base.hh revision 8541
12SN/A/*
21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292665Ssaidi@eecs.umich.edu *          Dave Greene
302665Ssaidi@eecs.umich.edu *          Nathan Binkert
312SN/A */
322SN/A
332623SN/A#ifndef __CPU_SIMPLE_BASE_HH__
342623SN/A#define __CPU_SIMPLE_BASE_HH__
352SN/A
364182Sgblack@eecs.umich.edu#include "arch/predecoder.hh"
371354SN/A#include "base/statistics.hh"
381858SN/A#include "config/full_system.hh"
396658Snate@binkert.org#include "config/the_isa.hh"
401717SN/A#include "cpu/base.hh"
418541Sgblack@eecs.umich.edu#include "cpu/decode.hh"
428229Snate@binkert.org#include "cpu/pc_event.hh"
432683Sktlim@umich.edu#include "cpu/simple_thread.hh"
441354SN/A#include "cpu/static_inst.hh"
452387SN/A#include "mem/packet.hh"
462387SN/A#include "mem/port.hh"
472387SN/A#include "mem/request.hh"
4856SN/A#include "sim/eventq.hh"
495348Ssaidi@eecs.umich.edu#include "sim/system.hh"
502SN/A
512SN/A// forward declarations
521858SN/A#if FULL_SYSTEM
532SN/Aclass Processor;
543453Sgblack@eecs.umich.edunamespace TheISA
553453Sgblack@eecs.umich.edu{
563453Sgblack@eecs.umich.edu    class ITB;
573453Sgblack@eecs.umich.edu    class DTB;
583453Sgblack@eecs.umich.edu}
592462SN/Aclass MemObject;
602SN/A
61715SN/A#else
62715SN/A
63715SN/Aclass Process;
64715SN/A
652SN/A#endif // FULL_SYSTEM
662SN/A
674182Sgblack@eecs.umich.edunamespace TheISA
684182Sgblack@eecs.umich.edu{
694182Sgblack@eecs.umich.edu    class Predecoder;
704182Sgblack@eecs.umich.edu}
712680Sktlim@umich.educlass ThreadContext;
72237SN/Aclass Checkpoint;
732SN/A
742SN/Anamespace Trace {
752SN/A    class InstRecord;
762SN/A}
772SN/A
785529Snate@binkert.orgclass BaseSimpleCPUParams;
795529Snate@binkert.org
802420SN/A
812623SN/Aclass BaseSimpleCPU : public BaseCPU
822SN/A{
832107SN/A  protected:
842159SN/A    typedef TheISA::MiscReg MiscReg;
852455SN/A    typedef TheISA::FloatReg FloatReg;
862455SN/A    typedef TheISA::FloatRegBits FloatRegBits;
872386SN/A
882623SN/A  protected:
892SN/A    Trace::InstRecord *traceData;
901371SN/A
915348Ssaidi@eecs.umich.edu    inline void checkPcEventQueue() {
927720Sgblack@eecs.umich.edu        Addr oldpc, pc = thread->instAddr();
935348Ssaidi@eecs.umich.edu        do {
947720Sgblack@eecs.umich.edu            oldpc = pc;
955348Ssaidi@eecs.umich.edu            system->pcEventQueue.service(tc);
967720Sgblack@eecs.umich.edu            pc = thread->instAddr();
977720Sgblack@eecs.umich.edu        } while (oldpc != pc);
985348Ssaidi@eecs.umich.edu    }
995348Ssaidi@eecs.umich.edu
1002SN/A  public:
1015807Snate@binkert.org    void wakeup();
1022SN/A
1032SN/A    void zero_fill_64(Addr addr) {
1042SN/A      static int warned = 0;
1052SN/A      if (!warned) {
1062SN/A        warn ("WH64 is not implemented");
1072SN/A        warned = 1;
1082SN/A      }
1092SN/A    };
1102SN/A
1111400SN/A  public:
1125529Snate@binkert.org    BaseSimpleCPU(BaseSimpleCPUParams *params);
1132623SN/A    virtual ~BaseSimpleCPU();
1142SN/A
1151400SN/A  public:
1162683Sktlim@umich.edu    /** SimpleThread object, provides all the architectural state. */
1172683Sktlim@umich.edu    SimpleThread *thread;
1182190SN/A
1192683Sktlim@umich.edu    /** ThreadContext object, provides an interface for external
1202683Sktlim@umich.edu     * objects to modify this thread's state.
1212683Sktlim@umich.edu     */
1222680Sktlim@umich.edu    ThreadContext *tc;
1235169Ssaidi@eecs.umich.edu  protected:
1245169Ssaidi@eecs.umich.edu
1255496Ssaidi@eecs.umich.edu    enum Status {
1265496Ssaidi@eecs.umich.edu        Idle,
1275496Ssaidi@eecs.umich.edu        Running,
1288276SAli.Saidi@ARM.com        Faulting,
1295894Sgblack@eecs.umich.edu        ITBWaitResponse,
1305496Ssaidi@eecs.umich.edu        IcacheRetry,
1315496Ssaidi@eecs.umich.edu        IcacheWaitResponse,
1325496Ssaidi@eecs.umich.edu        IcacheWaitSwitch,
1335894Sgblack@eecs.umich.edu        DTBWaitResponse,
1345496Ssaidi@eecs.umich.edu        DcacheRetry,
1355496Ssaidi@eecs.umich.edu        DcacheWaitResponse,
1365496Ssaidi@eecs.umich.edu        DcacheWaitSwitch,
1375496Ssaidi@eecs.umich.edu        SwitchedOut
1385496Ssaidi@eecs.umich.edu    };
1395496Ssaidi@eecs.umich.edu
1405496Ssaidi@eecs.umich.edu    Status _status;
1415496Ssaidi@eecs.umich.edu
1425169Ssaidi@eecs.umich.edu  public:
1432SN/A
1441858SN/A#if FULL_SYSTEM
1452SN/A    Addr dbg_vtophys(Addr addr);
1462SN/A
1472SN/A    bool interval_stats;
1482SN/A#endif
1492SN/A
1502SN/A    // current instruction
1514181Sgblack@eecs.umich.edu    TheISA::MachInst inst;
1524181Sgblack@eecs.umich.edu
1534182Sgblack@eecs.umich.edu    // The predecoder
1544182Sgblack@eecs.umich.edu    TheISA::Predecoder predecoder;
1552SN/A
1562107SN/A    StaticInstPtr curStaticInst;
1573276Sgblack@eecs.umich.edu    StaticInstPtr curMacroStaticInst;
1581469SN/A
1594377Sgblack@eecs.umich.edu    //This is the offset from the current pc that fetch should be performed at
1604377Sgblack@eecs.umich.edu    Addr fetchOffset;
1614377Sgblack@eecs.umich.edu    //This flag says to stay at the current pc. This is useful for
1624377Sgblack@eecs.umich.edu    //instructions which go beyond MachInst boundaries.
1634377Sgblack@eecs.umich.edu    bool stayAtPC;
1644377Sgblack@eecs.umich.edu
1652623SN/A    void checkForInterrupts();
1665894Sgblack@eecs.umich.edu    void setupFetchRequest(Request *req);
1672623SN/A    void preExecute();
1682623SN/A    void postExecute();
1692623SN/A    void advancePC(Fault fault);
170180SN/A
171393SN/A    virtual void deallocateContext(int thread_num);
172393SN/A    virtual void haltContext(int thread_num);
1732SN/A
1742SN/A    // statistics
175334SN/A    virtual void regStats();
176334SN/A    virtual void resetStats();
1772SN/A
1782SN/A    // number of simulated instructions
1792SN/A    Counter numInst;
180334SN/A    Counter startNumInst;
1815999Snate@binkert.org    Stats::Scalar numInsts;
182707SN/A
1834998Sgblack@eecs.umich.edu    void countInst()
1844998Sgblack@eecs.umich.edu    {
1854998Sgblack@eecs.umich.edu        numInst++;
1864998Sgblack@eecs.umich.edu        numInsts++;
1877897Shestness@cs.utexas.edu        system->totalNumInsts++;
1884998Sgblack@eecs.umich.edu        thread->funcExeInst++;
1894998Sgblack@eecs.umich.edu    }
1904998Sgblack@eecs.umich.edu
191707SN/A    virtual Counter totalInstructions() const
192707SN/A    {
193707SN/A        return numInst - startNumInst;
194707SN/A    }
1952SN/A
1967897Shestness@cs.utexas.edu    //number of integer alu accesses
1977897Shestness@cs.utexas.edu    Stats::Scalar numIntAluAccesses;
1987897Shestness@cs.utexas.edu
1997897Shestness@cs.utexas.edu    //number of float alu accesses
2007897Shestness@cs.utexas.edu    Stats::Scalar numFpAluAccesses;
2017897Shestness@cs.utexas.edu
2027897Shestness@cs.utexas.edu    //number of function calls/returns
2037897Shestness@cs.utexas.edu    Stats::Scalar numCallsReturns;
2047897Shestness@cs.utexas.edu
2057897Shestness@cs.utexas.edu    //conditional control instructions;
2067897Shestness@cs.utexas.edu    Stats::Scalar numCondCtrlInsts;
2077897Shestness@cs.utexas.edu
2087897Shestness@cs.utexas.edu    //number of int instructions
2097897Shestness@cs.utexas.edu    Stats::Scalar numIntInsts;
2107897Shestness@cs.utexas.edu
2117897Shestness@cs.utexas.edu    //number of float instructions
2127897Shestness@cs.utexas.edu    Stats::Scalar numFpInsts;
2137897Shestness@cs.utexas.edu
2147897Shestness@cs.utexas.edu    //number of integer register file accesses
2157897Shestness@cs.utexas.edu    Stats::Scalar numIntRegReads;
2167897Shestness@cs.utexas.edu    Stats::Scalar numIntRegWrites;
2177897Shestness@cs.utexas.edu
2187897Shestness@cs.utexas.edu    //number of float register file accesses
2197897Shestness@cs.utexas.edu    Stats::Scalar numFpRegReads;
2207897Shestness@cs.utexas.edu    Stats::Scalar numFpRegWrites;
2217897Shestness@cs.utexas.edu
2222SN/A    // number of simulated memory references
2235999Snate@binkert.org    Stats::Scalar numMemRefs;
2247897Shestness@cs.utexas.edu    Stats::Scalar numLoadInsts;
2257897Shestness@cs.utexas.edu    Stats::Scalar numStoreInsts;
2267897Shestness@cs.utexas.edu
2277897Shestness@cs.utexas.edu    // number of idle cycles
2287897Shestness@cs.utexas.edu    Stats::Formula numIdleCycles;
2297897Shestness@cs.utexas.edu
2307897Shestness@cs.utexas.edu    // number of busy cycles
2317897Shestness@cs.utexas.edu    Stats::Formula numBusyCycles;
2322SN/A
233124SN/A    // number of simulated loads
234124SN/A    Counter numLoad;
235334SN/A    Counter startNumLoad;
236124SN/A
2372SN/A    // number of idle cycles
2385999Snate@binkert.org    Stats::Average notIdleFraction;
239729SN/A    Stats::Formula idleFraction;
2402SN/A
2412390SN/A    // number of cycles stalled for I-cache responses
2425999Snate@binkert.org    Stats::Scalar icacheStallCycles;
2432SN/A    Counter lastIcacheStall;
2442SN/A
2452390SN/A    // number of cycles stalled for I-cache retries
2465999Snate@binkert.org    Stats::Scalar icacheRetryCycles;
2472390SN/A    Counter lastIcacheRetry;
2482390SN/A
2492390SN/A    // number of cycles stalled for D-cache responses
2505999Snate@binkert.org    Stats::Scalar dcacheStallCycles;
2512SN/A    Counter lastDcacheStall;
2522SN/A
2532390SN/A    // number of cycles stalled for D-cache retries
2545999Snate@binkert.org    Stats::Scalar dcacheRetryCycles;
2552390SN/A    Counter lastDcacheRetry;
2562390SN/A
257217SN/A    virtual void serialize(std::ostream &os);
258237SN/A    virtual void unserialize(Checkpoint *cp, const std::string &section);
2592SN/A
2601371SN/A    // These functions are only used in CPU models that split
2611371SN/A    // effective address computation from the actual memory access.
2622623SN/A    void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
2635543Ssaidi@eecs.umich.edu    Addr getEA()        { panic("BaseSimpleCPU::getEA() not implemented\n");
2643918Ssaidi@eecs.umich.edu        M5_DUMMY_RETURN}
2651371SN/A
266726SN/A    // The register accessor methods provide the index of the
267726SN/A    // instruction's operand (e.g., 0 or 1), not the architectural
268726SN/A    // register index, to simplify the implementation of register
269726SN/A    // renaming.  We find the architectural register index by indexing
270726SN/A    // into the instruction's own operand index table.  Note that a
271726SN/A    // raw pointer to the StaticInst is provided instead of a
272726SN/A    // ref-counted StaticInstPtr to redice overhead.  This is fine as
273726SN/A    // long as these methods don't copy the pointer into any long-term
274726SN/A    // storage (which is pretty hard to imagine they would have reason
275726SN/A    // to do).
276705SN/A
2773735Sstever@eecs.umich.edu    uint64_t readIntRegOperand(const StaticInst *si, int idx)
278726SN/A    {
2797897Shestness@cs.utexas.edu        numIntRegReads++;
2802683Sktlim@umich.edu        return thread->readIntReg(si->srcRegIdx(idx));
281726SN/A    }
282705SN/A
2833735Sstever@eecs.umich.edu    FloatReg readFloatRegOperand(const StaticInst *si, int idx)
284726SN/A    {
2857897Shestness@cs.utexas.edu        numFpRegReads++;
286726SN/A        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
2872683Sktlim@umich.edu        return thread->readFloatReg(reg_idx);
288726SN/A    }
289705SN/A
2903735Sstever@eecs.umich.edu    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
2912455SN/A    {
2927897Shestness@cs.utexas.edu        numFpRegReads++;
2932455SN/A        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
2942683Sktlim@umich.edu        return thread->readFloatRegBits(reg_idx);
295726SN/A    }
296705SN/A
2973735Sstever@eecs.umich.edu    void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
298726SN/A    {
2997897Shestness@cs.utexas.edu        numIntRegWrites++;
3002683Sktlim@umich.edu        thread->setIntReg(si->destRegIdx(idx), val);
301726SN/A    }
302705SN/A
3033735Sstever@eecs.umich.edu    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
304726SN/A    {
3057897Shestness@cs.utexas.edu        numFpRegWrites++;
306726SN/A        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
3072683Sktlim@umich.edu        thread->setFloatReg(reg_idx, val);
308726SN/A    }
309726SN/A
3103735Sstever@eecs.umich.edu    void setFloatRegOperandBits(const StaticInst *si, int idx,
3113735Sstever@eecs.umich.edu                                FloatRegBits val)
3122455SN/A    {
3137897Shestness@cs.utexas.edu        numFpRegWrites++;
3142455SN/A        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
3152683Sktlim@umich.edu        thread->setFloatRegBits(reg_idx, val);
316726SN/A    }
317705SN/A
3187597Sminkyu.jeong@arm.com    bool readPredicate() { return thread->readPredicate(); }
3197597Sminkyu.jeong@arm.com    void setPredicate(bool val)
3207600Sminkyu.jeong@arm.com    {
3217600Sminkyu.jeong@arm.com        thread->setPredicate(val);
3227600Sminkyu.jeong@arm.com        if (traceData) {
3237600Sminkyu.jeong@arm.com            traceData->setPredicate(val);
3247600Sminkyu.jeong@arm.com        }
3257600Sminkyu.jeong@arm.com    }
3267720Sgblack@eecs.umich.edu    TheISA::PCState pcState() { return thread->pcState(); }
3277720Sgblack@eecs.umich.edu    void pcState(const TheISA::PCState &val) { thread->pcState(val); }
3287720Sgblack@eecs.umich.edu    Addr instAddr() { return thread->instAddr(); }
3297720Sgblack@eecs.umich.edu    Addr nextInstAddr() { return thread->nextInstAddr(); }
3307720Sgblack@eecs.umich.edu    MicroPC microPC() { return thread->microPC(); }
331705SN/A
3324172Ssaidi@eecs.umich.edu    MiscReg readMiscRegNoEffect(int misc_reg)
3334172Ssaidi@eecs.umich.edu    {
3344172Ssaidi@eecs.umich.edu        return thread->readMiscRegNoEffect(misc_reg);
3354172Ssaidi@eecs.umich.edu    }
3364172Ssaidi@eecs.umich.edu
3372159SN/A    MiscReg readMiscReg(int misc_reg)
3382159SN/A    {
3397897Shestness@cs.utexas.edu        numIntRegReads++;
3402683Sktlim@umich.edu        return thread->readMiscReg(misc_reg);
3412159SN/A    }
342705SN/A
3433468Sgblack@eecs.umich.edu    void setMiscReg(int misc_reg, const MiscReg &val)
3442159SN/A    {
3457897Shestness@cs.utexas.edu        numIntRegWrites++;
3462683Sktlim@umich.edu        return thread->setMiscReg(misc_reg, val);
3472159SN/A    }
3482159SN/A
3494185Ssaidi@eecs.umich.edu    MiscReg readMiscRegOperand(const StaticInst *si, int idx)
3503792Sgblack@eecs.umich.edu    {
3517897Shestness@cs.utexas.edu        numIntRegReads++;
3523792Sgblack@eecs.umich.edu        int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
3533792Sgblack@eecs.umich.edu        return thread->readMiscReg(reg_idx);
3543792Sgblack@eecs.umich.edu    }
3553792Sgblack@eecs.umich.edu
3564185Ssaidi@eecs.umich.edu    void setMiscRegOperand(
3573792Sgblack@eecs.umich.edu            const StaticInst *si, int idx, const MiscReg &val)
3583792Sgblack@eecs.umich.edu    {
3597897Shestness@cs.utexas.edu        numIntRegWrites++;
3603792Sgblack@eecs.umich.edu        int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
3614172Ssaidi@eecs.umich.edu        return thread->setMiscReg(reg_idx, val);
3623792Sgblack@eecs.umich.edu    }
3633792Sgblack@eecs.umich.edu
3645358Sgblack@eecs.umich.edu    void demapPage(Addr vaddr, uint64_t asn)
3655358Sgblack@eecs.umich.edu    {
3665358Sgblack@eecs.umich.edu        thread->demapPage(vaddr, asn);
3675358Sgblack@eecs.umich.edu    }
3685358Sgblack@eecs.umich.edu
3695358Sgblack@eecs.umich.edu    void demapInstPage(Addr vaddr, uint64_t asn)
3705358Sgblack@eecs.umich.edu    {
3715358Sgblack@eecs.umich.edu        thread->demapInstPage(vaddr, asn);
3725358Sgblack@eecs.umich.edu    }
3735358Sgblack@eecs.umich.edu
3745358Sgblack@eecs.umich.edu    void demapDataPage(Addr vaddr, uint64_t asn)
3755358Sgblack@eecs.umich.edu    {
3765358Sgblack@eecs.umich.edu        thread->demapDataPage(vaddr, asn);
3775358Sgblack@eecs.umich.edu    }
3785358Sgblack@eecs.umich.edu
3794027Sstever@eecs.umich.edu    unsigned readStCondFailures() {
3804027Sstever@eecs.umich.edu        return thread->readStCondFailures();
3814027Sstever@eecs.umich.edu    }
3824027Sstever@eecs.umich.edu
3834027Sstever@eecs.umich.edu    void setStCondFailures(unsigned sc_failures) {
3844027Sstever@eecs.umich.edu        thread->setStCondFailures(sc_failures);
3854027Sstever@eecs.umich.edu    }
3864027Sstever@eecs.umich.edu
3876221Snate@binkert.org     MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
3884661Sksewell@umich.edu     {
3894661Sksewell@umich.edu        panic("Simple CPU models do not support multithreaded "
3904661Sksewell@umich.edu              "register access.\n");
3914661Sksewell@umich.edu     }
3924661Sksewell@umich.edu
3936221Snate@binkert.org     void setRegOtherThread(int regIdx, const MiscReg &val,
3946221Snate@binkert.org                            ThreadID tid = InvalidThreadID)
3954661Sksewell@umich.edu     {
3964661Sksewell@umich.edu        panic("Simple CPU models do not support multithreaded "
3974661Sksewell@umich.edu              "register access.\n");
3984661Sksewell@umich.edu     }
3994661Sksewell@umich.edu
4005250Sksewell@umich.edu    //Fault CacheOp(uint8_t Op, Addr EA);
4015222Sksewell@umich.edu
4021858SN/A#if FULL_SYSTEM
4035702Ssaidi@eecs.umich.edu    Fault hwrei() { return thread->hwrei(); }
4045702Ssaidi@eecs.umich.edu    bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
405705SN/A#else
4062683Sktlim@umich.edu    void syscall(int64_t callnum) { thread->syscall(callnum); }
407705SN/A#endif
408705SN/A
4092683Sktlim@umich.edu    bool misspeculating() { return thread->misspeculating(); }
4102680Sktlim@umich.edu    ThreadContext *tcBase() { return tc; }
4112SN/A};
4122SN/A
4132623SN/A#endif // __CPU_SIMPLE_BASE_HH__
414