base.hh revision 56 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __SIMPLE_CPU_HH__
30#define __SIMPLE_CPU_HH__
31
32#include "cpu/base_cpu.hh"
33#include "sim/eventq.hh"
34#include "base/loader/symtab.hh"
35#include "cpu/pc_event.hh"
36#include "base/statistics.hh"
37
38
39// forward declarations
40#ifdef FULL_SYSTEM
41class Processor;
42class Kernel;
43class AlphaItb;
44class AlphaDtb;
45class PhysicalMemory;
46
47class RemoteGDB;
48class GDBListener;
49#endif // FULL_SYSTEM
50
51class MemInterface;
52class IniFile;
53
54namespace Trace {
55    class InstRecord;
56}
57
58class SimpleCPU : public BaseCPU
59{
60  public:
61    // main simulation loop (one cycle)
62    void tick();
63
64  private:
65    class TickEvent : public Event
66    {
67      private:
68        SimpleCPU *cpu;
69
70      public:
71        TickEvent(SimpleCPU *c)
72            : Event(&mainEventQueue, 100), cpu(c) { }
73        void process() { cpu->tick(); }
74        virtual const char *description() { return "tick event"; }
75    };
76
77    TickEvent tickEvent;
78
79  private:
80    Trace::InstRecord *traceData;
81    template<typename T>
82    void trace_data(T data) {
83      if (traceData) {
84        traceData->setData(data);
85      }
86    };
87
88  public:
89    //
90    enum Status {
91        Running,
92        Idle,
93        IcacheMissStall,
94        IcacheMissComplete,
95        DcacheMissStall
96    };
97
98  private:
99    Status _status;
100
101  public:
102    void post_interrupt(int int_num, int index);
103
104    void zero_fill_64(Addr addr) {
105      static int warned = 0;
106      if (!warned) {
107        warn ("WH64 is not implemented");
108        warned = 1;
109      }
110    };
111
112#ifdef FULL_SYSTEM
113
114    SimpleCPU(const std::string &_name,
115              System *_system,
116              Counter max_insts_any_thread, Counter max_insts_all_threads,
117              AlphaItb *itb, AlphaDtb *dtb, FunctionalMemory *mem,
118              MemInterface *icache_interface, MemInterface *dcache_interface,
119              int cpu_id, Tick freq);
120
121#else
122
123    SimpleCPU(const std::string &_name, Process *_process,
124              Counter max_insts_any_thread,
125              Counter max_insts_all_threads,
126              MemInterface *icache_interface, MemInterface *dcache_interface);
127
128#endif
129
130    virtual ~SimpleCPU();
131
132    // execution context
133    ExecContext *xc;
134
135#ifdef FULL_SYSTEM
136    Addr dbg_vtophys(Addr addr);
137
138    bool interval_stats;
139#endif
140
141    // L1 instruction cache
142    MemInterface *icacheInterface;
143
144    // L1 data cache
145    MemInterface *dcacheInterface;
146
147    // current instruction
148    MachInst inst;
149
150    // current fault status
151    Fault fault;
152
153    // Refcounted pointer to the one memory request.
154    MemReqPtr memReq;
155
156    class CacheCompletionEvent : public Event
157    {
158      private:
159        SimpleCPU *cpu;
160
161      public:
162        CacheCompletionEvent(SimpleCPU *_cpu);
163
164        virtual void process();
165        virtual const char *description();
166    };
167
168    CacheCompletionEvent cacheCompletionEvent;
169
170    Status status() const { return _status; }
171    virtual void execCtxStatusChg() {
172        if (xc) {
173            if (xc->status() == ExecContext::Active)
174                setStatus(Running);
175            else
176                setStatus(Idle);
177        }
178    }
179
180    void setStatus(Status new_status) {
181        Status old_status = status();
182        _status = new_status;
183
184        switch (status()) {
185          case IcacheMissStall:
186            assert(old_status == Running);
187            lastIcacheStall = curTick;
188            if (tickEvent.scheduled())
189                tickEvent.squash();
190            break;
191
192          case IcacheMissComplete:
193            assert(old_status == IcacheMissStall);
194            if (tickEvent.squashed())
195                tickEvent.reschedule(curTick + 1);
196            else if (!tickEvent.scheduled())
197                tickEvent.schedule(curTick + 1);
198            break;
199
200          case DcacheMissStall:
201            assert(old_status == Running);
202            lastDcacheStall = curTick;
203            if (tickEvent.scheduled())
204                tickEvent.squash();
205            break;
206
207          case Idle:
208            assert(old_status == Running);
209            last_idle = curTick;
210            if (tickEvent.scheduled())
211                tickEvent.squash();
212            break;
213
214          case Running:
215            assert(old_status == Idle ||
216                   old_status == DcacheMissStall ||
217                   old_status == IcacheMissComplete);
218            if (old_status == Idle)
219                idleCycles += curTick - last_idle;
220
221            if (tickEvent.squashed())
222                tickEvent.reschedule(curTick + 1);
223            else if (!tickEvent.scheduled())
224                tickEvent.schedule(curTick + 1);
225            break;
226
227          default:
228            panic("can't get here");
229        }
230    }
231
232    // statistics
233    void regStats();
234
235    // number of simulated instructions
236    Counter numInst;
237    Statistics::Formula numInsts;
238
239    // number of simulated memory references
240    Statistics::Scalar<> numMemRefs;
241
242    // number of idle cycles
243    Statistics::Scalar<> idleCycles;
244    Statistics::Formula idleFraction;
245    Counter last_idle;
246
247    // number of cycles stalled for I-cache misses
248    Statistics::Scalar<> icacheStallCycles;
249    Counter lastIcacheStall;
250
251    // number of cycles stalled for D-cache misses
252    Statistics::Scalar<> dcacheStallCycles;
253    Counter lastDcacheStall;
254
255    void processCacheCompletion();
256
257    virtual void serialize();
258    virtual void unserialize(IniFile &db, const std::string &category,
259                             ConfigNode *node);
260
261    template <class T>
262    Fault read(Addr addr, T& data, unsigned flags);
263
264    template <class T>
265    Fault write(T data, Addr addr, unsigned flags,
266                        uint64_t *res);
267
268    Fault prefetch(Addr addr, unsigned flags)
269    {
270        // need to do this...
271        return No_Fault;
272    }
273
274    void writeHint(Addr addr, int size)
275    {
276        // need to do this...
277    }
278};
279
280#endif // __SIMPLE_CPU_HH__
281