base.hh revision 4997
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Dave Greene 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312SN/A */ 322SN/A 332623SN/A#ifndef __CPU_SIMPLE_BASE_HH__ 342623SN/A#define __CPU_SIMPLE_BASE_HH__ 352SN/A 364182Sgblack@eecs.umich.edu#include "arch/predecoder.hh" 371354SN/A#include "base/statistics.hh" 381858SN/A#include "config/full_system.hh" 391717SN/A#include "cpu/base.hh" 402683Sktlim@umich.edu#include "cpu/simple_thread.hh" 411354SN/A#include "cpu/pc_event.hh" 421354SN/A#include "cpu/static_inst.hh" 432387SN/A#include "mem/packet.hh" 442387SN/A#include "mem/port.hh" 452387SN/A#include "mem/request.hh" 4656SN/A#include "sim/eventq.hh" 472SN/A 482SN/A// forward declarations 491858SN/A#if FULL_SYSTEM 502SN/Aclass Processor; 513453Sgblack@eecs.umich.edunamespace TheISA 523453Sgblack@eecs.umich.edu{ 533453Sgblack@eecs.umich.edu class ITB; 543453Sgblack@eecs.umich.edu class DTB; 553453Sgblack@eecs.umich.edu} 562462SN/Aclass MemObject; 572SN/A 58715SN/A#else 59715SN/A 60715SN/Aclass Process; 61715SN/A 622SN/A#endif // FULL_SYSTEM 632SN/A 643960Sgblack@eecs.umich.educlass RemoteGDB; 653960Sgblack@eecs.umich.educlass GDBListener; 663960Sgblack@eecs.umich.edu 674182Sgblack@eecs.umich.edunamespace TheISA 684182Sgblack@eecs.umich.edu{ 694182Sgblack@eecs.umich.edu class Predecoder; 704182Sgblack@eecs.umich.edu} 712680Sktlim@umich.educlass ThreadContext; 72237SN/Aclass Checkpoint; 732SN/A 742SN/Anamespace Trace { 752SN/A class InstRecord; 762SN/A} 772SN/A 782420SN/A 792623SN/Aclass BaseSimpleCPU : public BaseCPU 802SN/A{ 812107SN/A protected: 822159SN/A typedef TheISA::MiscReg MiscReg; 832455SN/A typedef TheISA::FloatReg FloatReg; 842455SN/A typedef TheISA::FloatRegBits FloatRegBits; 852386SN/A 862623SN/A protected: 872SN/A Trace::InstRecord *traceData; 881371SN/A 892SN/A public: 902SN/A void post_interrupt(int int_num, int index); 912SN/A 922SN/A void zero_fill_64(Addr addr) { 932SN/A static int warned = 0; 942SN/A if (!warned) { 952SN/A warn ("WH64 is not implemented"); 962SN/A warned = 1; 972SN/A } 982SN/A }; 992SN/A 1001400SN/A public: 1011400SN/A struct Params : public BaseCPU::Params 1021400SN/A { 1033453Sgblack@eecs.umich.edu TheISA::ITB *itb; 1043453Sgblack@eecs.umich.edu TheISA::DTB *dtb; 1054997Sgblack@eecs.umich.edu#if !FULL_SYSTEM 1061400SN/A Process *process; 1072SN/A#endif 1081400SN/A }; 1092623SN/A BaseSimpleCPU(Params *params); 1102623SN/A virtual ~BaseSimpleCPU(); 1112SN/A 1121400SN/A public: 1132683Sktlim@umich.edu /** SimpleThread object, provides all the architectural state. */ 1142683Sktlim@umich.edu SimpleThread *thread; 1152190SN/A 1162683Sktlim@umich.edu /** ThreadContext object, provides an interface for external 1172683Sktlim@umich.edu * objects to modify this thread's state. 1182683Sktlim@umich.edu */ 1192680Sktlim@umich.edu ThreadContext *tc; 1202SN/A 1211858SN/A#if FULL_SYSTEM 1222SN/A Addr dbg_vtophys(Addr addr); 1232SN/A 1242SN/A bool interval_stats; 1252SN/A#endif 1262SN/A 1272SN/A // current instruction 1284181Sgblack@eecs.umich.edu TheISA::MachInst inst; 1294181Sgblack@eecs.umich.edu 1304182Sgblack@eecs.umich.edu // The predecoder 1314182Sgblack@eecs.umich.edu TheISA::Predecoder predecoder; 1322SN/A 1332107SN/A StaticInstPtr curStaticInst; 1343276Sgblack@eecs.umich.edu StaticInstPtr curMacroStaticInst; 1351469SN/A 1364377Sgblack@eecs.umich.edu //This is the offset from the current pc that fetch should be performed at 1374377Sgblack@eecs.umich.edu Addr fetchOffset; 1384377Sgblack@eecs.umich.edu //This flag says to stay at the current pc. This is useful for 1394377Sgblack@eecs.umich.edu //instructions which go beyond MachInst boundaries. 1404377Sgblack@eecs.umich.edu bool stayAtPC; 1414377Sgblack@eecs.umich.edu 1422623SN/A void checkForInterrupts(); 1432662Sstever@eecs.umich.edu Fault setupFetchRequest(Request *req); 1442623SN/A void preExecute(); 1452623SN/A void postExecute(); 1462623SN/A void advancePC(Fault fault); 147180SN/A 148393SN/A virtual void deallocateContext(int thread_num); 149393SN/A virtual void haltContext(int thread_num); 1502SN/A 1512SN/A // statistics 152334SN/A virtual void regStats(); 153334SN/A virtual void resetStats(); 1542SN/A 1552SN/A // number of simulated instructions 1562SN/A Counter numInst; 157334SN/A Counter startNumInst; 158729SN/A Stats::Scalar<> numInsts; 159707SN/A 160707SN/A virtual Counter totalInstructions() const 161707SN/A { 162707SN/A return numInst - startNumInst; 163707SN/A } 1642SN/A 1654564Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 1664564Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 1674564Sgblack@eecs.umich.edu 1682SN/A // number of simulated memory references 169729SN/A Stats::Scalar<> numMemRefs; 1702SN/A 171124SN/A // number of simulated loads 172124SN/A Counter numLoad; 173334SN/A Counter startNumLoad; 174124SN/A 1752SN/A // number of idle cycles 176729SN/A Stats::Average<> notIdleFraction; 177729SN/A Stats::Formula idleFraction; 1782SN/A 1792390SN/A // number of cycles stalled for I-cache responses 180729SN/A Stats::Scalar<> icacheStallCycles; 1812SN/A Counter lastIcacheStall; 1822SN/A 1832390SN/A // number of cycles stalled for I-cache retries 1842390SN/A Stats::Scalar<> icacheRetryCycles; 1852390SN/A Counter lastIcacheRetry; 1862390SN/A 1872390SN/A // number of cycles stalled for D-cache responses 188729SN/A Stats::Scalar<> dcacheStallCycles; 1892SN/A Counter lastDcacheStall; 1902SN/A 1912390SN/A // number of cycles stalled for D-cache retries 1922390SN/A Stats::Scalar<> dcacheRetryCycles; 1932390SN/A Counter lastDcacheRetry; 1942390SN/A 195217SN/A virtual void serialize(std::ostream &os); 196237SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1972SN/A 1981371SN/A // These functions are only used in CPU models that split 1991371SN/A // effective address computation from the actual memory access. 2002623SN/A void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 2013918Ssaidi@eecs.umich.edu Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); 2023918Ssaidi@eecs.umich.edu M5_DUMMY_RETURN} 2031371SN/A 204581SN/A void prefetch(Addr addr, unsigned flags) 2052SN/A { 2062SN/A // need to do this... 2072SN/A } 2082SN/A 209753SN/A void writeHint(Addr addr, int size, unsigned flags) 2102SN/A { 2112SN/A // need to do this... 2122SN/A } 213594SN/A 2144661Sksewell@umich.edu 215595SN/A Fault copySrcTranslate(Addr src); 216594SN/A 217595SN/A Fault copy(Addr dest); 218705SN/A 219726SN/A // The register accessor methods provide the index of the 220726SN/A // instruction's operand (e.g., 0 or 1), not the architectural 221726SN/A // register index, to simplify the implementation of register 222726SN/A // renaming. We find the architectural register index by indexing 223726SN/A // into the instruction's own operand index table. Note that a 224726SN/A // raw pointer to the StaticInst is provided instead of a 225726SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 226726SN/A // long as these methods don't copy the pointer into any long-term 227726SN/A // storage (which is pretty hard to imagine they would have reason 228726SN/A // to do). 229705SN/A 2303735Sstever@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx) 231726SN/A { 2322683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 233726SN/A } 234705SN/A 2353735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) 236726SN/A { 237726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2382683Sktlim@umich.edu return thread->readFloatReg(reg_idx, width); 239726SN/A } 240705SN/A 2413735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 242726SN/A { 243726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2442683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 245726SN/A } 246705SN/A 2473735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, 2483735Sstever@eecs.umich.edu int width) 249726SN/A { 250726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2512683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx, width); 2522455SN/A } 2532455SN/A 2543735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2552455SN/A { 2562455SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2572683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 258726SN/A } 259705SN/A 2603735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 261726SN/A { 2622683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 263726SN/A } 264705SN/A 2653735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 2663735Sstever@eecs.umich.edu int width) 267726SN/A { 268726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2692683Sktlim@umich.edu thread->setFloatReg(reg_idx, val, width); 270726SN/A } 271705SN/A 2723735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 273726SN/A { 274726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2752683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 276726SN/A } 277726SN/A 2783735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2793735Sstever@eecs.umich.edu FloatRegBits val, int width) 280726SN/A { 281726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2822683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val, width); 2832455SN/A } 2842455SN/A 2853735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2863735Sstever@eecs.umich.edu FloatRegBits val) 2872455SN/A { 2882455SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2892683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 290726SN/A } 291705SN/A 2922683Sktlim@umich.edu uint64_t readPC() { return thread->readPC(); } 2934950Sgblack@eecs.umich.edu uint64_t readMicroPC() { return thread->readMicroPC(); } 2942683Sktlim@umich.edu uint64_t readNextPC() { return thread->readNextPC(); } 2954950Sgblack@eecs.umich.edu uint64_t readNextMicroPC() { return thread->readNextMicroPC(); } 2962683Sktlim@umich.edu uint64_t readNextNPC() { return thread->readNextNPC(); } 2972447SN/A 2982683Sktlim@umich.edu void setPC(uint64_t val) { thread->setPC(val); } 2994950Sgblack@eecs.umich.edu void setMicroPC(uint64_t val) { thread->setMicroPC(val); } 3002683Sktlim@umich.edu void setNextPC(uint64_t val) { thread->setNextPC(val); } 3014950Sgblack@eecs.umich.edu void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); } 3022683Sktlim@umich.edu void setNextNPC(uint64_t val) { thread->setNextNPC(val); } 303705SN/A 3044172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 3054172Ssaidi@eecs.umich.edu { 3064172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 3074172Ssaidi@eecs.umich.edu } 3084172Ssaidi@eecs.umich.edu 3092159SN/A MiscReg readMiscReg(int misc_reg) 3102159SN/A { 3112683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 3122159SN/A } 313705SN/A 3144172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3152159SN/A { 3164172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 3172159SN/A } 3182159SN/A 3193468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 3202159SN/A { 3212683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3222159SN/A } 3232159SN/A 3244185Ssaidi@eecs.umich.edu MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) 3252159SN/A { 3264172Ssaidi@eecs.umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3274172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(reg_idx); 3282159SN/A } 329705SN/A 3304185Ssaidi@eecs.umich.edu MiscReg readMiscRegOperand(const StaticInst *si, int idx) 3313792Sgblack@eecs.umich.edu { 3323792Sgblack@eecs.umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3333792Sgblack@eecs.umich.edu return thread->readMiscReg(reg_idx); 3343792Sgblack@eecs.umich.edu } 3353792Sgblack@eecs.umich.edu 3364185Ssaidi@eecs.umich.edu void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val) 3373792Sgblack@eecs.umich.edu { 3383792Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3394172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(reg_idx, val); 3403792Sgblack@eecs.umich.edu } 3413792Sgblack@eecs.umich.edu 3424185Ssaidi@eecs.umich.edu void setMiscRegOperand( 3433792Sgblack@eecs.umich.edu const StaticInst *si, int idx, const MiscReg &val) 3443792Sgblack@eecs.umich.edu { 3453792Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3464172Ssaidi@eecs.umich.edu return thread->setMiscReg(reg_idx, val); 3473792Sgblack@eecs.umich.edu } 3483792Sgblack@eecs.umich.edu 3494027Sstever@eecs.umich.edu unsigned readStCondFailures() { 3504027Sstever@eecs.umich.edu return thread->readStCondFailures(); 3514027Sstever@eecs.umich.edu } 3524027Sstever@eecs.umich.edu 3534027Sstever@eecs.umich.edu void setStCondFailures(unsigned sc_failures) { 3544027Sstever@eecs.umich.edu thread->setStCondFailures(sc_failures); 3554027Sstever@eecs.umich.edu } 3564027Sstever@eecs.umich.edu 3574661Sksewell@umich.edu MiscReg readRegOtherThread(int regIdx, int tid = -1) 3584661Sksewell@umich.edu { 3594661Sksewell@umich.edu panic("Simple CPU models do not support multithreaded " 3604661Sksewell@umich.edu "register access.\n"); 3614661Sksewell@umich.edu } 3624661Sksewell@umich.edu 3634661Sksewell@umich.edu void setRegOtherThread(int regIdx, const MiscReg &val, int tid = -1) 3644661Sksewell@umich.edu { 3654661Sksewell@umich.edu panic("Simple CPU models do not support multithreaded " 3664661Sksewell@umich.edu "register access.\n"); 3674661Sksewell@umich.edu } 3684661Sksewell@umich.edu 3691858SN/A#if FULL_SYSTEM 3702683Sktlim@umich.edu Fault hwrei() { return thread->hwrei(); } 3712680Sktlim@umich.edu void ev5_trap(Fault fault) { fault->invoke(tc); } 3722683Sktlim@umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 373705SN/A#else 3742683Sktlim@umich.edu void syscall(int64_t callnum) { thread->syscall(callnum); } 375705SN/A#endif 376705SN/A 3772683Sktlim@umich.edu bool misspeculating() { return thread->misspeculating(); } 3782680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 3792SN/A}; 3802SN/A 3812623SN/A#endif // __CPU_SIMPLE_BASE_HH__ 382