base.hh revision 4564
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Dave Greene 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312SN/A */ 322SN/A 332623SN/A#ifndef __CPU_SIMPLE_BASE_HH__ 342623SN/A#define __CPU_SIMPLE_BASE_HH__ 352SN/A 364182Sgblack@eecs.umich.edu#include "arch/predecoder.hh" 371354SN/A#include "base/statistics.hh" 381858SN/A#include "config/full_system.hh" 391717SN/A#include "cpu/base.hh" 402683Sktlim@umich.edu#include "cpu/simple_thread.hh" 411354SN/A#include "cpu/pc_event.hh" 421354SN/A#include "cpu/static_inst.hh" 432387SN/A#include "mem/packet.hh" 442387SN/A#include "mem/port.hh" 452387SN/A#include "mem/request.hh" 4656SN/A#include "sim/eventq.hh" 472SN/A 482SN/A// forward declarations 491858SN/A#if FULL_SYSTEM 502SN/Aclass Processor; 513453Sgblack@eecs.umich.edunamespace TheISA 523453Sgblack@eecs.umich.edu{ 533453Sgblack@eecs.umich.edu class ITB; 543453Sgblack@eecs.umich.edu class DTB; 553453Sgblack@eecs.umich.edu} 562462SN/Aclass MemObject; 572SN/A 58715SN/A#else 59715SN/A 60715SN/Aclass Process; 61715SN/A 622SN/A#endif // FULL_SYSTEM 632SN/A 643960Sgblack@eecs.umich.educlass RemoteGDB; 653960Sgblack@eecs.umich.educlass GDBListener; 663960Sgblack@eecs.umich.edu 674182Sgblack@eecs.umich.edunamespace TheISA 684182Sgblack@eecs.umich.edu{ 694182Sgblack@eecs.umich.edu class Predecoder; 704182Sgblack@eecs.umich.edu} 712680Sktlim@umich.educlass ThreadContext; 72237SN/Aclass Checkpoint; 732SN/A 742SN/Anamespace Trace { 752SN/A class InstRecord; 762SN/A} 772SN/A 782420SN/A 792623SN/Aclass BaseSimpleCPU : public BaseCPU 802SN/A{ 812107SN/A protected: 822159SN/A typedef TheISA::MiscReg MiscReg; 832455SN/A typedef TheISA::FloatReg FloatReg; 842455SN/A typedef TheISA::FloatRegBits FloatRegBits; 852386SN/A 862623SN/A protected: 872SN/A Trace::InstRecord *traceData; 881371SN/A 892SN/A public: 902SN/A void post_interrupt(int int_num, int index); 912SN/A 922SN/A void zero_fill_64(Addr addr) { 932SN/A static int warned = 0; 942SN/A if (!warned) { 952SN/A warn ("WH64 is not implemented"); 962SN/A warned = 1; 972SN/A } 982SN/A }; 992SN/A 1001400SN/A public: 1011400SN/A struct Params : public BaseCPU::Params 1021400SN/A { 1031858SN/A#if FULL_SYSTEM 1043453Sgblack@eecs.umich.edu TheISA::ITB *itb; 1053453Sgblack@eecs.umich.edu TheISA::DTB *dtb; 1062SN/A#else 1071400SN/A Process *process; 1082SN/A#endif 1091400SN/A }; 1102623SN/A BaseSimpleCPU(Params *params); 1112623SN/A virtual ~BaseSimpleCPU(); 1122SN/A 1131400SN/A public: 1142683Sktlim@umich.edu /** SimpleThread object, provides all the architectural state. */ 1152683Sktlim@umich.edu SimpleThread *thread; 1162190SN/A 1172683Sktlim@umich.edu /** ThreadContext object, provides an interface for external 1182683Sktlim@umich.edu * objects to modify this thread's state. 1192683Sktlim@umich.edu */ 1202680Sktlim@umich.edu ThreadContext *tc; 1212SN/A 1221858SN/A#if FULL_SYSTEM 1232SN/A Addr dbg_vtophys(Addr addr); 1242SN/A 1252SN/A bool interval_stats; 1262SN/A#endif 1272SN/A 1282SN/A // current instruction 1294181Sgblack@eecs.umich.edu TheISA::MachInst inst; 1304181Sgblack@eecs.umich.edu 1314182Sgblack@eecs.umich.edu // The predecoder 1324182Sgblack@eecs.umich.edu TheISA::Predecoder predecoder; 1332SN/A 1342566SN/A // Static data storage 1354040Ssaidi@eecs.umich.edu TheISA::LargestRead dataReg; 1362566SN/A 1372107SN/A StaticInstPtr curStaticInst; 1383276Sgblack@eecs.umich.edu StaticInstPtr curMacroStaticInst; 1391469SN/A 1404377Sgblack@eecs.umich.edu //This is the offset from the current pc that fetch should be performed at 1414377Sgblack@eecs.umich.edu Addr fetchOffset; 1424377Sgblack@eecs.umich.edu //This flag says to stay at the current pc. This is useful for 1434377Sgblack@eecs.umich.edu //instructions which go beyond MachInst boundaries. 1444377Sgblack@eecs.umich.edu bool stayAtPC; 1454377Sgblack@eecs.umich.edu 1462623SN/A void checkForInterrupts(); 1472662Sstever@eecs.umich.edu Fault setupFetchRequest(Request *req); 1482623SN/A void preExecute(); 1492623SN/A void postExecute(); 1502623SN/A void advancePC(Fault fault); 151180SN/A 152393SN/A virtual void deallocateContext(int thread_num); 153393SN/A virtual void haltContext(int thread_num); 1542SN/A 1552SN/A // statistics 156334SN/A virtual void regStats(); 157334SN/A virtual void resetStats(); 1582SN/A 1592SN/A // number of simulated instructions 1602SN/A Counter numInst; 161334SN/A Counter startNumInst; 162729SN/A Stats::Scalar<> numInsts; 163707SN/A 164707SN/A virtual Counter totalInstructions() const 165707SN/A { 166707SN/A return numInst - startNumInst; 167707SN/A } 1682SN/A 1694564Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 1704564Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 1714564Sgblack@eecs.umich.edu 1722SN/A // number of simulated memory references 173729SN/A Stats::Scalar<> numMemRefs; 1742SN/A 175124SN/A // number of simulated loads 176124SN/A Counter numLoad; 177334SN/A Counter startNumLoad; 178124SN/A 1792SN/A // number of idle cycles 180729SN/A Stats::Average<> notIdleFraction; 181729SN/A Stats::Formula idleFraction; 1822SN/A 1832390SN/A // number of cycles stalled for I-cache responses 184729SN/A Stats::Scalar<> icacheStallCycles; 1852SN/A Counter lastIcacheStall; 1862SN/A 1872390SN/A // number of cycles stalled for I-cache retries 1882390SN/A Stats::Scalar<> icacheRetryCycles; 1892390SN/A Counter lastIcacheRetry; 1902390SN/A 1912390SN/A // number of cycles stalled for D-cache responses 192729SN/A Stats::Scalar<> dcacheStallCycles; 1932SN/A Counter lastDcacheStall; 1942SN/A 1952390SN/A // number of cycles stalled for D-cache retries 1962390SN/A Stats::Scalar<> dcacheRetryCycles; 1972390SN/A Counter lastDcacheRetry; 1982390SN/A 199217SN/A virtual void serialize(std::ostream &os); 200237SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 2012SN/A 2021371SN/A // These functions are only used in CPU models that split 2031371SN/A // effective address computation from the actual memory access. 2042623SN/A void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 2053918Ssaidi@eecs.umich.edu Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); 2063918Ssaidi@eecs.umich.edu M5_DUMMY_RETURN} 2071371SN/A 208581SN/A void prefetch(Addr addr, unsigned flags) 2092SN/A { 2102SN/A // need to do this... 2112SN/A } 2122SN/A 213753SN/A void writeHint(Addr addr, int size, unsigned flags) 2142SN/A { 2152SN/A // need to do this... 2162SN/A } 217594SN/A 218595SN/A Fault copySrcTranslate(Addr src); 219594SN/A 220595SN/A Fault copy(Addr dest); 221705SN/A 222726SN/A // The register accessor methods provide the index of the 223726SN/A // instruction's operand (e.g., 0 or 1), not the architectural 224726SN/A // register index, to simplify the implementation of register 225726SN/A // renaming. We find the architectural register index by indexing 226726SN/A // into the instruction's own operand index table. Note that a 227726SN/A // raw pointer to the StaticInst is provided instead of a 228726SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 229726SN/A // long as these methods don't copy the pointer into any long-term 230726SN/A // storage (which is pretty hard to imagine they would have reason 231726SN/A // to do). 232705SN/A 2333735Sstever@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx) 234726SN/A { 2352683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 236726SN/A } 237705SN/A 2383735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) 239726SN/A { 240726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2412683Sktlim@umich.edu return thread->readFloatReg(reg_idx, width); 242726SN/A } 243705SN/A 2443735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 245726SN/A { 246726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2472683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 248726SN/A } 249705SN/A 2503735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, 2513735Sstever@eecs.umich.edu int width) 252726SN/A { 253726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2542683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx, width); 2552455SN/A } 2562455SN/A 2573735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2582455SN/A { 2592455SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2602683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 261726SN/A } 262705SN/A 2633735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 264726SN/A { 2652683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 266726SN/A } 267705SN/A 2683735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 2693735Sstever@eecs.umich.edu int width) 270726SN/A { 271726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2722683Sktlim@umich.edu thread->setFloatReg(reg_idx, val, width); 273726SN/A } 274705SN/A 2753735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 276726SN/A { 277726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2782683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 279726SN/A } 280726SN/A 2813735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2823735Sstever@eecs.umich.edu FloatRegBits val, int width) 283726SN/A { 284726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2852683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val, width); 2862455SN/A } 2872455SN/A 2883735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2893735Sstever@eecs.umich.edu FloatRegBits val) 2902455SN/A { 2912455SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2922683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 293726SN/A } 294705SN/A 2952683Sktlim@umich.edu uint64_t readPC() { return thread->readPC(); } 2962683Sktlim@umich.edu uint64_t readNextPC() { return thread->readNextPC(); } 2972683Sktlim@umich.edu uint64_t readNextNPC() { return thread->readNextNPC(); } 2982447SN/A 2992683Sktlim@umich.edu void setPC(uint64_t val) { thread->setPC(val); } 3002683Sktlim@umich.edu void setNextPC(uint64_t val) { thread->setNextPC(val); } 3012683Sktlim@umich.edu void setNextNPC(uint64_t val) { thread->setNextNPC(val); } 302705SN/A 3034172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 3044172Ssaidi@eecs.umich.edu { 3054172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 3064172Ssaidi@eecs.umich.edu } 3074172Ssaidi@eecs.umich.edu 3082159SN/A MiscReg readMiscReg(int misc_reg) 3092159SN/A { 3102683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 3112159SN/A } 312705SN/A 3134172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3142159SN/A { 3154172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 3162159SN/A } 3172159SN/A 3183468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 3192159SN/A { 3202683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3212159SN/A } 3222159SN/A 3234185Ssaidi@eecs.umich.edu MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) 3242159SN/A { 3254172Ssaidi@eecs.umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3264172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(reg_idx); 3272159SN/A } 328705SN/A 3294185Ssaidi@eecs.umich.edu MiscReg readMiscRegOperand(const StaticInst *si, int idx) 3303792Sgblack@eecs.umich.edu { 3313792Sgblack@eecs.umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3323792Sgblack@eecs.umich.edu return thread->readMiscReg(reg_idx); 3333792Sgblack@eecs.umich.edu } 3343792Sgblack@eecs.umich.edu 3354185Ssaidi@eecs.umich.edu void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val) 3363792Sgblack@eecs.umich.edu { 3373792Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3384172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(reg_idx, val); 3393792Sgblack@eecs.umich.edu } 3403792Sgblack@eecs.umich.edu 3414185Ssaidi@eecs.umich.edu void setMiscRegOperand( 3423792Sgblack@eecs.umich.edu const StaticInst *si, int idx, const MiscReg &val) 3433792Sgblack@eecs.umich.edu { 3443792Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3454172Ssaidi@eecs.umich.edu return thread->setMiscReg(reg_idx, val); 3463792Sgblack@eecs.umich.edu } 3473792Sgblack@eecs.umich.edu 3484027Sstever@eecs.umich.edu unsigned readStCondFailures() { 3494027Sstever@eecs.umich.edu return thread->readStCondFailures(); 3504027Sstever@eecs.umich.edu } 3514027Sstever@eecs.umich.edu 3524027Sstever@eecs.umich.edu void setStCondFailures(unsigned sc_failures) { 3534027Sstever@eecs.umich.edu thread->setStCondFailures(sc_failures); 3544027Sstever@eecs.umich.edu } 3554027Sstever@eecs.umich.edu 3561858SN/A#if FULL_SYSTEM 3572683Sktlim@umich.edu Fault hwrei() { return thread->hwrei(); } 3582680Sktlim@umich.edu void ev5_trap(Fault fault) { fault->invoke(tc); } 3592683Sktlim@umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 360705SN/A#else 3612683Sktlim@umich.edu void syscall(int64_t callnum) { thread->syscall(callnum); } 362705SN/A#endif 363705SN/A 3642683Sktlim@umich.edu bool misspeculating() { return thread->misspeculating(); } 3652680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 3662SN/A}; 3672SN/A 3682623SN/A#endif // __CPU_SIMPLE_BASE_HH__ 369