base.hh revision 2665
12SN/A/*
21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292665Ssaidi@eecs.umich.edu *          Dave Greene
302665Ssaidi@eecs.umich.edu *          Nathan Binkert
312SN/A */
322SN/A
332623SN/A#ifndef __CPU_SIMPLE_BASE_HH__
342623SN/A#define __CPU_SIMPLE_BASE_HH__
352SN/A
361354SN/A#include "base/statistics.hh"
371858SN/A#include "config/full_system.hh"
381717SN/A#include "cpu/base.hh"
392190SN/A#include "cpu/cpu_exec_context.hh"
401354SN/A#include "cpu/pc_event.hh"
411717SN/A#include "cpu/sampler/sampler.hh"
421354SN/A#include "cpu/static_inst.hh"
432387SN/A#include "mem/packet.hh"
442387SN/A#include "mem/port.hh"
452387SN/A#include "mem/request.hh"
4656SN/A#include "sim/eventq.hh"
472SN/A
482SN/A// forward declarations
491858SN/A#if FULL_SYSTEM
502SN/Aclass Processor;
51676SN/Aclass AlphaITB;
52676SN/Aclass AlphaDTB;
532462SN/Aclass MemObject;
542SN/A
552SN/Aclass RemoteGDB;
562SN/Aclass GDBListener;
57715SN/A
58715SN/A#else
59715SN/A
60715SN/Aclass Process;
61715SN/A
622SN/A#endif // FULL_SYSTEM
632SN/A
642190SN/Aclass ExecContext;
65237SN/Aclass Checkpoint;
662SN/A
672SN/Anamespace Trace {
682SN/A    class InstRecord;
692SN/A}
702SN/A
712420SN/A
722623SN/Aclass BaseSimpleCPU : public BaseCPU
732SN/A{
742107SN/A  protected:
752107SN/A    typedef TheISA::MachInst MachInst;
762159SN/A    typedef TheISA::MiscReg MiscReg;
772455SN/A    typedef TheISA::FloatReg FloatReg;
782455SN/A    typedef TheISA::FloatRegBits FloatRegBits;
792386SN/A
802499SN/A    MemObject *mem;
812386SN/A
822623SN/A  protected:
832SN/A    Trace::InstRecord *traceData;
841371SN/A
852SN/A  public:
862SN/A    void post_interrupt(int int_num, int index);
872SN/A
882SN/A    void zero_fill_64(Addr addr) {
892SN/A      static int warned = 0;
902SN/A      if (!warned) {
912SN/A        warn ("WH64 is not implemented");
922SN/A        warned = 1;
932SN/A      }
942SN/A    };
952SN/A
961400SN/A  public:
971400SN/A    struct Params : public BaseCPU::Params
981400SN/A    {
992542SN/A        MemObject *mem;
1001858SN/A#if FULL_SYSTEM
1011400SN/A        AlphaITB *itb;
1021400SN/A        AlphaDTB *dtb;
1032SN/A#else
1041400SN/A        Process *process;
1052SN/A#endif
1061400SN/A    };
1072623SN/A    BaseSimpleCPU(Params *params);
1082623SN/A    virtual ~BaseSimpleCPU();
1092SN/A
1101400SN/A  public:
1112SN/A    // execution context
1122190SN/A    CPUExecContext *cpuXC;
1132190SN/A
1142190SN/A    ExecContext *xcProxy;
1152SN/A
1161858SN/A#if FULL_SYSTEM
1172SN/A    Addr dbg_vtophys(Addr addr);
1182SN/A
1192SN/A    bool interval_stats;
1202SN/A#endif
1212SN/A
1222SN/A    // current instruction
1232SN/A    MachInst inst;
1242SN/A
1252566SN/A    // Static data storage
1262566SN/A    TheISA::IntReg dataReg;
1272566SN/A
1281492SN/A    // Pointer to the sampler that is telling us to switchover.
1291492SN/A    // Used to signal the completion of the pipe drain and schedule
1301492SN/A    // the next switchover
1311752SN/A    Sampler *sampler;
1321492SN/A
1332107SN/A    StaticInstPtr curStaticInst;
1341469SN/A
1352623SN/A    void checkForInterrupts();
1362662Sstever@eecs.umich.edu    Fault setupFetchRequest(Request *req);
1372623SN/A    void preExecute();
1382623SN/A    void postExecute();
1392623SN/A    void advancePC(Fault fault);
140180SN/A
141393SN/A    virtual void deallocateContext(int thread_num);
142393SN/A    virtual void haltContext(int thread_num);
1432SN/A
1442SN/A    // statistics
145334SN/A    virtual void regStats();
146334SN/A    virtual void resetStats();
1472SN/A
1482SN/A    // number of simulated instructions
1492SN/A    Counter numInst;
150334SN/A    Counter startNumInst;
151729SN/A    Stats::Scalar<> numInsts;
152707SN/A
153707SN/A    virtual Counter totalInstructions() const
154707SN/A    {
155707SN/A        return numInst - startNumInst;
156707SN/A    }
1572SN/A
1582SN/A    // number of simulated memory references
159729SN/A    Stats::Scalar<> numMemRefs;
1602SN/A
161124SN/A    // number of simulated loads
162124SN/A    Counter numLoad;
163334SN/A    Counter startNumLoad;
164124SN/A
1652SN/A    // number of idle cycles
166729SN/A    Stats::Average<> notIdleFraction;
167729SN/A    Stats::Formula idleFraction;
1682SN/A
1692390SN/A    // number of cycles stalled for I-cache responses
170729SN/A    Stats::Scalar<> icacheStallCycles;
1712SN/A    Counter lastIcacheStall;
1722SN/A
1732390SN/A    // number of cycles stalled for I-cache retries
1742390SN/A    Stats::Scalar<> icacheRetryCycles;
1752390SN/A    Counter lastIcacheRetry;
1762390SN/A
1772390SN/A    // number of cycles stalled for D-cache responses
178729SN/A    Stats::Scalar<> dcacheStallCycles;
1792SN/A    Counter lastDcacheStall;
1802SN/A
1812390SN/A    // number of cycles stalled for D-cache retries
1822390SN/A    Stats::Scalar<> dcacheRetryCycles;
1832390SN/A    Counter lastDcacheRetry;
1842390SN/A
185217SN/A    virtual void serialize(std::ostream &os);
186237SN/A    virtual void unserialize(Checkpoint *cp, const std::string &section);
1872SN/A
1881371SN/A    // These functions are only used in CPU models that split
1891371SN/A    // effective address computation from the actual memory access.
1902623SN/A    void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
1912623SN/A    Addr getEA() 	{ panic("BaseSimpleCPU::getEA() not implemented\n"); }
1921371SN/A
193581SN/A    void prefetch(Addr addr, unsigned flags)
1942SN/A    {
1952SN/A        // need to do this...
1962SN/A    }
1972SN/A
198753SN/A    void writeHint(Addr addr, int size, unsigned flags)
1992SN/A    {
2002SN/A        // need to do this...
2012SN/A    }
202594SN/A
203595SN/A    Fault copySrcTranslate(Addr src);
204594SN/A
205595SN/A    Fault copy(Addr dest);
206705SN/A
207726SN/A    // The register accessor methods provide the index of the
208726SN/A    // instruction's operand (e.g., 0 or 1), not the architectural
209726SN/A    // register index, to simplify the implementation of register
210726SN/A    // renaming.  We find the architectural register index by indexing
211726SN/A    // into the instruction's own operand index table.  Note that a
212726SN/A    // raw pointer to the StaticInst is provided instead of a
213726SN/A    // ref-counted StaticInstPtr to redice overhead.  This is fine as
214726SN/A    // long as these methods don't copy the pointer into any long-term
215726SN/A    // storage (which is pretty hard to imagine they would have reason
216726SN/A    // to do).
217705SN/A
2182107SN/A    uint64_t readIntReg(const StaticInst *si, int idx)
219726SN/A    {
2202190SN/A        return cpuXC->readIntReg(si->srcRegIdx(idx));
221726SN/A    }
222705SN/A
2232455SN/A    FloatReg readFloatReg(const StaticInst *si, int idx, int width)
224726SN/A    {
225726SN/A        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
2262455SN/A        return cpuXC->readFloatReg(reg_idx, width);
227726SN/A    }
228705SN/A
2292455SN/A    FloatReg readFloatReg(const StaticInst *si, int idx)
230726SN/A    {
231726SN/A        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
2322455SN/A        return cpuXC->readFloatReg(reg_idx);
233726SN/A    }
234705SN/A
2352455SN/A    FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
236726SN/A    {
237726SN/A        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
2382455SN/A        return cpuXC->readFloatRegBits(reg_idx, width);
2392455SN/A    }
2402455SN/A
2412455SN/A    FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
2422455SN/A    {
2432455SN/A        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
2442455SN/A        return cpuXC->readFloatRegBits(reg_idx);
245726SN/A    }
246705SN/A
2472107SN/A    void setIntReg(const StaticInst *si, int idx, uint64_t val)
248726SN/A    {
2492190SN/A        cpuXC->setIntReg(si->destRegIdx(idx), val);
250726SN/A    }
251705SN/A
2522455SN/A    void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
253726SN/A    {
254726SN/A        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
2552455SN/A        cpuXC->setFloatReg(reg_idx, val, width);
256726SN/A    }
257705SN/A
2582455SN/A    void setFloatReg(const StaticInst *si, int idx, FloatReg val)
259726SN/A    {
260726SN/A        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
2612455SN/A        cpuXC->setFloatReg(reg_idx, val);
262726SN/A    }
263726SN/A
2642455SN/A    void setFloatRegBits(const StaticInst *si, int idx,
2652577SN/A                         FloatRegBits val, int width)
266726SN/A    {
267726SN/A        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
2682455SN/A        cpuXC->setFloatRegBits(reg_idx, val, width);
2692455SN/A    }
2702455SN/A
2712455SN/A    void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
2722455SN/A    {
2732455SN/A        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
2742455SN/A        cpuXC->setFloatRegBits(reg_idx, val);
275726SN/A    }
276705SN/A
2772190SN/A    uint64_t readPC() { return cpuXC->readPC(); }
2782447SN/A    uint64_t readNextPC() { return cpuXC->readNextPC(); }
2792447SN/A    uint64_t readNextNPC() { return cpuXC->readNextNPC(); }
2802447SN/A
2812447SN/A    void setPC(uint64_t val) { cpuXC->setPC(val); }
2822190SN/A    void setNextPC(uint64_t val) { cpuXC->setNextPC(val); }
2832447SN/A    void setNextNPC(uint64_t val) { cpuXC->setNextNPC(val); }
284705SN/A
2852159SN/A    MiscReg readMiscReg(int misc_reg)
2862159SN/A    {
2872190SN/A        return cpuXC->readMiscReg(misc_reg);
2882159SN/A    }
289705SN/A
2902159SN/A    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
2912159SN/A    {
2922190SN/A        return cpuXC->readMiscRegWithEffect(misc_reg, fault);
2932159SN/A    }
2942159SN/A
2952159SN/A    Fault setMiscReg(int misc_reg, const MiscReg &val)
2962159SN/A    {
2972190SN/A        return cpuXC->setMiscReg(misc_reg, val);
2982159SN/A    }
2992159SN/A
3002159SN/A    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
3012159SN/A    {
3022190SN/A        return cpuXC->setMiscRegWithEffect(misc_reg, val);
3032159SN/A    }
304705SN/A
3051858SN/A#if FULL_SYSTEM
3062190SN/A    Fault hwrei() { return cpuXC->hwrei(); }
3072190SN/A    int readIntrFlag() { return cpuXC->readIntrFlag(); }
3082190SN/A    void setIntrFlag(int val) { cpuXC->setIntrFlag(val); }
3092190SN/A    bool inPalMode() { return cpuXC->inPalMode(); }
3102234SN/A    void ev5_trap(Fault fault) { fault->invoke(xcProxy); }
3112190SN/A    bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); }
312705SN/A#else
3132561SN/A    void syscall(int64_t callnum) { cpuXC->syscall(callnum); }
314705SN/A#endif
315705SN/A
3162190SN/A    bool misspeculating() { return cpuXC->misspeculating(); }
3172190SN/A    ExecContext *xcBase() { return xcProxy; }
3182SN/A};
3192SN/A
3202623SN/A#endif // __CPU_SIMPLE_BASE_HH__
321