base.hh revision 10061
12SN/A/* 29448SAndreas.Sandberg@ARM.com * Copyright (c) 2011-2012 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 151762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Dave Greene 432665Ssaidi@eecs.umich.edu * Nathan Binkert 442SN/A */ 452SN/A 462623SN/A#ifndef __CPU_SIMPLE_BASE_HH__ 472623SN/A#define __CPU_SIMPLE_BASE_HH__ 482SN/A 491354SN/A#include "base/statistics.hh" 506658Snate@binkert.org#include "config/the_isa.hh" 511717SN/A#include "cpu/base.hh" 528887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 538229Snate@binkert.org#include "cpu/pc_event.hh" 542683Sktlim@umich.edu#include "cpu/simple_thread.hh" 551354SN/A#include "cpu/static_inst.hh" 562387SN/A#include "mem/packet.hh" 572387SN/A#include "mem/port.hh" 582387SN/A#include "mem/request.hh" 5956SN/A#include "sim/eventq.hh" 608779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 615348Ssaidi@eecs.umich.edu#include "sim/system.hh" 622SN/A 632SN/A// forward declarations 648779Sgblack@eecs.umich.educlass Checkpoint; 658779Sgblack@eecs.umich.educlass Process; 662SN/Aclass Processor; 678779Sgblack@eecs.umich.educlass ThreadContext; 682SN/A 694182Sgblack@eecs.umich.edunamespace TheISA 704182Sgblack@eecs.umich.edu{ 718779Sgblack@eecs.umich.edu class DTB; 728779Sgblack@eecs.umich.edu class ITB; 734182Sgblack@eecs.umich.edu} 742SN/A 752SN/Anamespace Trace { 762SN/A class InstRecord; 772SN/A} 782SN/A 798737Skoansin.tan@gmail.comstruct BaseSimpleCPUParams; 8010061Sandreas@sandberg.pp.seclass BPredUnit; 812420SN/A 822623SN/Aclass BaseSimpleCPU : public BaseCPU 832SN/A{ 842107SN/A protected: 852159SN/A typedef TheISA::MiscReg MiscReg; 862455SN/A typedef TheISA::FloatReg FloatReg; 872455SN/A typedef TheISA::FloatRegBits FloatRegBits; 889920Syasuko.eckert@amd.com typedef TheISA::CCReg CCReg; 892386SN/A 9010061Sandreas@sandberg.pp.se BPredUnit *branchPred; 9110061Sandreas@sandberg.pp.se 922623SN/A protected: 932SN/A Trace::InstRecord *traceData; 941371SN/A 955348Ssaidi@eecs.umich.edu inline void checkPcEventQueue() { 967720Sgblack@eecs.umich.edu Addr oldpc, pc = thread->instAddr(); 975348Ssaidi@eecs.umich.edu do { 987720Sgblack@eecs.umich.edu oldpc = pc; 995348Ssaidi@eecs.umich.edu system->pcEventQueue.service(tc); 1007720Sgblack@eecs.umich.edu pc = thread->instAddr(); 1017720Sgblack@eecs.umich.edu } while (oldpc != pc); 1025348Ssaidi@eecs.umich.edu } 1035348Ssaidi@eecs.umich.edu 1042SN/A public: 1055807Snate@binkert.org void wakeup(); 1062SN/A 1072SN/A void zero_fill_64(Addr addr) { 1082SN/A static int warned = 0; 1092SN/A if (!warned) { 1102SN/A warn ("WH64 is not implemented"); 1112SN/A warned = 1; 1122SN/A } 1132SN/A }; 1142SN/A 1151400SN/A public: 1165529Snate@binkert.org BaseSimpleCPU(BaseSimpleCPUParams *params); 1172623SN/A virtual ~BaseSimpleCPU(); 1182SN/A 1191400SN/A public: 1202683Sktlim@umich.edu /** SimpleThread object, provides all the architectural state. */ 1212683Sktlim@umich.edu SimpleThread *thread; 1222190SN/A 1232683Sktlim@umich.edu /** ThreadContext object, provides an interface for external 1242683Sktlim@umich.edu * objects to modify this thread's state. 1252683Sktlim@umich.edu */ 1262680Sktlim@umich.edu ThreadContext *tc; 1278733Sgeoffrey.blake@arm.com 1288733Sgeoffrey.blake@arm.com CheckerCPU *checker; 1298887Sgeoffrey.blake@arm.com 1305169Ssaidi@eecs.umich.edu protected: 1315169Ssaidi@eecs.umich.edu 1325496Ssaidi@eecs.umich.edu enum Status { 1335496Ssaidi@eecs.umich.edu Idle, 1345496Ssaidi@eecs.umich.edu Running, 1358276SAli.Saidi@ARM.com Faulting, 1365894Sgblack@eecs.umich.edu ITBWaitResponse, 1375496Ssaidi@eecs.umich.edu IcacheRetry, 1385496Ssaidi@eecs.umich.edu IcacheWaitResponse, 1395496Ssaidi@eecs.umich.edu IcacheWaitSwitch, 1405894Sgblack@eecs.umich.edu DTBWaitResponse, 1415496Ssaidi@eecs.umich.edu DcacheRetry, 1425496Ssaidi@eecs.umich.edu DcacheWaitResponse, 1435496Ssaidi@eecs.umich.edu DcacheWaitSwitch, 1445496Ssaidi@eecs.umich.edu }; 1455496Ssaidi@eecs.umich.edu 1465496Ssaidi@eecs.umich.edu Status _status; 1475496Ssaidi@eecs.umich.edu 1485169Ssaidi@eecs.umich.edu public: 1492SN/A 1502SN/A Addr dbg_vtophys(Addr addr); 1512SN/A 1522SN/A bool interval_stats; 1532SN/A 1542SN/A // current instruction 1554181Sgblack@eecs.umich.edu TheISA::MachInst inst; 1564181Sgblack@eecs.umich.edu 1572107SN/A StaticInstPtr curStaticInst; 1583276Sgblack@eecs.umich.edu StaticInstPtr curMacroStaticInst; 1591469SN/A 1604377Sgblack@eecs.umich.edu //This is the offset from the current pc that fetch should be performed at 1614377Sgblack@eecs.umich.edu Addr fetchOffset; 1624377Sgblack@eecs.umich.edu //This flag says to stay at the current pc. This is useful for 1634377Sgblack@eecs.umich.edu //instructions which go beyond MachInst boundaries. 1644377Sgblack@eecs.umich.edu bool stayAtPC; 1654377Sgblack@eecs.umich.edu 1662623SN/A void checkForInterrupts(); 1675894Sgblack@eecs.umich.edu void setupFetchRequest(Request *req); 1682623SN/A void preExecute(); 1692623SN/A void postExecute(); 1702623SN/A void advancePC(Fault fault); 171180SN/A 1728737Skoansin.tan@gmail.com virtual void deallocateContext(ThreadID thread_num); 1738737Skoansin.tan@gmail.com virtual void haltContext(ThreadID thread_num); 1742SN/A 1752SN/A // statistics 176334SN/A virtual void regStats(); 177334SN/A virtual void resetStats(); 1782SN/A 1799461Snilay@cs.wisc.edu virtual void startup(); 1809461Snilay@cs.wisc.edu 1812SN/A // number of simulated instructions 1822SN/A Counter numInst; 183334SN/A Counter startNumInst; 1845999Snate@binkert.org Stats::Scalar numInsts; 1858834Satgutier@umich.edu Counter numOp; 1868834Satgutier@umich.edu Counter startNumOp; 1878834Satgutier@umich.edu Stats::Scalar numOps; 188707SN/A 1894998Sgblack@eecs.umich.edu void countInst() 1904998Sgblack@eecs.umich.edu { 1918834Satgutier@umich.edu if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) { 1928834Satgutier@umich.edu numInst++; 1938834Satgutier@umich.edu numInsts++; 1948834Satgutier@umich.edu } 1958834Satgutier@umich.edu numOp++; 1968834Satgutier@umich.edu numOps++; 1978834Satgutier@umich.edu 1987897Shestness@cs.utexas.edu system->totalNumInsts++; 1994998Sgblack@eecs.umich.edu thread->funcExeInst++; 2004998Sgblack@eecs.umich.edu } 2014998Sgblack@eecs.umich.edu 2028834Satgutier@umich.edu virtual Counter totalInsts() const 203707SN/A { 204707SN/A return numInst - startNumInst; 205707SN/A } 2062SN/A 2078834Satgutier@umich.edu virtual Counter totalOps() const 2088834Satgutier@umich.edu { 2098834Satgutier@umich.edu return numOp - startNumOp; 2108834Satgutier@umich.edu } 2118834Satgutier@umich.edu 2127897Shestness@cs.utexas.edu //number of integer alu accesses 2137897Shestness@cs.utexas.edu Stats::Scalar numIntAluAccesses; 2147897Shestness@cs.utexas.edu 2157897Shestness@cs.utexas.edu //number of float alu accesses 2167897Shestness@cs.utexas.edu Stats::Scalar numFpAluAccesses; 2177897Shestness@cs.utexas.edu 2187897Shestness@cs.utexas.edu //number of function calls/returns 2197897Shestness@cs.utexas.edu Stats::Scalar numCallsReturns; 2207897Shestness@cs.utexas.edu 2217897Shestness@cs.utexas.edu //conditional control instructions; 2227897Shestness@cs.utexas.edu Stats::Scalar numCondCtrlInsts; 2237897Shestness@cs.utexas.edu 2247897Shestness@cs.utexas.edu //number of int instructions 2257897Shestness@cs.utexas.edu Stats::Scalar numIntInsts; 2267897Shestness@cs.utexas.edu 2277897Shestness@cs.utexas.edu //number of float instructions 2287897Shestness@cs.utexas.edu Stats::Scalar numFpInsts; 2297897Shestness@cs.utexas.edu 2307897Shestness@cs.utexas.edu //number of integer register file accesses 2317897Shestness@cs.utexas.edu Stats::Scalar numIntRegReads; 2327897Shestness@cs.utexas.edu Stats::Scalar numIntRegWrites; 2337897Shestness@cs.utexas.edu 2347897Shestness@cs.utexas.edu //number of float register file accesses 2357897Shestness@cs.utexas.edu Stats::Scalar numFpRegReads; 2367897Shestness@cs.utexas.edu Stats::Scalar numFpRegWrites; 2377897Shestness@cs.utexas.edu 2389920Syasuko.eckert@amd.com //number of condition code register file accesses 2399920Syasuko.eckert@amd.com Stats::Scalar numCCRegReads; 2409920Syasuko.eckert@amd.com Stats::Scalar numCCRegWrites; 2419920Syasuko.eckert@amd.com 2422SN/A // number of simulated memory references 2435999Snate@binkert.org Stats::Scalar numMemRefs; 2447897Shestness@cs.utexas.edu Stats::Scalar numLoadInsts; 2457897Shestness@cs.utexas.edu Stats::Scalar numStoreInsts; 2467897Shestness@cs.utexas.edu 2477897Shestness@cs.utexas.edu // number of idle cycles 2487897Shestness@cs.utexas.edu Stats::Formula numIdleCycles; 2497897Shestness@cs.utexas.edu 2507897Shestness@cs.utexas.edu // number of busy cycles 2517897Shestness@cs.utexas.edu Stats::Formula numBusyCycles; 2522SN/A 253124SN/A // number of simulated loads 254124SN/A Counter numLoad; 255334SN/A Counter startNumLoad; 256124SN/A 2572SN/A // number of idle cycles 2585999Snate@binkert.org Stats::Average notIdleFraction; 259729SN/A Stats::Formula idleFraction; 2602SN/A 2612390SN/A // number of cycles stalled for I-cache responses 2625999Snate@binkert.org Stats::Scalar icacheStallCycles; 2632SN/A Counter lastIcacheStall; 2642SN/A 2652390SN/A // number of cycles stalled for I-cache retries 2665999Snate@binkert.org Stats::Scalar icacheRetryCycles; 2672390SN/A Counter lastIcacheRetry; 2682390SN/A 2692390SN/A // number of cycles stalled for D-cache responses 2705999Snate@binkert.org Stats::Scalar dcacheStallCycles; 2712SN/A Counter lastDcacheStall; 2722SN/A 2732390SN/A // number of cycles stalled for D-cache retries 2745999Snate@binkert.org Stats::Scalar dcacheRetryCycles; 2752390SN/A Counter lastDcacheRetry; 2762390SN/A 27710061Sandreas@sandberg.pp.se /// @{ 27810061Sandreas@sandberg.pp.se /// Total number of branches fetched 27910061Sandreas@sandberg.pp.se Stats::Scalar numBranches; 28010061Sandreas@sandberg.pp.se /// Number of branches predicted as taken 28110061Sandreas@sandberg.pp.se Stats::Scalar numPredictedBranches; 28210061Sandreas@sandberg.pp.se /// Number of misprediced branches 28310061Sandreas@sandberg.pp.se Stats::Scalar numBranchMispred; 28410061Sandreas@sandberg.pp.se /// @} 28510061Sandreas@sandberg.pp.se 2869448SAndreas.Sandberg@ARM.com void serializeThread(std::ostream &os, ThreadID tid); 2879448SAndreas.Sandberg@ARM.com void unserializeThread(Checkpoint *cp, const std::string §ion, 2889448SAndreas.Sandberg@ARM.com ThreadID tid); 2892SN/A 2901371SN/A // These functions are only used in CPU models that split 2911371SN/A // effective address computation from the actual memory access. 2922623SN/A void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 2935543Ssaidi@eecs.umich.edu Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); 2943918Ssaidi@eecs.umich.edu M5_DUMMY_RETURN} 2951371SN/A 296726SN/A // The register accessor methods provide the index of the 297726SN/A // instruction's operand (e.g., 0 or 1), not the architectural 298726SN/A // register index, to simplify the implementation of register 299726SN/A // renaming. We find the architectural register index by indexing 300726SN/A // into the instruction's own operand index table. Note that a 301726SN/A // raw pointer to the StaticInst is provided instead of a 302726SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 303726SN/A // long as these methods don't copy the pointer into any long-term 304726SN/A // storage (which is pretty hard to imagine they would have reason 305726SN/A // to do). 306705SN/A 3073735Sstever@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx) 308726SN/A { 3097897Shestness@cs.utexas.edu numIntRegReads++; 3102683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 311726SN/A } 312705SN/A 3133735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 314726SN/A { 3157897Shestness@cs.utexas.edu numFpRegReads++; 3169918Ssteve.reinhardt@amd.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 3172683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 318726SN/A } 319705SN/A 3203735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 3212455SN/A { 3227897Shestness@cs.utexas.edu numFpRegReads++; 3239918Ssteve.reinhardt@amd.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 3242683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 325726SN/A } 326705SN/A 3279920Syasuko.eckert@amd.com CCReg readCCRegOperand(const StaticInst *si, int idx) 3289920Syasuko.eckert@amd.com { 3299920Syasuko.eckert@amd.com numCCRegReads++; 3309920Syasuko.eckert@amd.com int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; 3319920Syasuko.eckert@amd.com return thread->readCCReg(reg_idx); 3329920Syasuko.eckert@amd.com } 3339920Syasuko.eckert@amd.com 3343735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 335726SN/A { 3367897Shestness@cs.utexas.edu numIntRegWrites++; 3372683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 338726SN/A } 339705SN/A 3403735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 341726SN/A { 3427897Shestness@cs.utexas.edu numFpRegWrites++; 3439918Ssteve.reinhardt@amd.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 3442683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 345726SN/A } 346726SN/A 3473735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 3483735Sstever@eecs.umich.edu FloatRegBits val) 3492455SN/A { 3507897Shestness@cs.utexas.edu numFpRegWrites++; 3519918Ssteve.reinhardt@amd.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 3522683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 353726SN/A } 354705SN/A 3559920Syasuko.eckert@amd.com void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 3569920Syasuko.eckert@amd.com { 3579920Syasuko.eckert@amd.com numCCRegWrites++; 3589920Syasuko.eckert@amd.com int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; 3599920Syasuko.eckert@amd.com thread->setCCReg(reg_idx, val); 3609920Syasuko.eckert@amd.com } 3619920Syasuko.eckert@amd.com 3627597Sminkyu.jeong@arm.com bool readPredicate() { return thread->readPredicate(); } 3637597Sminkyu.jeong@arm.com void setPredicate(bool val) 3647600Sminkyu.jeong@arm.com { 3657600Sminkyu.jeong@arm.com thread->setPredicate(val); 3667600Sminkyu.jeong@arm.com if (traceData) { 3677600Sminkyu.jeong@arm.com traceData->setPredicate(val); 3687600Sminkyu.jeong@arm.com } 3697600Sminkyu.jeong@arm.com } 3707720Sgblack@eecs.umich.edu TheISA::PCState pcState() { return thread->pcState(); } 3717720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val) { thread->pcState(val); } 3727720Sgblack@eecs.umich.edu Addr instAddr() { return thread->instAddr(); } 3737720Sgblack@eecs.umich.edu Addr nextInstAddr() { return thread->nextInstAddr(); } 3747720Sgblack@eecs.umich.edu MicroPC microPC() { return thread->microPC(); } 375705SN/A 3764172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 3774172Ssaidi@eecs.umich.edu { 3784172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 3794172Ssaidi@eecs.umich.edu } 3804172Ssaidi@eecs.umich.edu 3812159SN/A MiscReg readMiscReg(int misc_reg) 3822159SN/A { 3837897Shestness@cs.utexas.edu numIntRegReads++; 3842683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 3852159SN/A } 386705SN/A 3873468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 3882159SN/A { 3897897Shestness@cs.utexas.edu numIntRegWrites++; 3902683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3912159SN/A } 3922159SN/A 3934185Ssaidi@eecs.umich.edu MiscReg readMiscRegOperand(const StaticInst *si, int idx) 3943792Sgblack@eecs.umich.edu { 3957897Shestness@cs.utexas.edu numIntRegReads++; 3969918Ssteve.reinhardt@amd.com int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base; 3973792Sgblack@eecs.umich.edu return thread->readMiscReg(reg_idx); 3983792Sgblack@eecs.umich.edu } 3993792Sgblack@eecs.umich.edu 4004185Ssaidi@eecs.umich.edu void setMiscRegOperand( 4013792Sgblack@eecs.umich.edu const StaticInst *si, int idx, const MiscReg &val) 4023792Sgblack@eecs.umich.edu { 4037897Shestness@cs.utexas.edu numIntRegWrites++; 4049918Ssteve.reinhardt@amd.com int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; 4054172Ssaidi@eecs.umich.edu return thread->setMiscReg(reg_idx, val); 4063792Sgblack@eecs.umich.edu } 4073792Sgblack@eecs.umich.edu 4085358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 4095358Sgblack@eecs.umich.edu { 4105358Sgblack@eecs.umich.edu thread->demapPage(vaddr, asn); 4115358Sgblack@eecs.umich.edu } 4125358Sgblack@eecs.umich.edu 4135358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 4145358Sgblack@eecs.umich.edu { 4155358Sgblack@eecs.umich.edu thread->demapInstPage(vaddr, asn); 4165358Sgblack@eecs.umich.edu } 4175358Sgblack@eecs.umich.edu 4185358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 4195358Sgblack@eecs.umich.edu { 4205358Sgblack@eecs.umich.edu thread->demapDataPage(vaddr, asn); 4215358Sgblack@eecs.umich.edu } 4225358Sgblack@eecs.umich.edu 4234027Sstever@eecs.umich.edu unsigned readStCondFailures() { 4244027Sstever@eecs.umich.edu return thread->readStCondFailures(); 4254027Sstever@eecs.umich.edu } 4264027Sstever@eecs.umich.edu 4274027Sstever@eecs.umich.edu void setStCondFailures(unsigned sc_failures) { 4284027Sstever@eecs.umich.edu thread->setStCondFailures(sc_failures); 4294027Sstever@eecs.umich.edu } 4304027Sstever@eecs.umich.edu 4316221Snate@binkert.org MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID) 4324661Sksewell@umich.edu { 4334661Sksewell@umich.edu panic("Simple CPU models do not support multithreaded " 4344661Sksewell@umich.edu "register access.\n"); 4354661Sksewell@umich.edu } 4364661Sksewell@umich.edu 4376221Snate@binkert.org void setRegOtherThread(int regIdx, const MiscReg &val, 4386221Snate@binkert.org ThreadID tid = InvalidThreadID) 4394661Sksewell@umich.edu { 4404661Sksewell@umich.edu panic("Simple CPU models do not support multithreaded " 4414661Sksewell@umich.edu "register access.\n"); 4424661Sksewell@umich.edu } 4434661Sksewell@umich.edu 4445250Sksewell@umich.edu //Fault CacheOp(uint8_t Op, Addr EA); 4455222Sksewell@umich.edu 4465702Ssaidi@eecs.umich.edu Fault hwrei() { return thread->hwrei(); } 4475702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 4488557Sgblack@eecs.umich.edu 4498557Sgblack@eecs.umich.edu void 4508557Sgblack@eecs.umich.edu syscall(int64_t callnum) 4518557Sgblack@eecs.umich.edu { 4528779Sgblack@eecs.umich.edu if (FullSystem) 4538779Sgblack@eecs.umich.edu panic("Syscall emulation isn't available in FS mode.\n"); 4548806Sgblack@eecs.umich.edu 4558557Sgblack@eecs.umich.edu thread->syscall(callnum); 4568557Sgblack@eecs.umich.edu } 457705SN/A 4582683Sktlim@umich.edu bool misspeculating() { return thread->misspeculating(); } 4592680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 46010061Sandreas@sandberg.pp.se 46110061Sandreas@sandberg.pp.se private: 46210061Sandreas@sandberg.pp.se TheISA::PCState pred_pc; 4632SN/A}; 4642SN/A 4652623SN/A#endif // __CPU_SIMPLE_BASE_HH__ 466