atomic.hh revision 10407
1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 */ 42 43#ifndef __CPU_SIMPLE_ATOMIC_HH__ 44#define __CPU_SIMPLE_ATOMIC_HH__ 45 46#include "cpu/simple/base.hh" 47#include "params/AtomicSimpleCPU.hh" 48#include "sim/probe/probe.hh" 49 50class AtomicSimpleCPU : public BaseSimpleCPU 51{ 52 public: 53 54 AtomicSimpleCPU(AtomicSimpleCPUParams *params); 55 virtual ~AtomicSimpleCPU(); 56 57 virtual void init(); 58 59 private: 60 61 struct TickEvent : public Event 62 { 63 AtomicSimpleCPU *cpu; 64 65 TickEvent(AtomicSimpleCPU *c); 66 void process(); 67 const char *description() const; 68 }; 69 70 TickEvent tickEvent; 71 72 const int width; 73 bool locked; 74 const bool simulate_data_stalls; 75 const bool simulate_inst_stalls; 76 77 /** 78 * Drain manager to use when signaling drain completion 79 * 80 * This pointer is non-NULL when draining and NULL otherwise. 81 */ 82 DrainManager *drain_manager; 83 84 // main simulation loop (one cycle) 85 void tick(); 86 87 /** 88 * Check if a system is in a drained state. 89 * 90 * We need to drain if: 91 * <ul> 92 * <li>We are in the middle of a microcode sequence as some CPUs 93 * (e.g., HW accelerated CPUs) can't be started in the middle 94 * of a gem5 microcode sequence. 95 * 96 * <li>The CPU is in a LLSC region. This shouldn't normally happen 97 * as these are executed atomically within a single tick() 98 * call. The only way this can happen at the moment is if 99 * there is an event in the PC event queue that affects the 100 * CPU state while it is in an LLSC region. 101 * 102 * <li>Stay at PC is true. 103 * </ul> 104 */ 105 bool isDrained() { 106 return microPC() == 0 && 107 !locked && 108 !stayAtPC; 109 } 110 111 /** 112 * Try to complete a drain request. 113 * 114 * @returns true if the CPU is drained, false otherwise. 115 */ 116 bool tryCompleteDrain(); 117 118 /** 119 * An AtomicCPUPort overrides the default behaviour of the 120 * recvAtomicSnoop and ignores the packet instead of panicking. It 121 * also provides an implementation for the purely virtual timing 122 * functions and panics on either of these. 123 */ 124 class AtomicCPUPort : public MasterPort 125 { 126 127 public: 128 129 AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu) 130 : MasterPort(_name, _cpu) 131 { } 132 133 protected: 134 virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; } 135 136 bool recvTimingResp(PacketPtr pkt) 137 { 138 panic("Atomic CPU doesn't expect recvTimingResp!\n"); 139 return true; 140 } 141 142 void recvRetry() 143 { 144 panic("Atomic CPU doesn't expect recvRetry!\n"); 145 } 146 147 }; 148 149 class AtomicCPUDPort : public AtomicCPUPort 150 { 151 152 public: 153 154 AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu) 155 : AtomicCPUPort(_name, _cpu), cpu(_cpu) 156 { 157 cacheBlockMask = ~(cpu->cacheLineSize() - 1); 158 } 159 160 bool isSnooping() const { return true; } 161 162 Addr cacheBlockMask; 163 protected: 164 BaseSimpleCPU *cpu; 165 166 virtual Tick recvAtomicSnoop(PacketPtr pkt); 167 virtual void recvFunctionalSnoop(PacketPtr pkt); 168 }; 169 170 171 AtomicCPUPort icachePort; 172 AtomicCPUDPort dcachePort; 173 174 bool fastmem; 175 Request ifetch_req; 176 Request data_read_req; 177 Request data_write_req; 178 179 bool dcache_access; 180 Tick dcache_latency; 181 182 /** Probe Points. */ 183 ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit; 184 185 protected: 186 187 /** Return a reference to the data port. */ 188 virtual MasterPort &getDataPort() { return dcachePort; } 189 190 /** Return a reference to the instruction port. */ 191 virtual MasterPort &getInstPort() { return icachePort; } 192 193 public: 194 195 unsigned int drain(DrainManager *drain_manager); 196 void drainResume(); 197 198 void switchOut(); 199 void takeOverFrom(BaseCPU *oldCPU); 200 201 void verifyMemoryMode() const; 202 203 virtual void activateContext(ThreadID thread_num); 204 virtual void suspendContext(ThreadID thread_num); 205 206 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 207 208 Fault writeMem(uint8_t *data, unsigned size, 209 Addr addr, unsigned flags, uint64_t *res); 210 211 virtual void regProbePoints(); 212 213 /** 214 * Print state of address in memory system via PrintReq (for 215 * debugging). 216 */ 217 void printAddr(Addr a); 218}; 219 220#endif // __CPU_SIMPLE_ATOMIC_HH__ 221