atomic.hh revision 9704
12623SN/A/* 29608Sandreas.hansson@arm.com * Copyright (c) 2012-2013 ARM Limited 38926Sandreas.hansson@arm.com * All rights reserved. 48926Sandreas.hansson@arm.com * 58926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138926Sandreas.hansson@arm.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 432623SN/A#ifndef __CPU_SIMPLE_ATOMIC_HH__ 442623SN/A#define __CPU_SIMPLE_ATOMIC_HH__ 452623SN/A 469647Sdam.sunwoo@arm.com#include "base/hashmap.hh" 472623SN/A#include "cpu/simple/base.hh" 485529Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 492623SN/A 509647Sdam.sunwoo@arm.com/** 519647Sdam.sunwoo@arm.com * Start and end address of basic block for SimPoint profiling. 529647Sdam.sunwoo@arm.com * This structure is used to look up the hash table of BBVs. 539647Sdam.sunwoo@arm.com * - first: PC of first inst in basic block 549647Sdam.sunwoo@arm.com * - second: PC of last inst in basic block 559647Sdam.sunwoo@arm.com */ 569647Sdam.sunwoo@arm.comtypedef std::pair<Addr, Addr> BasicBlockRange; 579647Sdam.sunwoo@arm.com 589647Sdam.sunwoo@arm.com/** Overload hash function for BasicBlockRange type */ 599647Sdam.sunwoo@arm.com__hash_namespace_begin 609647Sdam.sunwoo@arm.comtemplate <> 619704Sandreas.hansson@arm.comstruct hash<BasicBlockRange> 629647Sdam.sunwoo@arm.com{ 639647Sdam.sunwoo@arm.com public: 649647Sdam.sunwoo@arm.com size_t operator()(const BasicBlockRange &bb) const { 659647Sdam.sunwoo@arm.com return hash<Addr>()(bb.first + bb.second); 669647Sdam.sunwoo@arm.com } 679647Sdam.sunwoo@arm.com}; 689647Sdam.sunwoo@arm.com__hash_namespace_end 699647Sdam.sunwoo@arm.com 709647Sdam.sunwoo@arm.com 712623SN/Aclass AtomicSimpleCPU : public BaseSimpleCPU 722623SN/A{ 732623SN/A public: 742623SN/A 755529Snate@binkert.org AtomicSimpleCPU(AtomicSimpleCPUParams *params); 762623SN/A virtual ~AtomicSimpleCPU(); 772623SN/A 782623SN/A virtual void init(); 792623SN/A 802623SN/A private: 812623SN/A 822623SN/A struct TickEvent : public Event 832623SN/A { 842623SN/A AtomicSimpleCPU *cpu; 852623SN/A 862623SN/A TickEvent(AtomicSimpleCPU *c); 872623SN/A void process(); 885336Shines@cs.fsu.edu const char *description() const; 892623SN/A }; 902623SN/A 912623SN/A TickEvent tickEvent; 922623SN/A 932623SN/A const int width; 946078Sgblack@eecs.umich.edu bool locked; 955487Snate@binkert.org const bool simulate_data_stalls; 965487Snate@binkert.org const bool simulate_inst_stalls; 972623SN/A 989443SAndreas.Sandberg@ARM.com /** 999443SAndreas.Sandberg@ARM.com * Drain manager to use when signaling drain completion 1009443SAndreas.Sandberg@ARM.com * 1019443SAndreas.Sandberg@ARM.com * This pointer is non-NULL when draining and NULL otherwise. 1029443SAndreas.Sandberg@ARM.com */ 1039443SAndreas.Sandberg@ARM.com DrainManager *drain_manager; 1049443SAndreas.Sandberg@ARM.com 1052623SN/A // main simulation loop (one cycle) 1062623SN/A void tick(); 1072623SN/A 1088707Sandreas.hansson@arm.com /** 1099443SAndreas.Sandberg@ARM.com * Check if a system is in a drained state. 1109443SAndreas.Sandberg@ARM.com * 1119443SAndreas.Sandberg@ARM.com * We need to drain if: 1129443SAndreas.Sandberg@ARM.com * <ul> 1139443SAndreas.Sandberg@ARM.com * <li>We are in the middle of a microcode sequence as some CPUs 1149443SAndreas.Sandberg@ARM.com * (e.g., HW accelerated CPUs) can't be started in the middle 1159443SAndreas.Sandberg@ARM.com * of a gem5 microcode sequence. 1169443SAndreas.Sandberg@ARM.com * 1179443SAndreas.Sandberg@ARM.com * <li>The CPU is in a LLSC region. This shouldn't normally happen 1189443SAndreas.Sandberg@ARM.com * as these are executed atomically within a single tick() 1199443SAndreas.Sandberg@ARM.com * call. The only way this can happen at the moment is if 1209443SAndreas.Sandberg@ARM.com * there is an event in the PC event queue that affects the 1219443SAndreas.Sandberg@ARM.com * CPU state while it is in an LLSC region. 1229443SAndreas.Sandberg@ARM.com * 1239443SAndreas.Sandberg@ARM.com * <li>Stay at PC is true. 1249443SAndreas.Sandberg@ARM.com * </ul> 1259443SAndreas.Sandberg@ARM.com */ 1269443SAndreas.Sandberg@ARM.com bool isDrained() { 1279443SAndreas.Sandberg@ARM.com return microPC() == 0 && 1289443SAndreas.Sandberg@ARM.com !locked && 1299443SAndreas.Sandberg@ARM.com !stayAtPC; 1309443SAndreas.Sandberg@ARM.com } 1319443SAndreas.Sandberg@ARM.com 1329443SAndreas.Sandberg@ARM.com /** 1339443SAndreas.Sandberg@ARM.com * Try to complete a drain request. 1349443SAndreas.Sandberg@ARM.com * 1359443SAndreas.Sandberg@ARM.com * @returns true if the CPU is drained, false otherwise. 1369443SAndreas.Sandberg@ARM.com */ 1379443SAndreas.Sandberg@ARM.com bool tryCompleteDrain(); 1389443SAndreas.Sandberg@ARM.com 1399443SAndreas.Sandberg@ARM.com /** 1408707Sandreas.hansson@arm.com * An AtomicCPUPort overrides the default behaviour of the 1419608Sandreas.hansson@arm.com * recvAtomicSnoop and ignores the packet instead of panicking. It 1429608Sandreas.hansson@arm.com * also provides an implementation for the purely virtual timing 1439608Sandreas.hansson@arm.com * functions and panics on either of these. 1448707Sandreas.hansson@arm.com */ 1459608Sandreas.hansson@arm.com class AtomicCPUPort : public MasterPort 1462623SN/A { 1478707Sandreas.hansson@arm.com 1482623SN/A public: 1492623SN/A 1508707Sandreas.hansson@arm.com AtomicCPUPort(const std::string &_name, BaseCPU* _cpu) 1519608Sandreas.hansson@arm.com : MasterPort(_name, _cpu) 1522623SN/A { } 1532623SN/A 1542623SN/A protected: 1552623SN/A 1568948Sandreas.hansson@arm.com virtual Tick recvAtomicSnoop(PacketPtr pkt) 1578707Sandreas.hansson@arm.com { 1588707Sandreas.hansson@arm.com // Snooping a coherence request, just return 1598707Sandreas.hansson@arm.com return 0; 1608707Sandreas.hansson@arm.com } 1613192Srdreslin@umich.edu 1629608Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt) 1639608Sandreas.hansson@arm.com { 1649608Sandreas.hansson@arm.com panic("Atomic CPU doesn't expect recvTimingResp!\n"); 1659608Sandreas.hansson@arm.com return true; 1669608Sandreas.hansson@arm.com } 1679608Sandreas.hansson@arm.com 1689608Sandreas.hansson@arm.com void recvRetry() 1699608Sandreas.hansson@arm.com { 1709608Sandreas.hansson@arm.com panic("Atomic CPU doesn't expect recvRetry!\n"); 1719608Sandreas.hansson@arm.com } 1729608Sandreas.hansson@arm.com 1732623SN/A }; 1744192Sktlim@umich.edu 1758707Sandreas.hansson@arm.com AtomicCPUPort icachePort; 1768707Sandreas.hansson@arm.com AtomicCPUPort dcachePort; 1772623SN/A 1788926Sandreas.hansson@arm.com bool fastmem; 1794870Sstever@eecs.umich.edu Request ifetch_req; 1804870Sstever@eecs.umich.edu Request data_read_req; 1814870Sstever@eecs.umich.edu Request data_write_req; 1822623SN/A 1832623SN/A bool dcache_access; 1842662Sstever@eecs.umich.edu Tick dcache_latency; 1852623SN/A 1869647Sdam.sunwoo@arm.com /** 1879647Sdam.sunwoo@arm.com * Profile basic blocks for SimPoints. 1889647Sdam.sunwoo@arm.com * Called at every macro inst to increment basic block inst counts and 1899647Sdam.sunwoo@arm.com * to profile block if end of block. 1909647Sdam.sunwoo@arm.com */ 1919647Sdam.sunwoo@arm.com void profileSimPoint(); 1929647Sdam.sunwoo@arm.com 1939647Sdam.sunwoo@arm.com /** Data structures for SimPoints BBV generation 1949647Sdam.sunwoo@arm.com * @{ 1959647Sdam.sunwoo@arm.com */ 1969647Sdam.sunwoo@arm.com 1979647Sdam.sunwoo@arm.com /** Whether SimPoint BBV profiling is enabled */ 1989647Sdam.sunwoo@arm.com const bool simpoint; 1999647Sdam.sunwoo@arm.com /** SimPoint profiling interval size in instructions */ 2009647Sdam.sunwoo@arm.com const uint64_t intervalSize; 2019647Sdam.sunwoo@arm.com 2029647Sdam.sunwoo@arm.com /** Inst count in current basic block */ 2039647Sdam.sunwoo@arm.com uint64_t intervalCount; 2049647Sdam.sunwoo@arm.com /** Excess inst count from previous interval*/ 2059647Sdam.sunwoo@arm.com uint64_t intervalDrift; 2069647Sdam.sunwoo@arm.com /** Pointer to SimPoint BBV output stream */ 2079647Sdam.sunwoo@arm.com std::ostream *simpointStream; 2089647Sdam.sunwoo@arm.com 2099647Sdam.sunwoo@arm.com /** Basic Block information */ 2109647Sdam.sunwoo@arm.com struct BBInfo { 2119647Sdam.sunwoo@arm.com /** Unique ID */ 2129647Sdam.sunwoo@arm.com uint64_t id; 2139647Sdam.sunwoo@arm.com /** Num of static insts in BB */ 2149647Sdam.sunwoo@arm.com uint64_t insts; 2159647Sdam.sunwoo@arm.com /** Accumulated dynamic inst count executed by BB */ 2169647Sdam.sunwoo@arm.com uint64_t count; 2179647Sdam.sunwoo@arm.com }; 2189647Sdam.sunwoo@arm.com 2199647Sdam.sunwoo@arm.com /** Hash table containing all previously seen basic blocks */ 2209647Sdam.sunwoo@arm.com m5::hash_map<BasicBlockRange, BBInfo> bbMap; 2219647Sdam.sunwoo@arm.com /** Currently executing basic block */ 2229647Sdam.sunwoo@arm.com BasicBlockRange currentBBV; 2239647Sdam.sunwoo@arm.com /** inst count in current basic block */ 2249647Sdam.sunwoo@arm.com uint64_t currentBBVInstCount; 2259647Sdam.sunwoo@arm.com 2269647Sdam.sunwoo@arm.com /** @} 2279647Sdam.sunwoo@arm.com * End of data structures for SimPoints BBV generation 2289647Sdam.sunwoo@arm.com */ 2299647Sdam.sunwoo@arm.com 2308850Sandreas.hansson@arm.com protected: 2318850Sandreas.hansson@arm.com 2328850Sandreas.hansson@arm.com /** Return a reference to the data port. */ 2339608Sandreas.hansson@arm.com virtual MasterPort &getDataPort() { return dcachePort; } 2348850Sandreas.hansson@arm.com 2358850Sandreas.hansson@arm.com /** Return a reference to the instruction port. */ 2369608Sandreas.hansson@arm.com virtual MasterPort &getInstPort() { return icachePort; } 2378850Sandreas.hansson@arm.com 2382623SN/A public: 2392623SN/A 2409342SAndreas.Sandberg@arm.com unsigned int drain(DrainManager *drain_manager); 2419342SAndreas.Sandberg@arm.com void drainResume(); 2422623SN/A 2432798Sktlim@umich.edu void switchOut(); 2442623SN/A void takeOverFrom(BaseCPU *oldCPU); 2452623SN/A 2469523SAndreas.Sandberg@ARM.com void verifyMemoryMode() const; 2479523SAndreas.Sandberg@ARM.com 2489180Sandreas.hansson@arm.com virtual void activateContext(ThreadID thread_num, Cycles delay); 2498737Skoansin.tan@gmail.com virtual void suspendContext(ThreadID thread_num); 2502623SN/A 2518444Sgblack@eecs.umich.edu Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 2527520Sgblack@eecs.umich.edu 2538444Sgblack@eecs.umich.edu Fault writeMem(uint8_t *data, unsigned size, 2548444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res); 2557520Sgblack@eecs.umich.edu 2565315Sstever@gmail.com /** 2575315Sstever@gmail.com * Print state of address in memory system via PrintReq (for 2585315Sstever@gmail.com * debugging). 2595315Sstever@gmail.com */ 2605315Sstever@gmail.com void printAddr(Addr a); 2612623SN/A}; 2622623SN/A 2632623SN/A#endif // __CPU_SIMPLE_ATOMIC_HH__ 264