atomic.hh revision 9342
12623SN/A/* 28926Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited 38926Sandreas.hansson@arm.com * All rights reserved. 48926Sandreas.hansson@arm.com * 58926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138926Sandreas.hansson@arm.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 432623SN/A#ifndef __CPU_SIMPLE_ATOMIC_HH__ 442623SN/A#define __CPU_SIMPLE_ATOMIC_HH__ 452623SN/A 462623SN/A#include "cpu/simple/base.hh" 475529Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 482623SN/A 492623SN/Aclass AtomicSimpleCPU : public BaseSimpleCPU 502623SN/A{ 512623SN/A public: 522623SN/A 535529Snate@binkert.org AtomicSimpleCPU(AtomicSimpleCPUParams *params); 542623SN/A virtual ~AtomicSimpleCPU(); 552623SN/A 562623SN/A virtual void init(); 572623SN/A 582623SN/A private: 592623SN/A 602623SN/A struct TickEvent : public Event 612623SN/A { 622623SN/A AtomicSimpleCPU *cpu; 632623SN/A 642623SN/A TickEvent(AtomicSimpleCPU *c); 652623SN/A void process(); 665336Shines@cs.fsu.edu const char *description() const; 672623SN/A }; 682623SN/A 692623SN/A TickEvent tickEvent; 702623SN/A 712623SN/A const int width; 726078Sgblack@eecs.umich.edu bool locked; 735487Snate@binkert.org const bool simulate_data_stalls; 745487Snate@binkert.org const bool simulate_inst_stalls; 752623SN/A 762623SN/A // main simulation loop (one cycle) 772623SN/A void tick(); 782623SN/A 798707Sandreas.hansson@arm.com /** 808707Sandreas.hansson@arm.com * An AtomicCPUPort overrides the default behaviour of the 818707Sandreas.hansson@arm.com * recvAtomic and ignores the packet instead of panicking. 828707Sandreas.hansson@arm.com */ 838707Sandreas.hansson@arm.com class AtomicCPUPort : public CpuPort 842623SN/A { 858707Sandreas.hansson@arm.com 862623SN/A public: 872623SN/A 888707Sandreas.hansson@arm.com AtomicCPUPort(const std::string &_name, BaseCPU* _cpu) 898707Sandreas.hansson@arm.com : CpuPort(_name, _cpu) 902623SN/A { } 912623SN/A 922623SN/A protected: 932623SN/A 948948Sandreas.hansson@arm.com virtual Tick recvAtomicSnoop(PacketPtr pkt) 958707Sandreas.hansson@arm.com { 968707Sandreas.hansson@arm.com // Snooping a coherence request, just return 978707Sandreas.hansson@arm.com return 0; 988707Sandreas.hansson@arm.com } 993192Srdreslin@umich.edu 1002623SN/A }; 1014192Sktlim@umich.edu 1028707Sandreas.hansson@arm.com AtomicCPUPort icachePort; 1038707Sandreas.hansson@arm.com AtomicCPUPort dcachePort; 1042623SN/A 1058926Sandreas.hansson@arm.com bool fastmem; 1064870Sstever@eecs.umich.edu Request ifetch_req; 1074870Sstever@eecs.umich.edu Request data_read_req; 1084870Sstever@eecs.umich.edu Request data_write_req; 1092623SN/A 1102623SN/A bool dcache_access; 1112662Sstever@eecs.umich.edu Tick dcache_latency; 1122623SN/A 1138850Sandreas.hansson@arm.com protected: 1148850Sandreas.hansson@arm.com 1158850Sandreas.hansson@arm.com /** Return a reference to the data port. */ 1168850Sandreas.hansson@arm.com virtual CpuPort &getDataPort() { return dcachePort; } 1178850Sandreas.hansson@arm.com 1188850Sandreas.hansson@arm.com /** Return a reference to the instruction port. */ 1198850Sandreas.hansson@arm.com virtual CpuPort &getInstPort() { return icachePort; } 1208850Sandreas.hansson@arm.com 1212623SN/A public: 1222623SN/A 1232623SN/A virtual void serialize(std::ostream &os); 1242623SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1259342SAndreas.Sandberg@arm.com 1269342SAndreas.Sandberg@arm.com unsigned int drain(DrainManager *drain_manager); 1279342SAndreas.Sandberg@arm.com void drainResume(); 1282623SN/A 1292798Sktlim@umich.edu void switchOut(); 1302623SN/A void takeOverFrom(BaseCPU *oldCPU); 1312623SN/A 1329180Sandreas.hansson@arm.com virtual void activateContext(ThreadID thread_num, Cycles delay); 1338737Skoansin.tan@gmail.com virtual void suspendContext(ThreadID thread_num); 1342623SN/A 1358444Sgblack@eecs.umich.edu Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 1367520Sgblack@eecs.umich.edu 1378444Sgblack@eecs.umich.edu Fault writeMem(uint8_t *data, unsigned size, 1388444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res); 1397520Sgblack@eecs.umich.edu 1405315Sstever@gmail.com /** 1415315Sstever@gmail.com * Print state of address in memory system via PrintReq (for 1425315Sstever@gmail.com * debugging). 1435315Sstever@gmail.com */ 1445315Sstever@gmail.com void printAddr(Addr a); 1452623SN/A}; 1462623SN/A 1472623SN/A#endif // __CPU_SIMPLE_ATOMIC_HH__ 148