atomic.hh revision 8737
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 312623SN/A#ifndef __CPU_SIMPLE_ATOMIC_HH__ 322623SN/A#define __CPU_SIMPLE_ATOMIC_HH__ 332623SN/A 342623SN/A#include "cpu/simple/base.hh" 355529Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 362623SN/A 372623SN/Aclass AtomicSimpleCPU : public BaseSimpleCPU 382623SN/A{ 392623SN/A public: 402623SN/A 415529Snate@binkert.org AtomicSimpleCPU(AtomicSimpleCPUParams *params); 422623SN/A virtual ~AtomicSimpleCPU(); 432623SN/A 442623SN/A virtual void init(); 452623SN/A 462623SN/A private: 472623SN/A 482623SN/A struct TickEvent : public Event 492623SN/A { 502623SN/A AtomicSimpleCPU *cpu; 512623SN/A 522623SN/A TickEvent(AtomicSimpleCPU *c); 532623SN/A void process(); 545336Shines@cs.fsu.edu const char *description() const; 552623SN/A }; 562623SN/A 572623SN/A TickEvent tickEvent; 582623SN/A 592623SN/A const int width; 606078Sgblack@eecs.umich.edu bool locked; 615487Snate@binkert.org const bool simulate_data_stalls; 625487Snate@binkert.org const bool simulate_inst_stalls; 632623SN/A 642623SN/A // main simulation loop (one cycle) 652623SN/A void tick(); 662623SN/A 678707Sandreas.hansson@arm.com /** 688707Sandreas.hansson@arm.com * An AtomicCPUPort overrides the default behaviour of the 698707Sandreas.hansson@arm.com * recvAtomic and ignores the packet instead of panicking. 708707Sandreas.hansson@arm.com */ 718707Sandreas.hansson@arm.com class AtomicCPUPort : public CpuPort 722623SN/A { 738707Sandreas.hansson@arm.com 742623SN/A public: 752623SN/A 768707Sandreas.hansson@arm.com AtomicCPUPort(const std::string &_name, BaseCPU* _cpu) 778707Sandreas.hansson@arm.com : CpuPort(_name, _cpu) 782623SN/A { } 792623SN/A 802623SN/A protected: 812623SN/A 828707Sandreas.hansson@arm.com virtual Tick recvAtomic(PacketPtr pkt) 838707Sandreas.hansson@arm.com { 848707Sandreas.hansson@arm.com // Snooping a coherence request, just return 858707Sandreas.hansson@arm.com return 0; 868707Sandreas.hansson@arm.com } 873192Srdreslin@umich.edu 882623SN/A }; 894192Sktlim@umich.edu 908707Sandreas.hansson@arm.com AtomicCPUPort icachePort; 918707Sandreas.hansson@arm.com AtomicCPUPort dcachePort; 922623SN/A 934968Sacolyte@umich.edu CpuPort physmemPort; 944968Sacolyte@umich.edu bool hasPhysMemPort; 954870Sstever@eecs.umich.edu Request ifetch_req; 964870Sstever@eecs.umich.edu Request data_read_req; 974870Sstever@eecs.umich.edu Request data_write_req; 982623SN/A 992623SN/A bool dcache_access; 1002662Sstever@eecs.umich.edu Tick dcache_latency; 1012623SN/A 1024968Sacolyte@umich.edu Range<Addr> physMemAddr; 1034968Sacolyte@umich.edu 1042623SN/A public: 1052623SN/A 1062856Srdreslin@umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 1072856Srdreslin@umich.edu 1082623SN/A virtual void serialize(std::ostream &os); 1092623SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1102915Sktlim@umich.edu virtual void resume(); 1112623SN/A 1122798Sktlim@umich.edu void switchOut(); 1132623SN/A void takeOverFrom(BaseCPU *oldCPU); 1142623SN/A 1158737Skoansin.tan@gmail.com virtual void activateContext(ThreadID thread_num, int delay); 1168737Skoansin.tan@gmail.com virtual void suspendContext(ThreadID thread_num); 1172623SN/A 1188444Sgblack@eecs.umich.edu Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 1197520Sgblack@eecs.umich.edu 1208444Sgblack@eecs.umich.edu Fault writeMem(uint8_t *data, unsigned size, 1218444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res); 1227520Sgblack@eecs.umich.edu 1235315Sstever@gmail.com /** 1245315Sstever@gmail.com * Print state of address in memory system via PrintReq (for 1255315Sstever@gmail.com * debugging). 1265315Sstever@gmail.com */ 1275315Sstever@gmail.com void printAddr(Addr a); 1282623SN/A}; 1292623SN/A 1302623SN/A#endif // __CPU_SIMPLE_ATOMIC_HH__ 131