atomic.cc revision 5001 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/mmaped_ipr.hh"
33#include "arch/utility.hh"
34#include "base/bigint.hh"
35#include "cpu/exetrace.hh"
36#include "cpu/simple/atomic.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "params/AtomicSimpleCPU.hh"
40#include "sim/system.hh"
41
42using namespace std;
43using namespace TheISA;
44
45AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
46    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
47{
48}
49
50
51void
52AtomicSimpleCPU::TickEvent::process()
53{
54    cpu->tick();
55}
56
57const char *
58AtomicSimpleCPU::TickEvent::description()
59{
60    return "AtomicSimpleCPU tick";
61}
62
63Port *
64AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
65{
66    if (if_name == "dcache_port")
67        return &dcachePort;
68    else if (if_name == "icache_port")
69        return &icachePort;
70    else if (if_name == "physmem_port") {
71        hasPhysMemPort = true;
72        return &physmemPort;
73    }
74    else
75        panic("No Such Port\n");
76}
77
78void
79AtomicSimpleCPU::init()
80{
81    BaseCPU::init();
82#if FULL_SYSTEM
83    for (int i = 0; i < threadContexts.size(); ++i) {
84        ThreadContext *tc = threadContexts[i];
85
86        // initialize CPU, including PC
87        TheISA::initCPU(tc, tc->readCpuId());
88    }
89#endif
90    if (hasPhysMemPort) {
91        bool snoop = false;
92        AddrRangeList pmAddrList;
93        physmemPort.getPeerAddressRanges(pmAddrList, snoop);
94        physMemAddr = *pmAddrList.begin();
95    }
96}
97
98bool
99AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
100{
101    panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
102    return true;
103}
104
105Tick
106AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
107{
108    //Snooping a coherence request, just return
109    return 0;
110}
111
112void
113AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
114{
115    //No internal storage to update, just return
116    return;
117}
118
119void
120AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
121{
122    if (status == RangeChange) {
123        if (!snoopRangeSent) {
124            snoopRangeSent = true;
125            sendStatusChange(Port::RangeChange);
126        }
127        return;
128    }
129
130    panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
131}
132
133void
134AtomicSimpleCPU::CpuPort::recvRetry()
135{
136    panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
137}
138
139void
140AtomicSimpleCPU::DcachePort::setPeer(Port *port)
141{
142    Port::setPeer(port);
143
144#if FULL_SYSTEM
145    // Update the ThreadContext's memory ports (Functional/Virtual
146    // Ports)
147    cpu->tcBase()->connectMemPorts();
148#endif
149}
150
151AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
152    : BaseSimpleCPU(p), tickEvent(this),
153      width(p->width), simulate_stalls(p->simulate_stalls),
154      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
155      physmemPort(name() + "-iport", this), hasPhysMemPort(false)
156{
157    _status = Idle;
158
159    icachePort.snoopRangeSent = false;
160    dcachePort.snoopRangeSent = false;
161
162    ifetch_req.setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
163    data_read_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too
164    data_write_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too
165}
166
167
168AtomicSimpleCPU::~AtomicSimpleCPU()
169{
170}
171
172void
173AtomicSimpleCPU::serialize(ostream &os)
174{
175    SimObject::State so_state = SimObject::getState();
176    SERIALIZE_ENUM(so_state);
177    Status _status = status();
178    SERIALIZE_ENUM(_status);
179    BaseSimpleCPU::serialize(os);
180    nameOut(os, csprintf("%s.tickEvent", name()));
181    tickEvent.serialize(os);
182}
183
184void
185AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
186{
187    SimObject::State so_state;
188    UNSERIALIZE_ENUM(so_state);
189    UNSERIALIZE_ENUM(_status);
190    BaseSimpleCPU::unserialize(cp, section);
191    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
192}
193
194void
195AtomicSimpleCPU::resume()
196{
197    DPRINTF(SimpleCPU, "Resume\n");
198    if (_status != SwitchedOut && _status != Idle) {
199        assert(system->getMemoryMode() == Enums::atomic);
200
201        changeState(SimObject::Running);
202        if (thread->status() == ThreadContext::Active) {
203            if (!tickEvent.scheduled()) {
204                tickEvent.schedule(nextCycle());
205            }
206        }
207    }
208}
209
210void
211AtomicSimpleCPU::switchOut()
212{
213    assert(status() == Running || status() == Idle);
214    _status = SwitchedOut;
215
216    tickEvent.squash();
217}
218
219
220void
221AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
222{
223    BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
224
225    assert(!tickEvent.scheduled());
226
227    // if any of this CPU's ThreadContexts are active, mark the CPU as
228    // running and schedule its tick event.
229    for (int i = 0; i < threadContexts.size(); ++i) {
230        ThreadContext *tc = threadContexts[i];
231        if (tc->status() == ThreadContext::Active && _status != Running) {
232            _status = Running;
233            tickEvent.schedule(nextCycle());
234            break;
235        }
236    }
237    if (_status != Running) {
238        _status = Idle;
239    }
240}
241
242
243void
244AtomicSimpleCPU::activateContext(int thread_num, int delay)
245{
246    DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
247
248    assert(thread_num == 0);
249    assert(thread);
250
251    assert(_status == Idle);
252    assert(!tickEvent.scheduled());
253
254    notIdleFraction++;
255
256    //Make sure ticks are still on multiples of cycles
257    tickEvent.schedule(nextCycle(curTick + cycles(delay)));
258    _status = Running;
259}
260
261
262void
263AtomicSimpleCPU::suspendContext(int thread_num)
264{
265    DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
266
267    assert(thread_num == 0);
268    assert(thread);
269
270    assert(_status == Running);
271
272    // tick event may not be scheduled if this gets called from inside
273    // an instruction's execution, e.g. "quiesce"
274    if (tickEvent.scheduled())
275        tickEvent.deschedule();
276
277    notIdleFraction--;
278    _status = Idle;
279}
280
281
282template <class T>
283Fault
284AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
285{
286    // use the CPU's statically allocated read request and packet objects
287    Request *req = &data_read_req;
288
289    if (traceData) {
290        traceData->setAddr(addr);
291    }
292
293    //The block size of our peer.
294    int blockSize = dcachePort.peerBlockSize();
295    //The size of the data we're trying to read.
296    int dataSize = sizeof(T);
297
298    uint8_t * dataPtr = (uint8_t *)&data;
299
300    //The address of the second part of this access if it needs to be split
301    //across a cache line boundary.
302    Addr secondAddr = roundDown(addr + dataSize - 1, blockSize);
303
304    if(secondAddr > addr)
305        dataSize = secondAddr - addr;
306
307    dcache_latency = 0;
308
309    while(1) {
310        req->setVirt(0, addr, dataSize, flags, thread->readPC());
311
312        // translate to physical address
313        Fault fault = thread->translateDataReadReq(req);
314
315        // Now do the access.
316        if (fault == NoFault) {
317            Packet pkt = Packet(req,
318                    req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
319                    Packet::Broadcast);
320            pkt.dataStatic(dataPtr);
321
322            if (req->isMmapedIpr())
323                dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
324            else {
325                if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
326                    dcache_latency += physmemPort.sendAtomic(&pkt);
327                else
328                    dcache_latency += dcachePort.sendAtomic(&pkt);
329            }
330            dcache_access = true;
331            assert(!pkt.isError());
332
333            if (req->isLocked()) {
334                TheISA::handleLockedRead(thread, req);
335            }
336        }
337
338        // This will need a new way to tell if it has a dcache attached.
339        if (req->isUncacheable())
340            recordEvent("Uncached Read");
341
342        //If there's a fault, return it
343        if (fault != NoFault)
344            return fault;
345        //If we don't need to access a second cache line, stop now.
346        if (secondAddr <= addr)
347        {
348            data = gtoh(data);
349            return fault;
350        }
351
352        /*
353         * Set up for accessing the second cache line.
354         */
355
356        //Move the pointer we're reading into to the correct location.
357        dataPtr += dataSize;
358        //Adjust the size to get the remaining bytes.
359        dataSize = addr + sizeof(T) - secondAddr;
360        //And access the right address.
361        addr = secondAddr;
362    }
363}
364
365#ifndef DOXYGEN_SHOULD_SKIP_THIS
366
367template
368Fault
369AtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
370
371template
372Fault
373AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
374
375template
376Fault
377AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
378
379template
380Fault
381AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
382
383template
384Fault
385AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
386
387template
388Fault
389AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
390
391#endif //DOXYGEN_SHOULD_SKIP_THIS
392
393template<>
394Fault
395AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
396{
397    return read(addr, *(uint64_t*)&data, flags);
398}
399
400template<>
401Fault
402AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
403{
404    return read(addr, *(uint32_t*)&data, flags);
405}
406
407
408template<>
409Fault
410AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
411{
412    return read(addr, (uint32_t&)data, flags);
413}
414
415
416template <class T>
417Fault
418AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
419{
420    // use the CPU's statically allocated write request and packet objects
421    Request *req = &data_write_req;
422
423    if (traceData) {
424        traceData->setAddr(addr);
425    }
426
427    //The block size of our peer.
428    int blockSize = dcachePort.peerBlockSize();
429    //The size of the data we're trying to read.
430    int dataSize = sizeof(T);
431
432    uint8_t * dataPtr = (uint8_t *)&data;
433
434    //The address of the second part of this access if it needs to be split
435    //across a cache line boundary.
436    Addr secondAddr = roundDown(addr + dataSize - 1, blockSize);
437
438    if(secondAddr > addr)
439        dataSize = secondAddr - addr;
440
441    dcache_latency = 0;
442
443    while(1) {
444        req->setVirt(0, addr, dataSize, flags, thread->readPC());
445
446        // translate to physical address
447        Fault fault = thread->translateDataWriteReq(req);
448
449        // Now do the access.
450        if (fault == NoFault) {
451            MemCmd cmd = MemCmd::WriteReq; // default
452            bool do_access = true;  // flag to suppress cache access
453
454            if (req->isLocked()) {
455                cmd = MemCmd::StoreCondReq;
456                do_access = TheISA::handleLockedWrite(thread, req);
457            } else if (req->isSwap()) {
458                cmd = MemCmd::SwapReq;
459                if (req->isCondSwap()) {
460                    assert(res);
461                    req->setExtraData(*res);
462                }
463            }
464
465            if (do_access) {
466                Packet pkt = Packet(req, cmd, Packet::Broadcast);
467                pkt.dataStatic(dataPtr);
468
469                if (req->isMmapedIpr()) {
470                    dcache_latency +=
471                        TheISA::handleIprWrite(thread->getTC(), &pkt);
472                } else {
473                    //XXX This needs to be outside of the loop in order to
474                    //work properly for cache line boundary crossing
475                    //accesses in transendian simulations.
476                    data = htog(data);
477                    if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
478                        dcache_latency += physmemPort.sendAtomic(&pkt);
479                    else
480                        dcache_latency += dcachePort.sendAtomic(&pkt);
481                }
482                dcache_access = true;
483                assert(!pkt.isError());
484
485                if (req->isSwap()) {
486                    assert(res);
487                    *res = pkt.get<T>();
488                }
489            }
490
491            if (res && !req->isSwap()) {
492                *res = req->getExtraData();
493            }
494        }
495
496        // This will need a new way to tell if it's hooked up to a cache or not.
497        if (req->isUncacheable())
498            recordEvent("Uncached Write");
499
500        //If there's a fault or we don't need to access a second cache line,
501        //stop now.
502        if (fault != NoFault || secondAddr <= addr)
503        {
504            // If the write needs to have a fault on the access, consider
505            // calling changeStatus() and changing it to "bad addr write"
506            // or something.
507            return fault;
508        }
509
510        /*
511         * Set up for accessing the second cache line.
512         */
513
514        //Move the pointer we're reading into to the correct location.
515        dataPtr += dataSize;
516        //Adjust the size to get the remaining bytes.
517        dataSize = addr + sizeof(T) - secondAddr;
518        //And access the right address.
519        addr = secondAddr;
520    }
521}
522
523
524#ifndef DOXYGEN_SHOULD_SKIP_THIS
525
526template
527Fault
528AtomicSimpleCPU::write(Twin32_t data, Addr addr,
529                       unsigned flags, uint64_t *res);
530
531template
532Fault
533AtomicSimpleCPU::write(Twin64_t data, Addr addr,
534                       unsigned flags, uint64_t *res);
535
536template
537Fault
538AtomicSimpleCPU::write(uint64_t data, Addr addr,
539                       unsigned flags, uint64_t *res);
540
541template
542Fault
543AtomicSimpleCPU::write(uint32_t data, Addr addr,
544                       unsigned flags, uint64_t *res);
545
546template
547Fault
548AtomicSimpleCPU::write(uint16_t data, Addr addr,
549                       unsigned flags, uint64_t *res);
550
551template
552Fault
553AtomicSimpleCPU::write(uint8_t data, Addr addr,
554                       unsigned flags, uint64_t *res);
555
556#endif //DOXYGEN_SHOULD_SKIP_THIS
557
558template<>
559Fault
560AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
561{
562    return write(*(uint64_t*)&data, addr, flags, res);
563}
564
565template<>
566Fault
567AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
568{
569    return write(*(uint32_t*)&data, addr, flags, res);
570}
571
572
573template<>
574Fault
575AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
576{
577    return write((uint32_t)data, addr, flags, res);
578}
579
580
581void
582AtomicSimpleCPU::tick()
583{
584    DPRINTF(SimpleCPU, "Tick\n");
585
586    Tick latency = cycles(1); // instruction takes one cycle by default
587
588    for (int i = 0; i < width; ++i) {
589        numCycles++;
590
591        if (!curStaticInst || !curStaticInst->isDelayedCommit())
592            checkForInterrupts();
593
594        Fault fault = setupFetchRequest(&ifetch_req);
595
596        if (fault == NoFault) {
597            Tick icache_latency = 0;
598            bool icache_access = false;
599            dcache_access = false; // assume no dcache access
600
601            //Fetch more instruction memory if necessary
602            //if(predecoder.needMoreBytes())
603            //{
604                icache_access = true;
605                Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
606                                           Packet::Broadcast);
607                ifetch_pkt.dataStatic(&inst);
608
609                if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
610                    icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
611                else
612                    icache_latency = icachePort.sendAtomic(&ifetch_pkt);
613
614
615                // ifetch_req is initialized to read the instruction directly
616                // into the CPU object's inst field.
617            //}
618
619            preExecute();
620
621            if (curStaticInst) {
622                fault = curStaticInst->execute(this, traceData);
623
624                // keep an instruction count
625                if (fault == NoFault)
626                    countInst();
627                else if (traceData) {
628                    // If there was a fault, we should trace this instruction.
629                    delete traceData;
630                    traceData = NULL;
631                }
632
633                postExecute();
634            }
635
636            // @todo remove me after debugging with legion done
637            if (curStaticInst && (!curStaticInst->isMicroop() ||
638                        curStaticInst->isFirstMicroop()))
639                instCnt++;
640
641            if (simulate_stalls) {
642                Tick icache_stall =
643                    icache_access ? icache_latency - cycles(1) : 0;
644                Tick dcache_stall =
645                    dcache_access ? dcache_latency - cycles(1) : 0;
646                Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
647                if (cycles(stall_cycles) < (icache_stall + dcache_stall))
648                    latency += cycles(stall_cycles+1);
649                else
650                    latency += cycles(stall_cycles);
651            }
652
653        }
654        if(fault != NoFault || !stayAtPC)
655            advancePC(fault);
656    }
657
658    if (_status != Idle)
659        tickEvent.schedule(curTick + latency);
660}
661
662
663////////////////////////////////////////////////////////////////////////
664//
665//  AtomicSimpleCPU Simulation Object
666//
667AtomicSimpleCPU *
668AtomicSimpleCPUParams::create()
669{
670    AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
671    params->name = name;
672    params->numberOfThreads = 1;
673    params->max_insts_any_thread = max_insts_any_thread;
674    params->max_insts_all_threads = max_insts_all_threads;
675    params->max_loads_any_thread = max_loads_any_thread;
676    params->max_loads_all_threads = max_loads_all_threads;
677    params->progress_interval = progress_interval;
678    params->deferRegistration = defer_registration;
679    params->phase = phase;
680    params->clock = clock;
681    params->functionTrace = function_trace;
682    params->functionTraceStart = function_trace_start;
683    params->width = width;
684    params->simulate_stalls = simulate_stalls;
685    params->system = system;
686    params->cpu_id = cpu_id;
687    params->tracer = tracer;
688
689    params->itb = itb;
690    params->dtb = dtb;
691#if FULL_SYSTEM
692    params->profile = profile;
693    params->do_quiesce = do_quiesce;
694    params->do_checkpoint_insts = do_checkpoint_insts;
695    params->do_statistics_insts = do_statistics_insts;
696#else
697    if (workload.size() != 1)
698        panic("only one workload allowed");
699    params->process = workload[0];
700#endif
701
702    AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
703    return cpu;
704}
705