atomic.cc revision 4052 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/mmaped_ipr.hh"
33#include "arch/utility.hh"
34#include "base/bigint.hh"
35#include "cpu/exetrace.hh"
36#include "cpu/simple/atomic.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "sim/builder.hh"
40#include "sim/system.hh"
41
42using namespace std;
43using namespace TheISA;
44
45AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
46    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
47{
48}
49
50
51void
52AtomicSimpleCPU::TickEvent::process()
53{
54    cpu->tick();
55}
56
57const char *
58AtomicSimpleCPU::TickEvent::description()
59{
60    return "AtomicSimpleCPU tick event";
61}
62
63Port *
64AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
65{
66    if (if_name == "dcache_port")
67        return &dcachePort;
68    else if (if_name == "icache_port")
69        return &icachePort;
70    else
71        panic("No Such Port\n");
72}
73
74void
75AtomicSimpleCPU::init()
76{
77    BaseCPU::init();
78#if FULL_SYSTEM
79    for (int i = 0; i < threadContexts.size(); ++i) {
80        ThreadContext *tc = threadContexts[i];
81
82        // initialize CPU, including PC
83        TheISA::initCPU(tc, tc->readCpuId());
84    }
85#endif
86}
87
88bool
89AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
90{
91    panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
92    return true;
93}
94
95Tick
96AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
97{
98    //Snooping a coherence request, just return
99    return 0;
100}
101
102void
103AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
104{
105    //No internal storage to update, just return
106    return;
107}
108
109void
110AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
111{
112    if (status == RangeChange) {
113        if (!snoopRangeSent) {
114            snoopRangeSent = true;
115            sendStatusChange(Port::RangeChange);
116        }
117        return;
118    }
119
120    panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
121}
122
123void
124AtomicSimpleCPU::CpuPort::recvRetry()
125{
126    panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
127}
128
129
130AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
131    : BaseSimpleCPU(p), tickEvent(this),
132      width(p->width), simulate_stalls(p->simulate_stalls),
133      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
134{
135    _status = Idle;
136
137    icachePort.snoopRangeSent = false;
138    dcachePort.snoopRangeSent = false;
139
140    ifetch_req = new Request();
141    ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
142    ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
143    ifetch_pkt->dataStatic(&inst);
144
145    data_read_req = new Request();
146    data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
147    data_read_pkt = new Packet(data_read_req, MemCmd::ReadReq,
148                               Packet::Broadcast);
149    data_read_pkt->dataStatic(&dataReg);
150
151    data_write_req = new Request();
152    data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
153    data_write_pkt = new Packet(data_write_req, MemCmd::WriteReq,
154                                Packet::Broadcast);
155    data_swap_pkt = new Packet(data_write_req, MemCmd::SwapReq,
156                                Packet::Broadcast);
157}
158
159
160AtomicSimpleCPU::~AtomicSimpleCPU()
161{
162}
163
164void
165AtomicSimpleCPU::serialize(ostream &os)
166{
167    SimObject::State so_state = SimObject::getState();
168    SERIALIZE_ENUM(so_state);
169    Status _status = status();
170    SERIALIZE_ENUM(_status);
171    BaseSimpleCPU::serialize(os);
172    nameOut(os, csprintf("%s.tickEvent", name()));
173    tickEvent.serialize(os);
174}
175
176void
177AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
178{
179    SimObject::State so_state;
180    UNSERIALIZE_ENUM(so_state);
181    UNSERIALIZE_ENUM(_status);
182    BaseSimpleCPU::unserialize(cp, section);
183    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
184}
185
186void
187AtomicSimpleCPU::resume()
188{
189    if (_status != SwitchedOut && _status != Idle) {
190        assert(system->getMemoryMode() == System::Atomic);
191
192        changeState(SimObject::Running);
193        if (thread->status() == ThreadContext::Active) {
194            if (!tickEvent.scheduled()) {
195                tickEvent.schedule(nextCycle());
196            }
197        }
198    }
199}
200
201void
202AtomicSimpleCPU::switchOut()
203{
204    assert(status() == Running || status() == Idle);
205    _status = SwitchedOut;
206
207    tickEvent.squash();
208}
209
210
211void
212AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
213{
214    BaseCPU::takeOverFrom(oldCPU);
215
216    assert(!tickEvent.scheduled());
217
218    // if any of this CPU's ThreadContexts are active, mark the CPU as
219    // running and schedule its tick event.
220    for (int i = 0; i < threadContexts.size(); ++i) {
221        ThreadContext *tc = threadContexts[i];
222        if (tc->status() == ThreadContext::Active && _status != Running) {
223            _status = Running;
224            tickEvent.schedule(nextCycle());
225            break;
226        }
227    }
228    if (_status != Running) {
229        _status = Idle;
230    }
231}
232
233
234void
235AtomicSimpleCPU::activateContext(int thread_num, int delay)
236{
237    assert(thread_num == 0);
238    assert(thread);
239
240    assert(_status == Idle);
241    assert(!tickEvent.scheduled());
242
243    notIdleFraction++;
244
245#if FULL_SYSTEM
246    // Connect the ThreadContext's memory ports (Functional/Virtual
247    // Ports)
248    tc->connectMemPorts();
249#endif
250
251    //Make sure ticks are still on multiples of cycles
252    tickEvent.schedule(nextCycle(curTick + cycles(delay)));
253    _status = Running;
254}
255
256
257void
258AtomicSimpleCPU::suspendContext(int thread_num)
259{
260    assert(thread_num == 0);
261    assert(thread);
262
263    assert(_status == Running);
264
265    // tick event may not be scheduled if this gets called from inside
266    // an instruction's execution, e.g. "quiesce"
267    if (tickEvent.scheduled())
268        tickEvent.deschedule();
269
270    notIdleFraction--;
271    _status = Idle;
272}
273
274
275template <class T>
276Fault
277AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
278{
279    // use the CPU's statically allocated read request and packet objects
280    Request *req = data_read_req;
281    PacketPtr pkt = data_read_pkt;
282
283    req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
284
285    if (traceData) {
286        traceData->setAddr(addr);
287    }
288
289    // translate to physical address
290    Fault fault = thread->translateDataReadReq(req);
291
292    // Now do the access.
293    if (fault == NoFault) {
294        pkt->reinitFromRequest();
295
296        if (req->isMmapedIpr())
297            dcache_latency = TheISA::handleIprRead(thread->getTC(),pkt);
298        else
299            dcache_latency = dcachePort.sendAtomic(pkt);
300        dcache_access = true;
301#if !defined(NDEBUG)
302        if (pkt->result != Packet::Success)
303            panic("Unable to find responder for address pa = %#X va = %#X\n",
304                    pkt->req->getPaddr(), pkt->req->getVaddr());
305#endif
306        data = pkt->get<T>();
307
308        if (req->isLocked()) {
309            TheISA::handleLockedRead(thread, req);
310        }
311    }
312
313    // This will need a new way to tell if it has a dcache attached.
314    if (req->isUncacheable())
315        recordEvent("Uncached Read");
316
317    return fault;
318}
319
320#ifndef DOXYGEN_SHOULD_SKIP_THIS
321
322template
323Fault
324AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
325
326template
327Fault
328AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
329
330template
331Fault
332AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
333
334template
335Fault
336AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
337
338template
339Fault
340AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
341
342#endif //DOXYGEN_SHOULD_SKIP_THIS
343
344template<>
345Fault
346AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
347{
348    return read(addr, *(uint64_t*)&data, flags);
349}
350
351template<>
352Fault
353AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
354{
355    return read(addr, *(uint32_t*)&data, flags);
356}
357
358
359template<>
360Fault
361AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
362{
363    return read(addr, (uint32_t&)data, flags);
364}
365
366
367template <class T>
368Fault
369AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
370{
371    // use the CPU's statically allocated write request and packet objects
372    Request *req = data_write_req;
373    PacketPtr pkt;
374
375    req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
376
377    if (req->isSwap())
378        pkt = data_swap_pkt;
379    else
380        pkt = data_write_pkt;
381
382    if (traceData) {
383        traceData->setAddr(addr);
384    }
385
386    // translate to physical address
387    Fault fault = thread->translateDataWriteReq(req);
388
389    // Now do the access.
390    if (fault == NoFault) {
391        bool do_access = true;  // flag to suppress cache access
392
393        if (req->isLocked()) {
394            do_access = TheISA::handleLockedWrite(thread, req);
395        }
396        if (req->isCondSwap()) {
397             assert(res);
398             req->setExtraData(*res);
399        }
400
401
402        if (do_access) {
403            pkt->reinitFromRequest();
404            pkt->dataStatic(&data);
405
406            if (req->isMmapedIpr()) {
407                dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt);
408            } else {
409                data = htog(data);
410                dcache_latency = dcachePort.sendAtomic(pkt);
411            }
412            dcache_access = true;
413
414#if !defined(NDEBUG)
415            if (pkt->result != Packet::Success)
416                panic("Unable to find responder for address pa = %#X va = %#X\n",
417                        pkt->req->getPaddr(), pkt->req->getVaddr());
418#endif
419        }
420
421        if (req->isSwap()) {
422            assert(res);
423            *res = pkt->get<T>();
424        } else if (res) {
425            *res = req->getExtraData();
426        }
427    }
428
429    // This will need a new way to tell if it's hooked up to a cache or not.
430    if (req->isUncacheable())
431        recordEvent("Uncached Write");
432
433    // If the write needs to have a fault on the access, consider calling
434    // changeStatus() and changing it to "bad addr write" or something.
435    return fault;
436}
437
438
439#ifndef DOXYGEN_SHOULD_SKIP_THIS
440template
441Fault
442AtomicSimpleCPU::write(uint64_t data, Addr addr,
443                       unsigned flags, uint64_t *res);
444
445template
446Fault
447AtomicSimpleCPU::write(uint32_t data, Addr addr,
448                       unsigned flags, uint64_t *res);
449
450template
451Fault
452AtomicSimpleCPU::write(uint16_t data, Addr addr,
453                       unsigned flags, uint64_t *res);
454
455template
456Fault
457AtomicSimpleCPU::write(uint8_t data, Addr addr,
458                       unsigned flags, uint64_t *res);
459
460#endif //DOXYGEN_SHOULD_SKIP_THIS
461
462template<>
463Fault
464AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
465{
466    return write(*(uint64_t*)&data, addr, flags, res);
467}
468
469template<>
470Fault
471AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
472{
473    return write(*(uint32_t*)&data, addr, flags, res);
474}
475
476
477template<>
478Fault
479AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
480{
481    return write((uint32_t)data, addr, flags, res);
482}
483
484
485void
486AtomicSimpleCPU::tick()
487{
488    Tick latency = cycles(1); // instruction takes one cycle by default
489
490    for (int i = 0; i < width; ++i) {
491        numCycles++;
492
493        if (!curStaticInst || !curStaticInst->isDelayedCommit())
494            checkForInterrupts();
495
496        Fault fault = setupFetchRequest(ifetch_req);
497
498        if (fault == NoFault) {
499            ifetch_pkt->reinitFromRequest();
500
501            Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
502            // ifetch_req is initialized to read the instruction directly
503            // into the CPU object's inst field.
504
505            dcache_access = false; // assume no dcache access
506            preExecute();
507
508            fault = curStaticInst->execute(this, traceData);
509            postExecute();
510
511            // @todo remove me after debugging with legion done
512            if (curStaticInst && (!curStaticInst->isMicroOp() ||
513                        curStaticInst->isFirstMicroOp()))
514                instCnt++;
515
516            if (simulate_stalls) {
517                Tick icache_stall = icache_latency - cycles(1);
518                Tick dcache_stall =
519                    dcache_access ? dcache_latency - cycles(1) : 0;
520                Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
521                if (cycles(stall_cycles) < (icache_stall + dcache_stall))
522                    latency += cycles(stall_cycles+1);
523                else
524                    latency += cycles(stall_cycles);
525            }
526
527        }
528
529        advancePC(fault);
530    }
531
532    if (_status != Idle)
533        tickEvent.schedule(curTick + latency);
534}
535
536
537////////////////////////////////////////////////////////////////////////
538//
539//  AtomicSimpleCPU Simulation Object
540//
541BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
542
543    Param<Counter> max_insts_any_thread;
544    Param<Counter> max_insts_all_threads;
545    Param<Counter> max_loads_any_thread;
546    Param<Counter> max_loads_all_threads;
547    Param<Tick> progress_interval;
548    SimObjectParam<System *> system;
549    Param<int> cpu_id;
550
551#if FULL_SYSTEM
552    SimObjectParam<TheISA::ITB *> itb;
553    SimObjectParam<TheISA::DTB *> dtb;
554    Param<Tick> profile;
555
556    Param<bool> do_quiesce;
557    Param<bool> do_checkpoint_insts;
558    Param<bool> do_statistics_insts;
559#else
560    SimObjectParam<Process *> workload;
561#endif // FULL_SYSTEM
562
563    Param<int> clock;
564    Param<int> phase;
565
566    Param<bool> defer_registration;
567    Param<int> width;
568    Param<bool> function_trace;
569    Param<Tick> function_trace_start;
570    Param<bool> simulate_stalls;
571
572END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
573
574BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
575
576    INIT_PARAM(max_insts_any_thread,
577               "terminate when any thread reaches this inst count"),
578    INIT_PARAM(max_insts_all_threads,
579               "terminate when all threads have reached this inst count"),
580    INIT_PARAM(max_loads_any_thread,
581               "terminate when any thread reaches this load count"),
582    INIT_PARAM(max_loads_all_threads,
583               "terminate when all threads have reached this load count"),
584    INIT_PARAM(progress_interval, "Progress interval"),
585    INIT_PARAM(system, "system object"),
586    INIT_PARAM(cpu_id, "processor ID"),
587
588#if FULL_SYSTEM
589    INIT_PARAM(itb, "Instruction TLB"),
590    INIT_PARAM(dtb, "Data TLB"),
591    INIT_PARAM(profile, ""),
592    INIT_PARAM(do_quiesce, ""),
593    INIT_PARAM(do_checkpoint_insts, ""),
594    INIT_PARAM(do_statistics_insts, ""),
595#else
596    INIT_PARAM(workload, "processes to run"),
597#endif // FULL_SYSTEM
598
599    INIT_PARAM(clock, "clock speed"),
600    INIT_PARAM_DFLT(phase, "clock phase", 0),
601    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
602    INIT_PARAM(width, "cpu width"),
603    INIT_PARAM(function_trace, "Enable function trace"),
604    INIT_PARAM(function_trace_start, "Cycle to start function trace"),
605    INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
606
607END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
608
609
610CREATE_SIM_OBJECT(AtomicSimpleCPU)
611{
612    AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
613    params->name = getInstanceName();
614    params->numberOfThreads = 1;
615    params->max_insts_any_thread = max_insts_any_thread;
616    params->max_insts_all_threads = max_insts_all_threads;
617    params->max_loads_any_thread = max_loads_any_thread;
618    params->max_loads_all_threads = max_loads_all_threads;
619    params->progress_interval = progress_interval;
620    params->deferRegistration = defer_registration;
621    params->phase = phase;
622    params->clock = clock;
623    params->functionTrace = function_trace;
624    params->functionTraceStart = function_trace_start;
625    params->width = width;
626    params->simulate_stalls = simulate_stalls;
627    params->system = system;
628    params->cpu_id = cpu_id;
629
630#if FULL_SYSTEM
631    params->itb = itb;
632    params->dtb = dtb;
633    params->profile = profile;
634    params->do_quiesce = do_quiesce;
635    params->do_checkpoint_insts = do_checkpoint_insts;
636    params->do_statistics_insts = do_statistics_insts;
637#else
638    params->process = workload;
639#endif
640
641    AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
642    return cpu;
643}
644
645REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
646
647