atomic.cc revision 3661:efc80a01aeb6 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/utility.hh"
33#include "cpu/exetrace.hh"
34#include "cpu/simple/atomic.hh"
35#include "mem/packet.hh"
36#include "mem/packet_access.hh"
37#include "sim/builder.hh"
38#include "sim/system.hh"
39
40using namespace std;
41using namespace TheISA;
42
43AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
44    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
45{
46}
47
48
49void
50AtomicSimpleCPU::TickEvent::process()
51{
52    cpu->tick();
53}
54
55const char *
56AtomicSimpleCPU::TickEvent::description()
57{
58    return "AtomicSimpleCPU tick event";
59}
60
61Port *
62AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
63{
64    if (if_name == "dcache_port")
65        return &dcachePort;
66    else if (if_name == "icache_port")
67        return &icachePort;
68    else
69        panic("No Such Port\n");
70}
71
72void
73AtomicSimpleCPU::init()
74{
75    BaseCPU::init();
76#if FULL_SYSTEM
77    for (int i = 0; i < threadContexts.size(); ++i) {
78        ThreadContext *tc = threadContexts[i];
79
80        // initialize CPU, including PC
81        TheISA::initCPU(tc, tc->readCpuId());
82    }
83#endif
84}
85
86bool
87AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
88{
89    panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
90    return true;
91}
92
93Tick
94AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
95{
96    //Snooping a coherence request, just return
97    return 0;
98}
99
100void
101AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
102{
103    //No internal storage to update, just return
104    return;
105}
106
107void
108AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
109{
110    if (status == RangeChange) {
111        if (!snoopRangeSent) {
112            snoopRangeSent = true;
113            sendStatusChange(Port::RangeChange);
114        }
115        return;
116    }
117
118    panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
119}
120
121void
122AtomicSimpleCPU::CpuPort::recvRetry()
123{
124    panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
125}
126
127
128AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
129    : BaseSimpleCPU(p), tickEvent(this),
130      width(p->width), simulate_stalls(p->simulate_stalls),
131      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
132{
133    _status = Idle;
134
135    icachePort.snoopRangeSent = false;
136    dcachePort.snoopRangeSent = false;
137
138    ifetch_req = new Request();
139    ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
140    ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
141    ifetch_pkt->dataStatic(&inst);
142
143    data_read_req = new Request();
144    data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
145    data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
146                               Packet::Broadcast);
147    data_read_pkt->dataStatic(&dataReg);
148
149    data_write_req = new Request();
150    data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
151    data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
152                                Packet::Broadcast);
153}
154
155
156AtomicSimpleCPU::~AtomicSimpleCPU()
157{
158}
159
160void
161AtomicSimpleCPU::serialize(ostream &os)
162{
163    SimObject::State so_state = SimObject::getState();
164    SERIALIZE_ENUM(so_state);
165    Status _status = status();
166    SERIALIZE_ENUM(_status);
167    BaseSimpleCPU::serialize(os);
168    nameOut(os, csprintf("%s.tickEvent", name()));
169    tickEvent.serialize(os);
170}
171
172void
173AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
174{
175    SimObject::State so_state;
176    UNSERIALIZE_ENUM(so_state);
177    UNSERIALIZE_ENUM(_status);
178    BaseSimpleCPU::unserialize(cp, section);
179    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
180}
181
182void
183AtomicSimpleCPU::resume()
184{
185    if (_status != SwitchedOut && _status != Idle) {
186        assert(system->getMemoryMode() == System::Atomic);
187
188        changeState(SimObject::Running);
189        if (thread->status() == ThreadContext::Active) {
190            if (!tickEvent.scheduled()) {
191                tickEvent.schedule(nextCycle());
192            }
193        }
194    }
195}
196
197void
198AtomicSimpleCPU::switchOut()
199{
200    assert(status() == Running || status() == Idle);
201    _status = SwitchedOut;
202
203    tickEvent.squash();
204}
205
206
207void
208AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
209{
210    BaseCPU::takeOverFrom(oldCPU);
211
212    assert(!tickEvent.scheduled());
213
214    // if any of this CPU's ThreadContexts are active, mark the CPU as
215    // running and schedule its tick event.
216    for (int i = 0; i < threadContexts.size(); ++i) {
217        ThreadContext *tc = threadContexts[i];
218        if (tc->status() == ThreadContext::Active && _status != Running) {
219            _status = Running;
220            tickEvent.schedule(nextCycle());
221            break;
222        }
223    }
224    if (_status != Running) {
225        _status = Idle;
226    }
227}
228
229
230void
231AtomicSimpleCPU::activateContext(int thread_num, int delay)
232{
233    assert(thread_num == 0);
234    assert(thread);
235
236    assert(_status == Idle);
237    assert(!tickEvent.scheduled());
238
239    notIdleFraction++;
240    //Make sure ticks are still on multiples of cycles
241    tickEvent.schedule(nextCycle(curTick + cycles(delay)));
242    _status = Running;
243}
244
245
246void
247AtomicSimpleCPU::suspendContext(int thread_num)
248{
249    assert(thread_num == 0);
250    assert(thread);
251
252    assert(_status == Running);
253
254    // tick event may not be scheduled if this gets called from inside
255    // an instruction's execution, e.g. "quiesce"
256    if (tickEvent.scheduled())
257        tickEvent.deschedule();
258
259    notIdleFraction--;
260    _status = Idle;
261}
262
263
264template <class T>
265Fault
266AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
267{
268    // use the CPU's statically allocated read request and packet objects
269    Request *req = data_read_req;
270    PacketPtr pkt = data_read_pkt;
271
272    req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
273
274    if (traceData) {
275        traceData->setAddr(addr);
276    }
277
278    // translate to physical address
279    Fault fault = thread->translateDataReadReq(req);
280
281    // Now do the access.
282    if (fault == NoFault) {
283        pkt->reinitFromRequest();
284
285        dcache_latency = dcachePort.sendAtomic(pkt);
286        dcache_access = true;
287
288        assert(pkt->result == Packet::Success);
289        data = pkt->get<T>();
290
291        if (req->isLocked()) {
292            TheISA::handleLockedRead(thread, req);
293        }
294    }
295
296    // This will need a new way to tell if it has a dcache attached.
297    if (req->isUncacheable())
298        recordEvent("Uncached Read");
299
300    return fault;
301}
302
303#ifndef DOXYGEN_SHOULD_SKIP_THIS
304
305template
306Fault
307AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
308
309template
310Fault
311AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
312
313template
314Fault
315AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
316
317template
318Fault
319AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
320
321#endif //DOXYGEN_SHOULD_SKIP_THIS
322
323template<>
324Fault
325AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
326{
327    return read(addr, *(uint64_t*)&data, flags);
328}
329
330template<>
331Fault
332AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
333{
334    return read(addr, *(uint32_t*)&data, flags);
335}
336
337
338template<>
339Fault
340AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
341{
342    return read(addr, (uint32_t&)data, flags);
343}
344
345
346template <class T>
347Fault
348AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
349{
350    // use the CPU's statically allocated write request and packet objects
351    Request *req = data_write_req;
352    PacketPtr pkt = data_write_pkt;
353
354    req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
355
356    if (traceData) {
357        traceData->setAddr(addr);
358    }
359
360    // translate to physical address
361    Fault fault = thread->translateDataWriteReq(req);
362
363    // Now do the access.
364    if (fault == NoFault) {
365        bool do_access = true;  // flag to suppress cache access
366
367        if (req->isLocked()) {
368            do_access = TheISA::handleLockedWrite(thread, req);
369        }
370
371        if (do_access) {
372            data = htog(data);
373            pkt->reinitFromRequest();
374            pkt->dataStatic(&data);
375
376            dcache_latency = dcachePort.sendAtomic(pkt);
377            dcache_access = true;
378
379            assert(pkt->result == Packet::Success);
380        }
381
382        if (req->isLocked()) {
383            uint64_t scResult = req->getScResult();
384            if (scResult != 0) {
385                // clear failure counter
386                thread->setStCondFailures(0);
387            }
388            if (res) {
389                *res = req->getScResult();
390            }
391        }
392    }
393
394    // This will need a new way to tell if it's hooked up to a cache or not.
395    if (req->isUncacheable())
396        recordEvent("Uncached Write");
397
398    // If the write needs to have a fault on the access, consider calling
399    // changeStatus() and changing it to "bad addr write" or something.
400    return fault;
401}
402
403
404#ifndef DOXYGEN_SHOULD_SKIP_THIS
405template
406Fault
407AtomicSimpleCPU::write(uint64_t data, Addr addr,
408                       unsigned flags, uint64_t *res);
409
410template
411Fault
412AtomicSimpleCPU::write(uint32_t data, Addr addr,
413                       unsigned flags, uint64_t *res);
414
415template
416Fault
417AtomicSimpleCPU::write(uint16_t data, Addr addr,
418                       unsigned flags, uint64_t *res);
419
420template
421Fault
422AtomicSimpleCPU::write(uint8_t data, Addr addr,
423                       unsigned flags, uint64_t *res);
424
425#endif //DOXYGEN_SHOULD_SKIP_THIS
426
427template<>
428Fault
429AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
430{
431    return write(*(uint64_t*)&data, addr, flags, res);
432}
433
434template<>
435Fault
436AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
437{
438    return write(*(uint32_t*)&data, addr, flags, res);
439}
440
441
442template<>
443Fault
444AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
445{
446    return write((uint32_t)data, addr, flags, res);
447}
448
449
450void
451AtomicSimpleCPU::tick()
452{
453    Tick latency = cycles(1); // instruction takes one cycle by default
454
455    for (int i = 0; i < width; ++i) {
456        numCycles++;
457
458        if (!curStaticInst || !curStaticInst->isDelayedCommit())
459            checkForInterrupts();
460
461        Fault fault = setupFetchRequest(ifetch_req);
462
463        if (fault == NoFault) {
464            ifetch_pkt->reinitFromRequest();
465
466            Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
467            // ifetch_req is initialized to read the instruction directly
468            // into the CPU object's inst field.
469
470            dcache_access = false; // assume no dcache access
471            preExecute();
472            fault = curStaticInst->execute(this, traceData);
473            postExecute();
474
475            if (simulate_stalls) {
476                Tick icache_stall = icache_latency - cycles(1);
477                Tick dcache_stall =
478                    dcache_access ? dcache_latency - cycles(1) : 0;
479                Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
480                if (cycles(stall_cycles) < (icache_stall + dcache_stall))
481                    latency += cycles(stall_cycles+1);
482                else
483                    latency += cycles(stall_cycles);
484            }
485
486        }
487
488        advancePC(fault);
489    }
490
491    if (_status != Idle)
492        tickEvent.schedule(curTick + latency);
493}
494
495
496////////////////////////////////////////////////////////////////////////
497//
498//  AtomicSimpleCPU Simulation Object
499//
500BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
501
502    Param<Counter> max_insts_any_thread;
503    Param<Counter> max_insts_all_threads;
504    Param<Counter> max_loads_any_thread;
505    Param<Counter> max_loads_all_threads;
506    Param<Tick> progress_interval;
507    SimObjectParam<System *> system;
508    Param<int> cpu_id;
509
510#if FULL_SYSTEM
511    SimObjectParam<TheISA::ITB *> itb;
512    SimObjectParam<TheISA::DTB *> dtb;
513    Param<Tick> profile;
514
515    Param<bool> do_quiesce;
516    Param<bool> do_checkpoint_insts;
517    Param<bool> do_statistics_insts;
518#else
519    SimObjectParam<Process *> workload;
520#endif // FULL_SYSTEM
521
522    Param<int> clock;
523    Param<int> phase;
524
525    Param<bool> defer_registration;
526    Param<int> width;
527    Param<bool> function_trace;
528    Param<Tick> function_trace_start;
529    Param<bool> simulate_stalls;
530
531END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
532
533BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
534
535    INIT_PARAM(max_insts_any_thread,
536               "terminate when any thread reaches this inst count"),
537    INIT_PARAM(max_insts_all_threads,
538               "terminate when all threads have reached this inst count"),
539    INIT_PARAM(max_loads_any_thread,
540               "terminate when any thread reaches this load count"),
541    INIT_PARAM(max_loads_all_threads,
542               "terminate when all threads have reached this load count"),
543    INIT_PARAM(progress_interval, "Progress interval"),
544    INIT_PARAM(system, "system object"),
545    INIT_PARAM(cpu_id, "processor ID"),
546
547#if FULL_SYSTEM
548    INIT_PARAM(itb, "Instruction TLB"),
549    INIT_PARAM(dtb, "Data TLB"),
550    INIT_PARAM(profile, ""),
551    INIT_PARAM(do_quiesce, ""),
552    INIT_PARAM(do_checkpoint_insts, ""),
553    INIT_PARAM(do_statistics_insts, ""),
554#else
555    INIT_PARAM(workload, "processes to run"),
556#endif // FULL_SYSTEM
557
558    INIT_PARAM(clock, "clock speed"),
559    INIT_PARAM_DFLT(phase, "clock phase", 0),
560    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
561    INIT_PARAM(width, "cpu width"),
562    INIT_PARAM(function_trace, "Enable function trace"),
563    INIT_PARAM(function_trace_start, "Cycle to start function trace"),
564    INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
565
566END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
567
568
569CREATE_SIM_OBJECT(AtomicSimpleCPU)
570{
571    AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
572    params->name = getInstanceName();
573    params->numberOfThreads = 1;
574    params->max_insts_any_thread = max_insts_any_thread;
575    params->max_insts_all_threads = max_insts_all_threads;
576    params->max_loads_any_thread = max_loads_any_thread;
577    params->max_loads_all_threads = max_loads_all_threads;
578    params->progress_interval = progress_interval;
579    params->deferRegistration = defer_registration;
580    params->phase = phase;
581    params->clock = clock;
582    params->functionTrace = function_trace;
583    params->functionTraceStart = function_trace_start;
584    params->width = width;
585    params->simulate_stalls = simulate_stalls;
586    params->system = system;
587    params->cpu_id = cpu_id;
588
589#if FULL_SYSTEM
590    params->itb = itb;
591    params->dtb = dtb;
592    params->profile = profile;
593    params->do_quiesce = do_quiesce;
594    params->do_checkpoint_insts = do_checkpoint_insts;
595    params->do_statistics_insts = do_statistics_insts;
596#else
597    params->process = workload;
598#endif
599
600    AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
601    return cpu;
602}
603
604REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
605
606